CN111538473A - A Posit floating point processor - Google Patents

Abstract

The present application provides a Posit floating point number processor, which relates to the field of computer technology. Provide users with a floating-point processor that meets the Posit standard. The Posit floating-point number processor includes: a decoding circuit, an arithmetic circuit and an encoding circuit; the decoding circuit is used to obtain a plurality of target Posit floating-point numbers participating in the operation according to a calculation instruction of the CPU, and float the plurality of target Posit numbers. Points are converted into corresponding intermediate data in complement form; the intermediate data includes a plurality of fields: a sign field, a real exponent field, a first mantissa field and a protection bit field; the operation circuit is used for calculating the instruction according to the calculation instruction , perform operations on the received intermediate data output by the decoding circuit to obtain an operation result represented by the intermediate data in complement form; the encoding circuit is used for converting the The operation result is converted into a Position floating-point number in the specified format.

Description

A Posit floating point processor

technical field

The present application relates to the field of computer technology, and in particular to a Posit floating point number processor.

Background technique

Floating-point numbers are a common data representation method in the field of scientific computing and high-performance computing. In particular, in the occasions where the precision of calculation results is required, a large number of floating-point numbers are used for data processing, such as autonomous driving, aerospace, and mechanical computing. .

Compared with IEEE 754 standard floating-point numbers, the Posit standard floating-point numbers are more flexible, and the sampling distribution of Posit floating-point numbers on real numbers is related to the sigmoid function, which is a commonly used activation function in machine learning, so Using Posit floating point numbers for machine learning, the computer is more efficient in data processing.

However, at present, most of the floating-point number processors of commercial computers are based on the IEEE 754 standard, and there are no floating-point number processors that fully meet the Posit standard.

SUMMARY OF THE INVENTION

To solve the above problem, an embodiment of the present application provides a Posit floating-point number processor, which provides users with a floating-point number processor that satisfies the Posit standard.

The Posit floating-point number processor provided by the embodiments of the present application includes: a decoding circuit, an arithmetic circuit, and an encoding circuit;

The decoding circuit is used to obtain a plurality of target Posit floating-point numbers participating in the operation according to a calculation instruction of the CPU, and convert the plurality of target Posit floating-point numbers into respective corresponding intermediate data in complement form; the intermediate data includes Multiple fields: sign field, real exponent field, first mantissa field and protection bit field;

The operation circuit is configured to perform operation on the received multiple intermediate data output by the decoding circuit according to the calculation instruction, to obtain an operation result represented by the intermediate data in complement form;

The encoding circuit is configured to convert the operation result into a Posit floating point number of the specified format according to the specified format in the calculation instruction.

Optionally, the decoding circuit includes: a first XOR device, a second XOR device, a reverse leading zero detection circuit device, a first shift circuit device, a first splicing circuit device, a first extraction circuit device, and the following Module:

The real symbol determination module of the regime is used to perform an XOR operation on the highest bit of the target Posit floating-point number and the second highest bit of the target Posit floating-point number by the first XOR device, to obtain the regime field of the target Posit floating-point number. real symbols;

The unified module of the regime field is used to remove the highest bit and the second highest bit of the target Posit floating point number for the first time, remove the highest bit and the lowest bit of the target Posit floating point number for the second time, and then pass the second XOR device The XOR operation is performed on the result of the first removal and the result of the second removal to obtain the uniform field of the regime;

The regime value calculation module is used to detect the unified field of the regime by the reverse leading zero detection circuit device, and obtain the value field of the regime field according to the output of the reverse leading zero detection circuit device;

an extraction module, configured to shift out the highest three bits of the target Posit floating-point number through the first shifting circuit device, and shift the remaining fields of the target Posit floating-point number after the highest three bits are shifted left by a specified number of bits ; The specified number of digits is obtained according to the output of the reverse leading zero detection circuit device;

The extraction module is further configured to extract the exponent field and the second mantissa field of the target Posit floating-point number from the left-shifted target Posit floating-point number according to the bit width of the exponent field of the target Posit floating-point number;

The true exponent determination module is used to invert the exponent field when the target Posit floating point number is a negative number, and then use the first splicing circuit device to convert the exponent field or the inverted exponent The field is spliced with the value field of the regime field to obtain and output the real index field in the intermediate data corresponding to the target Posit floating point number;

a first mantissa field determining module, configured to fill the lower bits of the second mantissa field with zeros according to the maximum bit width of the first mantissa field to obtain the first mantissa field, and output the first mantissa field; the The maximum bit width of the first mantissa field is the total bit width of the target Posit floating point number minus the bit width of the sign bit of the target Posit floating point number, the bit width of the exponent field, and the minimum bit of the regime field. wide available;

A protection bit output module, configured to use a field whose value of each bit is 0 as the protection bit field, and output the protection bit field; the bit width of the protection bit field is 3.

Optionally, the intermediate data further includes an infinite number field and a zero value field; the decoding circuit further includes: an infinite number determination module and a zero value judgment module;

The infinite number determination module is used to set the infinite number field of the intermediate data corresponding to the target Posit floating point number to true when the target Posit floating point number is an infinite number;

The zero value judgment module is configured to set the zero value field of the intermediate data corresponding to the target Posit floating point number to true when the target Posit floating point number is zero.

Optionally, the intermediate data further includes a symbol field; the decoding circuit further includes: a symbol judgment module;

The symbol judgment module is used to determine the symbol of the target Posit floating point number according to the highest bit of the target Posit floating point number, and then use the symbol of the target Posit floating point number as the symbol of the intermediate data corresponding to the target Posit floating point number, And output the symbol field of the intermediate data corresponding to the target Posit floating point number as the symbol of the intermediate data.

Optionally, the encoding circuit includes: a second extraction circuit device, a second shift circuit device, a second splicing circuit device, and the following modules:

The exponent field encoding module is used for extracting a field whose bit width is the same as that of the exponent encoding field in the real exponent field of the operation result by the second extraction circuit device in the order of the lowest bit to the highest bit , obtain the exponent encoding field according to the field whose bit width is the same as that of the exponent encoding field, and extract the real exponent field after the field whose bit width is the same as that of the exponent encoding field is used as the The value corresponding to the above-mentioned regular code field;

Regime format determination module, according to the symbol field of described operation result and the symbol of described regime coding field, determine the filling format of described regime coding field;

The regime field encoding module is used for sequentially splicing the padding format, the exponent encoding field, the first mantissa field of the operation result, and the protection bit field of the operation result with the second splicing circuit device to obtain The splicing field, and with the second shift circuit device, according to the numerical value corresponding to the regular coding field, the splicing field is arithmetically shifted to the right to obtain the regular coding field;

A floating-point number result determination module, configured to use the protection bit field to perform a rounding operation on the splicing field shifted to the right, and add the operation result to the highest bit of the splicing field after the rounding operation of the sign field, to get the Position floating point number in the specified format.

Optionally, the encoding circuit further includes an output module:

The output module is used to directly output the Posit floating point number of the specified format as an infinite number encoding field representing an infinite number when the infinite number field of the intermediate data is true;

The output module is further configured to directly output the Posit floating point number in the specified format as an infinite number encoded field representing a zero value when the zero value field of the intermediate data is true.

Optionally, the reverse leading zero detection circuit device includes an OR device, a first inversion device, and a second inversion device;

The reverse leading zero detection circuit device is used to use the first inversion device to respectively invert the 0th bit of a plurality of input fields with a bit width of 2, and then use the OR device to respectively invert multiple bits. The inversion results are ORed with the first bits of the input fields with a bit width of 2 to obtain the 0th bit of the output fields; the input fields with a bit width of 2 are the unified obtained after dichotomous processing;

The reverse leading zero detection circuit device is further configured to use the OR device to detect the 0th bit of the plurality of input fields with a bit width of 2 and the first bit of the plurality of input fields with a bit width of 2 respectively. performing an OR operation on the bits to obtain the first bit of the plurality of output fields;

The reverse leading zero detection circuit device is also used for splicing the multiple output fields to obtain the inverse code of the value of the regular uniform field.

Optionally, the regime value calculation module includes:

The regime value calculation sub-module is used to invert the inverse code output by the reverse leading zero detection circuit device when the real symbol of the regime field is positive, and then invert the reversed leading zero The highest bit of the inverse code output by the detection circuit device adds the real symbol of the regime field to obtain the value field of the regime field;

The regime value calculation submodule is also used to add the real symbol of the regime field to the highest bit of the complement code output by the reverse leading zero detection circuit device when the real symbol of the regime field is negative, to obtain the Describe the value field of the regime field.

Optionally, the floating-point number result determination module includes:

The protection bit submodule is used to add 1 to the lowest bit of the splicing field after shifting to the right when each bit of the splicing field after shifting to the right is 0, and When all the values of the splicing field are 1, keep the splicing field after shifting to the right unchanged;

The protection bit submodule is further configured to, when the values of any two bits in the splicing field shifted to the right are not the same, and the value of the protection bit is greater than 4, when the value of the protection bit shifted to the right is greater than 4. The lowest bit of the splicing field is added by 1, or any two bits in the splicing field after shifting to the right are not the same, when the value of the protection bit is equal to 4, and the splicing field after shifting to the right When the lowest bit of is 1, add 1 to the lowest bit of the spliced field after shifting to the right.

Optionally, the exponent field encoding module is further configured to invert a field whose bit width is the same as that of the exponent encoding field when the symbol field of the intermediate data represents a negative number, to obtain the exponent encoding field. ;

When the sign field of the intermediate data represents a positive number, a field with the same bit width as that of the exponent encoding field is used as the exponent encoding field.

The Posit floating-point number processor proposed by the embodiment of the present application uses a decoding circuit to convert the Posit floating-point number obtained according to the calculation instruction into intermediate data in complement form, where the intermediate data includes an infinite number field and a zero value representing a special Posit floating-point number field, so that when the calculation parameter or the calculation result is a special Posit floating point number, the arithmetic circuit and the encoding circuit can directly output the infinite number encoding field or zero value encoding field representing the special Posit floating point number, which improves the output of the Posit floating point number processor efficiency.

The arithmetic circuit can directly use the real exponent field and the first mantissa field in the intermediate data for operation, and after extracting and splicing the constituent fields of the Posit floating point number, the real exponent field and the first mantissa field, the real exponent field and the The first mantissa field is a fixed-point number in complement form. After multiple intermediate data are operated according to the calculation instructions, the operation result represented by the intermediate data is still a fixed-point number in complement form. The encoding circuit only needs to be specified by the CPU processor. The encoding format of the Posit floating-point number can be completed by converting the fixed-point number in the complement form to the encoding format of the Posit floating-point number. The above process does not require multiple processes of mutual conversion from original code to complement code, which simplifies the processing operation of the Posit floating point number.

The symbol field in the intermediate data can be directly used in the operation circuit, and the symbol of the operation result can also be used in the encoding circuit to obtain the regular encoding field, which is directly used as the highest bit of the Posit floating-point number that finally represents the operation result. When considering complement, the difference in the encoding form of positive and negative Posit floating-point numbers simplifies the processing of Posit floating-point numbers.

The protection bit field in the intermediate data is used in the operation circuit to round the operation result, and it can also be used in the encoding circuit to round the encoding process, so that the work of the Posit floating point number processor conforms to the Posit floating point number. specification.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present application more clearly, the following briefly introduces the drawings that are used in the description of the embodiments of the present application. Obviously, the drawings in the following description are only some embodiments of the present application. , for those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative labor.

1 is a schematic structural diagram of a decoding circuit according to an embodiment of the present application;

2 is a schematic structural diagram of a reverse leading zero detection circuit device proposed in an embodiment of the present application;

3 is a schematic structural diagram of a Posit floating-point number processor proposed by an embodiment of the present application;

FIG. 4 is a schematic structural diagram of an encoding circuit proposed in an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

Posit floating point number is a new floating point number standard (also called Unum floating point standard, Posit is the third edition Unum standard) proposed by John L. Gustafson, a professor at the National University of Singapore, which defines a different data format from IEEE 754 and arithmetic rules. Compared with IEEE 754, Posit has the advantages of flexible data format, large dynamic range, less abnormal format and high precision. It is not limited to the advantages listed below:

The sampling distribution of Posit floating-point numbers on real numbers is related to the sigmoid function, which is an activation function commonly used in popular machine learning. After practice, Posit floating-point numbers are very convenient when fitting sigmoid functions. Therefore, applying Posit floating-point numbers in the field of machine learning can simplify the related hardware design.

Compared with IEEE 754 floating-point numbers, when agreeing on the total bit width of floating-point numbers, it needs to meet the bit width format specified in IEEE 754-2008, that is, 16-bit half-precision, 32-bit single-precision, 64-bit double-precision and 128-bit quad-precision four. Seed width. Posit floating-point numbers can choose the bit width of any format if they meet the needs of the application, either 32bit, 31bit, 33bit, 30bit, etc., which reflects the flexibility of Posit floating-point numbers. Compared with IEEE754 floating-point numbers, in order to utilize more coding space, an unconventional number whose hidden bit is 0 is specified, while the hidden bit of Posit floating-point number is always 1, which reduces the complexity of the hardware.

In the prior art, the processing of Posit floating point numbers is still in the theoretical research stage, and there is no Posit processor that can be put into commercial applications. Moreover, the current research direction of the processing method of Posit floating-point numbers is to first use the decoding circuit to convert the Posit floating-point numbers into the original code, and then input the operation circuit. After the operation result, it is converted into the operation result of the original code, input to the encoding circuit, and the encoding side finally converts the operation result of the original code into a Posit floating point number. The entire processing process requires repeated conversion from original code to complement code and complement code to original code. The logic is complex, resulting in a large number of additional operations, resulting in a large overall Posit floating-point number processing circuit area.

In view of the above problems, an embodiment of the present application proposes a Posit floating-point number processor, which is used to decode the Posit floating-point number into intermediate data in complement form, perform operations on the intermediate data, and then encode the operation result to obtain the operation of the Posit floating-point number. result. The Posit floating-point number processor proposed by the embodiments of the present application can decode the Posit floating-point number into intermediate data that can directly participate in the operation, and solves the problem in the existing solution that the Posit floating-point number must be converted into the binary code of its value before the operation can be performed. Defects, as well as the entire processing of Posit floating point numbers, require a large number of defects in conversion calculations from the original code to the complement, and from the complement to the original code.

Floating point number is a scientific notation method used to approximately represent any real number in computer technology. Take the real number M×2 ^e as an example, M is the mantissa, 2 is the base, and e is the exponent. The data involved in the operation in the computer are all represented in binary, so whether it is an IEEE 754 floating point number or a Posit floating point number, the base is 2.

After the total bit width of the Posit floating-point number is agreed, the bit width of the exponent is also agreed. Generally, for a Posit floating point number with a total bit width of 32 bits, a bit width of 2-4 bits is usually agreed as the exponent bit width of the Posit floating point number. For a Posit floating point number with a total bit width of 8 bits, a bit width of 1-2 bits is usually agreed. The bit width of the exponent field as a floating-point number for Position. Including the exponent field, the Posit floating point standard specifies that Posit floating point numbers have the following fields:

One: Symbol field. The sign field is usually the most significant bit of a Position floating-point number.

2. The regime field, located after the symbol field, the regime field consists of a series of consecutive 1s from the highest bit to the next lowest bit and the lowest bit 0, the lowest bit 0 is the flip bit, or from the highest bit to the next lowest bit one The string consists of consecutive 0s and the least significant 1. When the regime field is positive, the value of the regime field is minus 1 for the number of consecutive 1s, and when the consecutive regime field is negative, the value of the regime field is negative for the number of 0s. The width of the regime field can be arbitrary. For example: when the regime field is 1110, its value is 3-1=2; when the regime field is 0001, its value is -3.

3. Exponent field, if the Regime field does not use up the pre-agreed total bit width, the Regime field is followed by the exponent field, and the bit exponent field width is the pre-agreed bit width. The exponent field is an unsigned integer whose value must be greater than zero.

例如，es＝1时，

es＝2时，

假设一个Posit浮点数的符号为s，regime的值为r，指数的值为e，含隐藏位的尾数值为m，那么该Posit浮点数对应的十进制实数为：4. The mantissa field, that is, the second mantissa field. If the exponent field and the regime field do not use up the total bit width agreed in advance, the remaining total bit width is the bit width of the mantissa field. It can be understood that, in the decimal system, since the mantissa is a decimal number greater than or equal to 1.0 and less than 10, its integer part takes any integer from 1 to 9. In binary, the integer part of the mantissa can only be 1. In order to reduce unnecessary encoding, the Posit floating-point number standard uses the integer bits as hidden bits, and only records the decimal place in the mantissa field of the Posit floating-point number. For example: if the mantissa field is 1001, then it is 11001 plus hidden bits, and the corresponding decimal value is 1×2 ⁰ +1×2 ^-1 +0×2 ^-2 +0×2 ^-3 +1×2 ^{- 4} = 1.5625. In the Posit floating-point number standard, the concept of used is also defined, which is used to unify the regime field and the exponent field numerically. The value of used is related to the bit width of the exponent field of the pre-agreed Posit floating-point number. For any fixed-format Posit floating-point number, the value of used is also fixed. Assuming that the bit width of the exponent field is es, the value of used is

For example, when es=1,

When es=2,

Assuming that the symbol of a Posit floating-point number is s, the value of the regime is r, the value of the exponent is e, and the value of the mantissa with hidden bits is m, then the decimal real number corresponding to the Posit floating-point number is:

(-1) ^s ×used ^r ×2 ^e ×m

At present, in the related research of Posit floating-point numbers, the Posit floating-point number is converted into the original code, that is, the Posit floating-point number with a negative sign is converted into an absolute value, and the absolute value is the positive number corresponding to the Posit floating-point number with the negative sign, plus The sign bit above represents a negative number. Since the computer uses the complement code for operation, the operation circuit needs to convert the mantissa part of the positive number corresponding to the negative Posit floating point number to the complement code during the operation; in the encoding process, the complement code needs to be converted to the original again. code. It can be seen that the entire processor for Posit floating-point numbers requires multiple circuits for mutual conversion between original code and complement code, resulting in a larger area and greater heat generation of the circuit for processing Posit floating-point numbers.

The embodiment of the present application creates an original decoding circuit of complement code type, uses the original decoding circuit to decode the Posit floating point number into intermediate data that can directly participate in the operation, and then uses the operation circuit to directly perform operations on the intermediate data to obtain the operation represented by the intermediate data. As a result, the operation result is finally encoded as a Posit floating point number using an original complement-type encoding circuit. The entire processing process (decoding, operation, and encoding) of Posit floating-point numbers is carried out in complement code, without a large number of complement code conversion, which reduces power consumption.

The above circuits and modules for processing Posit floating point numbers have been integrated into the open source RISC-V (open source instruction set architecture based on reduced instruction set principle) processor RocketChip (an open source integrated chip generator developed based on open source hardware construction language) , which constitutes the Posit floating point processor proposed in this application, which can execute all floating point instructions and correctly complete the corresponding functions.

Referring to FIG. 1 , FIG. 1 is a schematic structural diagram of a decoding circuit according to an embodiment of the present application. First, the decoding circuit of the Posit floating-point number processor will be described. The decoding circuit includes: an infinite number determination module 101, a zero value determination module 102, a symbol determination module 103, a regular real symbol determination module 104, a regular field unification module 105, a regular value calculation module 106, an extraction module 107, a real index determination module 108, The first mantissa field determination module 109 and the protection bit output module 110 .

The decoding circuit is used to obtain a plurality of target Posit floating-point numbers participating in the operation according to a calculation instruction of the CPU, and convert the plurality of target Posit floating-point numbers into respective corresponding intermediate data in complement form; the intermediate data includes Multiple fields: sign field, real exponent field, first mantissa field and protection bit field;

Compared with the current need to determine whether to perform complement conversion on the Posit floating point number by judging the sign of the Posit floating point number before calculating the Posit floating point number, the sign field in the embodiment of the present application can directly participate in the operation, reducing the Posit floating point number. The logical judgment before and after the operation is completed.

The target Posit floating-point number is the Posit floating-point number to be decoded obtained by the decoding circuit according to the calculation instruction. Since the target Posit floating-point numbers are involved in the operation, the number of target Posit floating-point numbers is two or more, and the decoding circuit can decode multiple target Posit floating-point numbers at the same time or sequentially.

The intermediate data set in this embodiment of the present application is in a fixed-point format, and specifically includes: an infinite number field, a zero value field, a sign field, a real exponent field, a first mantissa field, and a protection bit field.

In order to distinguish between the intermediate data and the mantissa field of the target Posit floating point number, the first mantissa field represents the mantissa field in the intermediate data, and the second mantissa field represents the mantissa field of the target Posit floating point number.

There are only two special codes in Posit floating-point numbers: the real number 0 is represented by the code where all the digits are 0, the real number is represented by the code where the highest digit is 1, and the code where the rest of the digits are all 0 represents the infinite number. Therefore, an infinite number determination module and a zero value judgment module are set in the decoding circuit to mark the special-coded target Posit floating-point number, so that when the arithmetic circuit recognizes the special-coded target Posit floating-point number according to the mark, it can directly output, The operation result after the operation on a plurality of special-coded target Posit floating-point numbers enables the encoding circuit to directly output the code representing infinite number and the code representing zero when the operation result is intermediate data representing the special code. According to the above analysis, the Posit floating point number processor proposed in the present application processes the specially encoded target Posit floating point number more quickly.

Assuming that the specified format is Posit<8,1>, the encoding of an infinite number is 10000000, and the encoding of zero is 00000000.

The decoding circuit further includes: an infinite number determination module 101 and a zero value determination module 102;

The intermediate data further includes an infinite number field and a zero value field; the decoding circuit further includes: an infinite number determination module and a zero value judgment module;

The infinite number determination module 101 is used to set the infinite number field of the intermediate data corresponding to the target Posit floating point number to true when the target Posit floating point number is an infinite number;

The zero value judgment module 102 is configured to set the zero value field of the intermediate data corresponding to the target Posit floating point number to true when the target Posit floating point number is zero.

When the infinite number determination module determines that the target Posit floating point number is not an infinite number, the zero value field and the infinite number field are set to false. The infinite number determination module 101, the zero value judgment module 102 and the symbol judgment module 103 are connected in parallel, no matter whether the infinite number field and the zero value field are true, the decoding circuit will decode the target Posit floating point number to obtain the symbol field, the real exponent field, the first The mantissa field and the protection bit field. The infinity field and the zero value field are used to ensure that when the target Posit floating-point number is zero or infinity, the result of the operation is zero or infinity, regardless of the sign field, the real exponent field, the first mantissa field, and the protection bit field. Whether the code obtained after the calculation is the code of zero or infinite number, and whether the calculation efficiency of the special code is calculated according to the sign field, the real exponent field, the first mantissa field and the guard bit field, the Posit floating point number processor can quickly and accurately. Output a Position floating point number representing zero or infinity.

The intermediate data further includes a symbol field; the decoding circuit further includes: a symbol judgment module;

The symbol judgment module 103 is used to determine the symbol of the target Posit floating point number according to the highest bit of the target Posit floating point number, and then use the symbol of the target Posit floating point number as the symbol of the intermediate data corresponding to the target Posit floating point number , and output the symbol field of the intermediate data corresponding to the target Posit floating point number as the symbol of the intermediate data.

According to the Posit floating point number standard, the most significant bit of the target Posit floating point number is the sign bit. When the target Posit floating-point number is not an infinite number or zero, if its highest bit is 1, the target Posit floating-point number is a negative number, and 1 is used as the sign field; if its highest bit is 0, the target Position floating-point number is a positive number, with 0 as the sign field. The symbol field of the intermediate data is that after the decoding circuit parses the encoding of the Posit floating-point number, the highest bit of the Posit floating-point number, that is, the symbol field of the Posit floating-point number, is directly used as the symbol field.

The decoding circuit further includes: a first XOR device, a second XOR device, a reverse leading zero detection circuit device, a first shift circuit device, a first splicing circuit device, and a first extraction circuit device.

The real symbol determination module 104 of the regime is configured to perform an XOR operation on the highest bit of the target Posit floating point number and the second highest bit of the target Posit floating point number through the first XOR device to obtain the regime field of the target Posit floating point number the real symbol of ;

Since the entire Posit floating-point number is in complement form, the sign of the registry field of a negative Posit floating-point number cannot be directly judged by the form of the registry field of the Posit floating-point number. Specifically, when the Posit floating-point number represents a negative number, it does not change the sign of the corresponding positive number to 1, but inverts and adds one to the entire Posit floating-point number like a complement. For example, suppose the format of the target Posit float is Posit<8, 1>, the target Posit float is 01011000, 01011000 means 3, but -3 is not 11011000, but 10100111+1=10101000.

In the embodiment of the present application, the real symbol of the regime is determined by the module, and the two-digit number (the highest bit and the second highest bit of the target Posit floating-point number) can be calculated only by the XOR circuit device, so that the real symbol of the regime field in the target Posit floating-point number can be distinguished. , reduces the area of the circuit, and reduces the heat generated when the Posit floating point processor is running.

Continuing with the above example about the regime field, assuming that the form of the regime field obtained from the Posit floating-point number is 1110, when the Posit floating-point number is positive, the regime field of the Posit floating-point number is 1110; when the Posit floating-point number is negative, The entire Posit floating-point number is obtained by another encoding's complement, and inevitably the region field is also obtained by another encoding 0001's complement.

In view of this, the decoding circuit of the Posit floating-point number proposed in the embodiment of the present application obtains the real symbol of the regime field in the Posit floating-point number by using the real symbol determination module of the regime.

The working principle of the real sign determination module of the regime is that any digit in binary is XORed with 0 and remains unchanged, and XORed with 1 to take the inverse of the digit. When the Posit floating-point number is positive, the highest bit is 0, and 0 is XORed with the first bit of the regime field, and the first bit of the regime field remains unchanged; when the Posit floating-point number is negative, the highest bit is 1, and 1 and the first bit of the regime field remain unchanged. The first bit is XORed, and the first bit of the regime field is negated. For example, the Posit floating point number is 01110, the regime field 1110 is a positive number, the Posit floating point number is 11110, and the regime field 1110 should be 0001, which is a negative number. Combining the characteristics of the exclusive algorithm and the properties of the regime field itself, the embodiment of the present application uses the XOR device to XOR only the highest-order and second-highest two digits to obtain the real symbol of the regime field. The circuit is simple and does not need to add other arithmetic circuit.

The regime field unification module 105 is used to remove the highest bit and the second highest bit of the target Posit floating point number for the first time, remove the highest bit and the lowest bit of the target Posit floating point number for the second time, and then pass the second XOR The device performs an XOR operation on the result of the first removal and the result of the second removal to obtain the uniform field of the regime;

The first removal is to remove the highest and second highest bits of the target Posit floating point number; the second removal is to remove the highest and lowest bits of the same target Posit floating point number. The first removal and the second removal refer to removing the highest and second highest bits, and removing the highest and lowest bits, respectively, for the same target Posit floating-point number. The first and the second do not represent restrictions on the execution order of the steps.

The working principle of the unified module of the regime field is: the Posit floating-point number after removing the highest and lowest bits and the Posit floating-point number after removing the highest and second highest bits will differ by one bit, and the lowest bit of the regime field will be flipped, so the regime The last bit of the field must be XORed with the next-lowest bit of the regime field, which belongs to the XOR of different numbers. The XOR of the bits before the lowest bit of the regime field is the XOR of the same number, and the XOR of different numbers is 1. The XOR of the same number results in 0, and further, the uniform field of the regime must be in the form of a string of 0 plus 1. The unified regime field is a field that unifies the regime field with leading 0 and the regime field with leading 1.

For example, assuming that the target position float is "0|110|0|000", the result of the first removal is "110|0|00", and the result of the second removal is "10|0|000", the " 0|110|0|000" and "10|0|000" are XORed to obtain the uniform field "01|0000" of the regime.

In this embodiment of the present application, the two encoding forms of the regime field are unified into one encoding form through the regime field unification module, so that all the regime fields (for example: 11110 and 00001) can be obtained directly through a leading zero detection circuit. The effect of the value avoids the defect that a leading zero detection circuit and a leading one detection circuit need to be used separately for the regime fields of the two encoding forms, and avoids the use of the leading zero detection circuit and the leading one detection circuit at the same time. The circuit area is too large.

The regime value calculation module 106 is used to detect the uniform field of the regime by the reverse leading zero detection circuit device, and obtain the value field of the regime field according to the output of the reverse leading zero detection circuit device;

The value field of the regime field is the value of the regime field in binary representation.

Another embodiment of the present application proposes a method for detecting the uniform field of the regime with a reverse leading zero detection circuit to obtain the value of the regime field. Referring to FIG. 2 , FIG. 2 is a schematic structural diagram of a reverse leading zero detection circuit device proposed by an embodiment of the present application.

The reverse leading zero detection circuit device includes an OR device, a first inversion device, and a second inversion device;

The reverse leading zero detection circuit device is used to use the first inversion device to respectively invert the 0th bit of a plurality of input fields with a bit width of 2, and then use the OR device to respectively invert multiple bits. The inversion results are ORed with the first bits of the input fields with a bit width of 2 to obtain the 0th bit of the output fields; the input fields with a bit width of 2 are the unified obtained after dichotomous processing;

The reverse leading zero detection circuit device is further configured to use the OR device to detect the 0th bit of the plurality of input fields with a bit width of 2 and the first bit of the plurality of input fields with a bit width of 2 respectively. performing an OR operation on the bits to obtain the first bit of the plurality of output fields;

The reverse leading zero detection circuit device is also used for splicing the multiple output fields to obtain the inverse code of the value of the regular uniform field.

The reverse leading zero detection circuit device firstly halves the uniform field of the regime several times to obtain a plurality of input fields with a bit width of 2. For example, assuming that the uniform field of the regime is 000001, the multiple input fields with a bit width of 2 obtained by the binary circuit are (00), (00), (01). The sub-circuit is then used to detect each input field with a bit width of 2, and obtain the inverse code of the number of 0s in each input field with a bit width of 2.

As an example, it is described with (01) in a plurality of input fields with a bit width of 2, "1" is the 0th bit of the input field (01), "0" is the 1st bit of the input field (01), " After inversion of 1", "0" is obtained, and "0" is ORed with "0" to obtain 0, which is used as the 0th bit of the output field corresponding to (01). Similarly, the first bit of the output field is 1, and the output field corresponding to (01) is "10". Similarly, the sub-circuit calculates (00), and the output field corresponding to (00) is 01, and then output The complement of the value of the unified field of regime [(01)(01)(10)].

After obtaining the inverse code of the value of the unified field of the regime [(01)(01)(10)], invert "10" to get "01", 01 is the number of 0s in (01), indicating (01) There is 1 0 in it. Invert 01, invert 01 to get 10, 10 is the number of 0s in (00), indicating that there are 2 0s in (00). Then, the detection results of multiple input fields [(00)(00)(01)] with a bit width of 2 are obtained as [(2)+(2)+(1)], that is, there are a total of 5 0s in 000001.

The regime value calculation sub-module is used to invert the inverse code output by the reverse leading zero detection circuit device when the real symbol of the regime field is positive, and then invert the reversed leading zero The highest bit of the inverse code output by the detection circuit device adds the real symbol of the regime field to obtain the value field of the regime field;

The regime value calculation submodule is also used to add the real symbol of the regime field to the highest bit of the complement code output by the reverse leading zero detection circuit device when the real symbol of the regime field is negative, to obtain the Describe the value field of the regime field.

Detecting the uniform field of the regime 000001, it is found that there are 5 zeros, that is, the value of the regime field is 5, and the value field of the regime field is 101. According to the real symbol of the regime and the value of the uniform field of the regime, the value of the regime field in the target Posit floating-point number can be clearly obtained.

The reverse leading zero detection circuit proposed in the embodiment of the present application firstly detects the unified field of the regime to directly obtain the inverse code of the value of the region field, and then inverts the unified logic of the output field obtained by each sub-circuit, avoiding the need for a unified logic in each sub-circuit. The circuit frequently inverts the 1st and 0th bits of the input field, respectively, resulting in an increase in the circuit area.

The extraction module 107 is configured to shift out the highest three bits of the target Posit floating-point number through the first shifting circuit device, and shift the remaining fields of the target Posit floating-point number after the highest three bits are shifted left by a specified position The specified number of digits is obtained according to the output of the reverse leading zero detection circuit device;

The highest three bits shifted out are the sign bit of the target Posit floating point, the flip bit of the regime field of the target Posit floating point, and the 1-bit difference between the uniform field and the regime field.

The specified number of bits is the number of 0s obtained in the uniform field of the regime after the reverse leading zero detection circuit device detects the uniform field of the regime. For example, if the uniform field of the regime is 0001, then the specified number of digits is 3.

The decoding circuit provided by the embodiment of the present application uses the reverse leading zero detection circuit device to detect the number of 0s in the uniform field of the regime, and then compares the number of 0s in the uniform field of the regime and the sign bit, the flip bit and the uniform field of the regime with the regular The 1-bit difference of the fields is shifted out to obtain the exponent field and the second mantissa field with the remaining bit width determined, which solves the problem that the exponent is difficult to distinguish due to the uncertainty of the bit width of the regime field in the Posit floating-point number. The exponent field is extracted from the target Posit floating-point number after removing the highest three digits and the specified number of digits.

The extraction module is further configured to extract the exponent field and the second mantissa field of the target Posit floating-point number from the left-shifted target Posit floating-point number according to the bit width of the exponent field of the target Posit floating-point number;

The true exponent determination module 108 is configured to invert the exponent field when the target Posit floating point number is a negative number, and then use the first splicing circuit device to invert the exponent field or the inverted The exponent field is spliced with the value field of the regime field to obtain and output the real exponent field in the intermediate data corresponding to the target Posit floating point number;

The first mantissa field determining module 109 is configured to, according to the maximum bit width of the first mantissa field, fill in the lower bits of the second mantissa field with zeros to obtain the first mantissa field, and output the first mantissa field; The maximum bit width of the first mantissa field is the total bit width of the target Posit floating point number minus the bit width of the sign bit of the target Posit floating point number, the bit width of the exponent field, and the minimum of the regime field. bit width obtained;

The second mantissa field extracted from the Posit floating point number is directly used as the first mantissa field of the intermediate data. The exponent field extracted from the Posit floating point number is spliced with the value field of the regime field to obtain the real exponent field of the intermediate data. When splicing the regime index and the index field, the regime index is high.

Since the bit width of the left shift of the exponent field is exactly 2 ^es , in this embodiment of the present application, the exponent field is directly spliced into the low-order bit of the value field of the regime field to implement the carry of the value field of the regime field. Specifically, the index field is placed at a low position, and the value field of the regime field is placed at a high position. Through splicing, the indexation of the regime field is completed, which avoids the redundant logic circuit required to use used to index the regime field, thereby reducing the Posit floating point. The circuit area of the point processor.

When converting the Posit floating point number to the corresponding real value represented by binary, the exponent field and the regime field of the Posit floating point number will be unified through used. The unified exponent field and regime field are: used·regime+e, where used=2 ^es , where e refers to the exponent field, regime refers to the regime field, and es refers to the exponent bit width of the Posit floating point number.

The bit width of the real exponent field is determined by the bit width of the exponent and the bit width of the value field of the regular field, and is a fixed value. The range of the bit width of the first mantissa field is further determined: the total bit width of the target Posit floating point number - the bit width of the exponent field - the sign bit - the smallest regular field (2 bits) = the maximum value of the bit width of the first mantissa field.

The real exponent field of the intermediate data obtained in the embodiment of the present application only needs to splicing the value field and exponent field of the regime field to obtain the real exponent field that can participate in the operation, and the extracted second mantissa field can be directly used as The first mantissa field of the intermediate data, the decoding process is simple, and the calculation steps of the decoding circuit are simplified.

The protection bit output module 110 is configured to use a field whose value of each bit is 0 as the protection bit field, and output the protection bit field; the bit width of the protection bit field is 3.

The decoding circuit converts the target Posit floating-point number into intermediate data without right-shift rounding, so the value of the three protection bits of the protection bit field is directly set to 0.

When the arithmetic circuit operates with intermediate data, the protection bit field is used to round the result after the operation, which follows the rounding principle in the Posit floating-point number standard. On the other hand, the real exponent field and the first mantissa field are The directly extracted field of the target Posit floating-point number, or obtained by splicing each field in the target Posit floating-point number, is still in the form of complement code, so that the intermediate data obtained by the Posit floating-point number processor proposed in the embodiment of the present application is strictly complied with. The Posit floating point number standard is adopted, and the intermediate data does not need to be converted into the original code, and the decoding process is simple.

Referring to FIG. 3 , FIG. 3 is a schematic structural diagram of a Posit floating-point number processor proposed by an embodiment of the present application. The Posit floating point number processor includes: a decoding circuit 301, an arithmetic circuit 302 and an encoding circuit 303;

The operation circuit 302 is configured to perform operation on the received multiple intermediate data output by the decoding circuit according to the calculation instruction, to obtain an operation result represented by the intermediate data in the form of complement code;

After the decoding circuit obtains the intermediate data: the infinite number field, the zero value field, the sign field, the real exponent field, the first mantissa field and the protection bit field, the operation circuit directly performs the operation on the intermediate data. When the infinite number field or zero value field in the intermediate data is true, the operation circuit can directly obtain the corresponding special value (infinite number or zero intermediate data), protect the bit field during the operation process, or round the operation result operate. The input of the whole operation circuit is the intermediate data in complement form, and the output is still the intermediate data in complement form, and there is no need to convert the intermediate data between the original code and the complement code, which simplifies the operation process.

The encoding circuit 303 is configured to convert the operation result into a Posit floating point number in the specified format according to the specified format in the calculation instruction.

The specified format refers to the convention for the total bit width and exponent bit width of the Posit floating point number. Generally, the specified format is Position<total bit width, index bit width>.

The encoding circuit converts the intermediate data output by the operation circuit into Posit floating point code according to the format specified by the computer processor (CPU) for the operation result. The entire encoding process does not involve the conversion of the original code to the complement code, and only needs to restore each field of the intermediate data to each field of the Posit floating point number encoding, and the logic of the encoding circuit is simple.

The encoding circuit also includes an output module:

The output module 401 is configured to directly output the Posit floating point number of the specified format as an infinite number encoding field representing an infinite number when the infinite number field of the intermediate data is true;

The output module 401 is further configured to directly output the Posit floating point number in the specified format as an infinite number encoding field representing a zero value when the zero value field of the intermediate data is true.

When the infinite number field of the intermediate data is not true and the zero value field is not true, the output module outputs the Posit floating point number encoded by the sign field, the real exponent field, the first mantissa field and the protection bit field of the intermediate data. It can be understood that, according to the symbol field, the real exponent field, the first mantissa field, and the protection bit field of the intermediate data, the calculation of the Posit floating-point number obtained by encoding is relatively complicated. The Posit floating-point number processor processes multiple target Posit floating-point numbers. It takes a long time to get the output Posit floating point number. Therefore, through the output module, when the infinite number field is true, or the zero value field is true, the special code representing 0 or infinite number is forcibly and preferentially output directly, which can avoid waiting for the Posit floating point number. The point processor converts the target Posit floating point number into intermediate data, then calculates the time consumed by the intermediate data, and directly outputs the special code, which improves the output efficiency of the Posit floating point number processor for the special encoding of 0 or infinite number.

Referring to FIG. 4 , FIG. 4 is a schematic structural diagram of an encoding circuit proposed by an embodiment of the present application.

The encoding circuit 303 includes: a second extraction circuit device, a second shift circuit device, a second splicing circuit device, and the following modules:

The exponent field encoding module 402 is used for extracting the second extraction circuit device from the real exponent field of the operation result, in the order of the lowest bit to the highest bit, to obtain a bit width that is the same as the bit width of the exponent encoding field. field, the exponent encoding field is obtained according to the field whose bit width is the same as that of the exponent encoding field, and the real exponent field after the field whose bit width is the same as that of the exponent encoding field is extracted, as the value corresponding to the regular code field;

The exponent field encoding module is further configured to invert a field whose bit width is the same as that of the exponent encoding field when the symbol field of the intermediate data represents a negative number to obtain the exponent encoding field;

When the sign field of the intermediate data represents a positive number, a field with the same bit width as that of the exponent encoding field is used as the exponent encoding field.

The encoding circuit is the inverse process of the decoding circuit, that is, according to a specific intermediate data type, it outputs a Posit<total bit width, index bit width> encoding, which needs to be shifted and rounded.

The exponent encoding field refers to the exponent field of the Position floating-point number representing the operation result.

In the real exponent field, the regular exponent is in the high position and the exponent field is in the low position. The format of the Posit floating point number of the operation result determines the bit width of the exponent encoding field, so that the exponent encoding field can be quickly extracted from the real exponent field. For example, assuming that the real exponent field is 11101011, and the exponent bit width of the Posit floating-point number representing the operation result is 2, 11 is directly extracted as the exponent coding field, and the remaining 111010 is used as the regime exponent to be converted into the regime coding field.

Regime format determination module 403, according to the symbol field of described operation result and the symbol of described regime coding field, determine the filling format of described regime coding field;

The regime encoding field refers to the regime field of the Posit floating point number representing the operation result.

Because the regime value calculation sub-module inverts the inverse code output by the reverse leading zero detection circuit device, adds the real symbol of the regime field, and obtains the value field of the regime field, or the regime value calculation sub-module reverses the leading zero. Detect the inverse code output by the circuit device, add the real symbol of the regime field, and obtain the value field of the regime field. Therefore, the value field of the regime field in the real exponent field in the intermediate data corresponding to the operation result carries the regime code. Therefore, the coding circuit can directly obtain the symbol of the regime coding field according to the value field of the regime field in the real exponent field of the extracted exponent coding field.

To further determine the representation of the regime encoding field in the Posit floating-point number of the operation result, it is also necessary to combine the sign of the Posit floating-point number of the operation result, that is, the symbol of the intermediate data, which is also the symbol field of the intermediate data.

The padding format refers to whether the regime encoding field is in the form of a leading one or a leading zero, determined according to the sign of the regime encoding field and the sign (sign field) of the Posit floating point number. If the Posit floating point number is positive and the regime encoding field is also positive, fill in 10; if the Posit floating point number is positive and the regime is a negative encoding field, fill in 01; if the Posit floating point number is negative and the regime encoding field is positive, fill in 01; if the Posit floating point number is negative and the registry encoding field is also negative, then fill with 10.

The regime field encoding module 404 is used for sequentially splicing the padding format, the exponent encoding field, the first mantissa field of the operation result and the protection bit field of the operation result with the second splicing circuit device, Obtaining the splicing field, and with the second shift circuit device, according to the numerical value corresponding to the regime encoding field, the splicing field is arithmetically shifted to the right to obtain the regime encoding field;

The lowest three bits of the splicing field are the protection bit fields to ensure the input protection of the entire splicing field when filling according to the padding format.

For example, assuming that the Posit floating point number is a positive number, the registry encoding field is a positive number, the padding format is 10, the exponent encoding field is 11, the first mantissa field of the operation result is 110111, the concatenated field is 10|11|110111|000, and the regime The value corresponding to the encoding field is 3, and the splicing field 11110111 000 needs to be arithmetically shifted 3 bits to the right to obtain 11110|11|110|111. The 111 of the mantissa field passes through the protection bit, and the protection bit finally forms 111. Thus, the regime code field 11110 is directly obtained. Guard bits are used to protect the precision of Posit floating point numbers. The Posit floating-point number standard specifies three protection bits GRS called Guard, Round, and Sticky respectively.

If the total bit width of the calculation result Posit<12,2> specified by the calculation instruction is 12 bits, then 1111110 11110111 needs to be rounded, and the rounded concatenated field is 1111110 11110. During the rounding process, 111 passes through The protection bits 000 and 000 correspond to the GRS bits, that is, the S bit, and the S bit is fixed to 1.

A floating-point number result determination module 405, configured to perform a rounding operation on the right-shifted splicing field by using the guard bit field, and add the operation to the highest bit of the rounded splicing field The sign field of the result, obtains the Position floating point number in the specified format.

The rounding operation can be understood as a binary "rounding" operation.

According to the positive number of the Posit floating point number, the sign field of the intermediate data is 1, and the sign bit is spliced in the highest bit of the rounded concatenation field 111111011110 to obtain the operation result of the specified format Posit floating point number 11111110 11110.

According to the standard specification of Posit, the encoding circuit takes a saturation operation on the encoding process of the intermediate data.

The floating point result determination module includes:

The protection bit submodule is used to add 1 to the lowest bit of the splicing field after shifting to the right when each bit of the splicing field after shifting to the right is 0, and When all the values of the splicing field are 1, keep the splicing field after shifting to the right unchanged;

The protection bit submodule is further configured to, when the values of any two bits in the splicing field shifted to the right are not the same, and the value of the protection bit is greater than 4, when the value of the protection bit shifted to the right is greater than 4. The lowest bit of the splicing field is added by 1, or any two bits in the splicing field after shifting to the right are not the same, when the value of the protection bit is equal to 4, and the splicing field after shifting to the right When the lowest bit of is 1, add 1 to the lowest bit of the spliced field after shifting to the right.

The value of any two bits in the right-shifted splicing field is different, except that the right-shifted splicing field is in the form of 00000...0 and 11111...1, all other forms of splicing field .

The standard of Posit is standardized. When special encoding (infinite number encoding and zero value encoding) is not considered during encoding, the encoding of the minimum value of positive Posit floating-point numbers is 00000...01, and the encoding of the maximum value of positive Posit floating-point numbers is 011111 ...... 1, when the absolute value of the negative Posit floating point number is the largest, the encoding is 1111111... 1, when the absolute value of the negative Posit floating point number is the smallest, the encoding is 10000...... 01, the saturation operation is, after encoding When the number is less than the encoding of the minimum value of the Posit floating-point number, the encoding of the minimum value of the Posit floating-point number is taken, that is, 00000... , which is 1111111...1.

The Posit floating-point number processor proposed by the embodiment of the present application uses a decoding circuit to convert the Posit floating-point number obtained according to the calculation instruction into intermediate data in complement form, where the intermediate data includes an infinite number field and a zero value representing a special Posit floating-point number field, so that when the calculation parameter or the calculation result is a special Posit floating point number, the arithmetic circuit and the encoding circuit can directly output the infinite number encoding field or zero value encoding field representing the special Posit floating point number, which improves the output of the Posit floating point number processor efficiency.

The arithmetic circuit can directly use the real exponent field and the first mantissa field in the intermediate data for operation, and in the coding rules of Posit floating point numbers, after extracting and splicing the constituent fields of the Posit floating point number, the real exponent field and the first mantissa field can be obtained. The one-mantissa field, the real exponent field and the first mantissa field are fixed-point numbers in complement form. After multiple intermediate data are operated according to the calculation instructions, the operation result represented by the intermediate data is still the fixed-point number in complement form. The circuit only needs to convert the fixed-point number in complement form to the encoding format of Posit floating-point number according to the format specified by the CPU processor, and then the encoding of the Posit floating-point number can be completed. The above process does not need to convert the Posit floating point number into the original code, and then convert the original code into the Posit floating point number, which simplifies the processing operation of the Posit floating point number. It avoids the redundancy and waste of calculation caused by converting the Posit floating point number to the original code, but it needs to complement the calculation.

The sign field in the intermediate data participates in the operation of the mantissa field in the operation circuit, and directly outputs the sign field of the operation result. It can be directly used in the operation circuit, and the symbol of the operation result can also be used in the encoding circuit to obtain the regular code field, which can be directly used as the highest bit of the Posit floating-point number that finally represents the operation result. When the complement code is no longer considered, The difference in the encoding form of positive and negative Posit floating-point numbers simplifies the processing of Posit floating-point numbers.

The protection bit field in the intermediate data is used in the operation circuit to round the operation result, and it can also be used in the encoding circuit to round the encoding process, so that the work of the Posit floating point number processor conforms to the Posit floating point number. specification.

Each embodiment in this specification is described in a progressive or illustrative manner, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between the various embodiments may be referred to each other.

Although the preferred embodiments of the embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once the basic inventive concepts are known. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications that fall within the scope of the embodiments of the present application.

Finally, it should also be noted that in this document, relational terms such as first and second are used only to distinguish one entity or operation from another, and do not necessarily require or imply these entities or that there is any such actual relationship or sequence between operations. Furthermore, the terms "comprising", "comprising" or any other variation thereof are intended to encompass a non-exclusive inclusion such that a process, apparatus or terminal device comprising a list of elements includes not only those elements, but also not expressly listed Other elements, or elements inherent to such a process, apparatus or circuit are also included. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in the process, device, or circuit that includes the element.

The above provides a detailed introduction to a Posit floating-point number processor provided by the present application. The descriptions of the above embodiments are only used to help understand the working principle of the Posit floating-point number processor of the present application; meanwhile, for those skilled in the art, According to the idea of the present application, there will be changes in the specific embodiments and application scope. In conclusion, the content of this specification should not be construed as a limitation on the present application.

Claims (10)

1. A Posit floating point number processor, comprising: a decoding circuit, an arithmetic circuit, and an encoding circuit;

the decoding circuit is used for acquiring a plurality of target Posit floating point numbers participating in operation according to a calculation instruction of the CPU, and converting the plurality of target Posit floating point numbers into intermediate data in a complementary code form corresponding to each target Posit floating point number; the intermediate data includes a plurality of fields: a sign field, a true exponent field, a first mantissa field, and a protection bit field;

the arithmetic circuit is used for carrying out arithmetic on a plurality of received intermediate data output by the decoding circuit according to the calculation instruction to obtain an arithmetic result represented by the intermediate data in a complementary code form;

and the coding circuit is used for converting the operation result into a Posit floating point number in a specified format according to the specified format in the calculation instruction.

2. The Posit floating point number processor of claim 1, wherein the decoding circuit comprises: a first exclusive-or device, a second exclusive-or device, an inverted leading zero detection circuit device, a first shift circuit device, a first splicing circuit device, a first extraction circuit device, and the following modules:

the register real symbol determining module is used for carrying out XOR operation on the highest bit of the target Posit floating point number and the second highest bit of the target Posit floating point number through the first XOR device to obtain a real symbol of a register field of the target Posit floating point number;

the region field unifying module is used for removing the highest bit and the second highest bit of the target Posite floating point number for the first time, removing the highest bit and the second lowest bit of the target Posite floating point number for the second time, and then performing XOR operation on the result of the first removal and the result of the second removal through the second XOR device to obtain a region unifying field;

the reverse leading zero detection circuit device is used for detecting the reverse leading zero value of the region field;

the extraction module is used for shifting out the highest three bits of the target Posit floating point number through the first shift circuit device and shifting left assigned numbers of the residual fields of the target Posit floating point number after the highest three bits are shifted out; the specified bit number is obtained according to the output of the reverse leading zero detection circuit device;

the extraction module is further configured to extract an exponent field and a second mantissa field of the target Posit floating point number from the left-shifted target Posit floating point number according to the bit width of the exponent field of the target Posit floating point number;

the real exponent determining module is used for negating the exponent field when the target Posit floating point number is a negative number, and splicing the exponent field or the negated exponent field with the value field of the register field through the first splicing circuit device to obtain and output a real exponent field in intermediate data corresponding to the target Posit floating point number;

a first mantissa field determining module, configured to perform zero padding on a low bit of the second mantissa field according to a maximum bit width of the first mantissa field to obtain a first mantissa field, and output the first mantissa field; the maximum bit width of the first mantissa field is obtained by subtracting the bit width of the sign bit of the target Posite floating point number from the total bit width of the target Posite floating point number, the bit width of the exponent field, and the minimum bit width of the register field;

a protection bit output module, configured to use a field with a value of 0 for each bit as the protection bit field, and output the protection bit field; the bit width of the protection bit field is 3.

3. The Posit floating point number processor of claim 1, wherein the intermediate data further comprises an infinity field and a zero value field; the decoding circuit further includes: an infinite number determining module and a zero value judging module;

the infinity determination module is configured to set an infinity number segment of intermediate data corresponding to the target Posit floating point number to true when the target Posit floating point number is an infinity number;

and the zero value judging module is used for setting a zero value field of intermediate data corresponding to the target Posit floating point number to be true when the target Posit floating point number is zero.

4. The Posit floating point number processor of claim 3, wherein the intermediate data further comprises a sign field; the decoding circuit further includes: a symbol judgment module;

and the symbol judgment module is used for determining the symbol of the target Posit floating point number according to the highest bit of the target Posit floating point number, taking the symbol of the target Posit floating point number as the symbol of the intermediate data corresponding to the target Posit floating point number, and outputting the symbol field of the intermediate data corresponding to the target Posit floating point number as the symbol of the intermediate data.

5. The Posit floating point number processor of claim 1, wherein the encoding circuit comprises: a second extraction circuit device, a second shift circuit device, a second stitching circuit device, and the following modules:

an exponent field encoding module, configured to extract, by the second extraction circuit device, a field with a bit width that is the same as a bit width of an exponent encoding field from a lowest bit to a highest bit in a true exponent field of the operation result, obtain the exponent encoding field according to the field with the bit width that is the same as the bit width of the exponent encoding field, and extract the true exponent field after the field with the bit width that is the same as the bit width of the exponent encoding field as a numerical value corresponding to the regime encoding field;

the region format determining module is used for determining the filling format of the region coding field according to the symbol field of the operation result and the symbol of the region coding field;

the region field coding module is used for sequentially splicing the filling format, the exponent coding field, the first mantissa field of the operation result and the protection bit field of the operation result by using the second splicing circuit device to obtain a spliced field, and arithmetically right-shifting the spliced field by using the second shifting circuit device according to a numerical value corresponding to the region coding field to obtain the region coding field;

and the floating point number result determining module is used for rounding the spliced field after right shifting by using the protection bit field, and adding the sign field of the operation result to the highest bit of the spliced field after rounding to obtain the Posite floating point number in the specified format.

6. The Posit floating point number processor of claim 5, wherein the encoding circuit further comprises an output module:

the output module is used for directly outputting the Posite floating point number in the specified format as an infinite number encoding field representing an infinite number when the infinite number field of the intermediate data is true;

the output module is further configured to directly output the Posite floating point number in the specified format as an infinity encoded field representing a zero value when the zero value field of the intermediate data is true.

7. The Posit floating point number processor of claim 2, wherein the inverted leading zero detection circuit device comprises an OR device, a first inverting device, a second inverting device;

the reverse leading zero detection circuit device is used for respectively carrying out negation operation on the 0 th bits of a plurality of input fields with the bit width of 2 by using the first negation device, and then respectively carrying out OR operation on a plurality of negation results and the 1 st bits of the plurality of input fields with the bit width of 2 by using the OR device to obtain the 0 th bits of a plurality of output fields; the input field with the bit width of 2 is obtained after the region unified field is processed by a binary circuit;

the reverse leading zero detection circuit device is further configured to perform an or operation on the 0 th bits of the input fields with the bit width of 2 and the 1 st bits of the input fields with the bit width of 2 by using the or device, respectively, to obtain the 1 st bits of the output fields;

the reverse leading zero detection circuit device is also used for splicing the output fields to obtain the inverted code of the value of the region uniform field.

8. The Posit floating point number processor of claim 7, wherein the regime value calculation module comprises:

the region value calculation submodule is used for negating the inverse code output by the reverse leading zero detection circuit device when the real symbol of the region field is positive, and then adding the real symbol of the region field to the highest bit of the inverse code output by the reversed reverse leading zero detection circuit device to obtain the value field of the region field;

and the region value calculation sub-module is further used for adding the real symbol of the region field to the highest bit of the inverse code output by the reverse leading zero detection circuit device when the real symbol of the region field is negative, so as to obtain the value field of the region field.

9. The Posit floating point number processor of claim 5, wherein the floating point number result determination module comprises:

a protection bit sub-module, configured to add 1 to the lowest bit of the right-shifted concatenation field when each bit of the right-shifted concatenation field is 0, and keep the right-shifted concatenation field unchanged when all values of the right-shifted concatenation field are 1;

the protection bit submodule is further configured to, when values of any two bits in the concatenation field after right shift are different and the value of the protection bit is greater than 4, add 1 to the lowest bit of the concatenation field after right shift, or when any two bits in the concatenation field after right shift are different, and when the value of the protection bit is equal to 4 and the lowest bit of the concatenation field after right shift is 1, add 1 to the lowest bit of the concatenation field after right shift.

10. The Posit floating point number processor of claim 5, wherein the exponent field encoding module is further configured to, when the sign field of the intermediate data represents a negative number, invert the field having the same bit width as the exponent encoded field to obtain the exponent encoded field;

and when the sign field of the intermediate data represents a positive number, taking the field with the bit width being the same as that of the exponent encoding field as the exponent encoding field.

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