CN111538262B - Carrier rocket computer self-checking system based on DSP and FPGA - Google Patents
Carrier rocket computer self-checking system based on DSP and FPGA Download PDFInfo
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Abstract
The invention provides a carrier rocket computer self-checking system and a carrier rocket computer self-checking method based on DSP and FPGA, wherein task scheduling and data processing are executed through a DSP main processing module, and management and control and resource allocation are carried out through a communication bus; and the FPGA control module is used for recovering the multi-channel time sequence instruction signals and reading the multi-channel time sequence instruction signals by the DSP, receiving the telemetering information of the DSP main processor, responding to the telemetering subframe synchronizing signal and the word code synchronizing signal, and transmitting the information. The invention has various communication interfaces and high-speed buses, solves the problem that the data of a single CPU can not be effectively transmitted to a measuring system, and solves the problem that the external interface of the existing product does not realize isolation design.
Description
Technical Field
The invention relates to the technical field of aerospace electronic equipment, in particular to a computer self-checking system of a carrier rocket based on DSP and FPGA.
Background
With the increasing complexity of space missions, the requirements for the self-detection, state monitoring and data processing capabilities of the launch vehicle computer are increasing. Meanwhile, the aerospace application of the domestic high-performance DSP provides guarantee for the safety and the autonomy of the carrier rocket computer. The monitoring single machine which can be used for a control computer of a carrier rocket at present has weak general capability and has the following defects: 1) the isolation design is not carried out with an external interface; 2) the resolution for collecting the multi-channel time sequence signals is weak; 3) the data of other single CPUs cannot be effectively transmitted to the measurement system. Therefore, the current domestic carrier rocket monitoring module is difficult to meet the requirement of carrier rocket flight mission with increasingly improved detection precision requirement.
Patent document CN107918325A provides a multi-channel analog acquisition card, which includes a field side processing module, an optical coupler isolator, and a system side processing module, wherein the field side processing module includes an I/V switching unit, a filtering unit, a digital-to-analog conversion unit, and an overcurrent protection unit, and the system side processing module includes a slave station microprocessor based on EtherCAT protocol, a slave station controller based on EtherCAT protocol, and a memory. The invention adopts the slave station microprocessor of the EtherCAT protocol and the slave station controller based on the EtherCAT protocol to realize the acquisition of multi-path analog quantity, thereby having higher safety factor and good real-time property. In the invention, the overcurrent protection unit, the I/V switching unit, the filtering unit and the like of a plurality of analog quantity acquisition channels are all in separate structures, and signals acquired by analog quantity in the invention need to enter the digital-to-analog conversion unit, so that the data acquisition quantity is large.
Patent document CN206960924U provides a multi-channel data collector, which includes a sensor, an analog switch, a multi-channel AD converter, and an FPGA module. The sensor collects physical signals of the site and converts the physical signals into electrical signals. The analog quantity switch and the sensor are arranged in a one-to-one mode, and the analog quantity switch outputs an electric signal output by the sensor to the multichannel AD converter. The multi-channel AD converter converts the received analog quantity signal into a digital signal and outputs the digital signal to the FPGA module. And the FPGA module performs operation processing on the received digital signals. In the document, a measured physical quantity is sent to an analog quantity switch through a plurality of groups of sensors, a multi-channel AD converter is connected behind the measured physical quantity switch, the resolution ratio of collecting a plurality of paths of measured signals depends on the conversion rate of an AD chip and the switching rate of the analog quantity switch, and the filtering width cannot be set.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a carrier rocket computer self-checking system and method based on DSP and FPGA.
The invention provides a carrier rocket computer self-checking system based on DSP and FPGA, comprising:
the DSP main processing module: executing task scheduling and data processing, and performing management and control and resource allocation through a communication bus;
the FPGA control module: and (3) recovering the multi-channel time sequence command signals and allowing the DSP to read the signals, receiving the telemetering information of the DSP main processor, responding to the telemetering subframe synchronizing signals and the word code synchronizing signals, and transmitting the information.
Preferably, the FPGA control module includes:
the reset control module: electrifying and generating a first reset signal, generating a first signal after the first reset signal is switched by a logic circuit, and carrying out NAND on the first signal and a DONE signal generated by the configuration completion of the FPGA to form a second reset signal and outputting the second reset signal to a CPU and other devices needing to be reset;
the PCM communication control module: processing the subframe synchronizing signal, the word code synchronizing signal and the transmission data signal through a PCM interface;
a time instruction extraction module: supporting the recovery of 48 paths of time command signals, performing filtering and anti-interference processing, then counting data, outputting the rising edge times and/or the falling edge times of the 48 paths of time command signals, and outputting the current level state;
DSP read-write control module: and the DSP read-write control is supported, the data sent by the CPU is received, and the DSP reads and/or writes the data into an internal register.
Preferably, the carrier rocket computer self-checking system based on the DSP and the FPGA further comprises a communication module, the communication module comprises a CAN bus, an isolation serial port and an isolation PCM code transmission interface, a subframe synchronization signal and a word code synchronization signal are used as input signals, and an output drive is used as a PCM output signal.
Preferably, the subframe synchronization signal is active low, and a transmission data signal is sent on the rising edge of the codeword synchronization signal for data transmission.
Preferably, the DSP main processing module is connected with the connector through a CAN interface chip, and the connector adopts an RS422 interface to carry out signal interconnection inside the single machine.
The invention provides a carrier rocket computer self-checking method based on DSP and FPGA, comprising the following steps:
and DSP main processing step: executing task scheduling and data processing, and performing management and control and resource allocation through a communication bus;
FPGA control: and (3) recovering the multi-channel time sequence command signals and allowing the DSP to read the signals, receiving the telemetering information of the DSP main processor, responding to the telemetering subframe synchronizing signals and the word code synchronizing signals, and transmitting the information.
Preferably, the FPGA controlling step includes:
a reset control step: electrifying and generating a first reset signal, generating a first signal after the first reset signal is switched by a logic circuit, and carrying out NAND on the first signal and a DONE signal generated by the configuration completion of the FPGA to form a second reset signal and outputting the second reset signal to a CPU and other devices needing to be reset;
PCM communication control step: processing the subframe synchronizing signal, the word code synchronizing signal and the transmission data signal through a PCM interface;
a time instruction recovery step: supporting the recovery of 48 paths of time command signals, performing filtering and anti-interference processing, then counting data, outputting the rising edge times and/or the falling edge times of the 48 paths of time command signals, and outputting the current level state;
DSP read-write control step: and the DSP read-write control is supported, the data sent by the CPU is received, and the DSP reads and/or writes the data into an internal register.
Preferably, the computer self-checking method of the carrier rocket based on the DSP and the FPGA further comprises a communication step, wherein the communication step comprises a CAN bus, an isolation serial port and an isolation PCM code transmission interface, a subframe synchronizing signal and a word code synchronizing signal are used as input signals, and an output drive is used as a PCM output signal.
Preferably, the subframe synchronization signal is active low, and a transmission data signal is sent on the rising edge of the codeword synchronization signal for data transmission.
Preferably, the management and control and the resource allocation through the communication bus are performed through connection between a CAN interface chip and a connector, and the connector performs single-machine internal signal interconnection through an RS422 interface.
Compared with the prior art, the invention has the following beneficial effects:
1. the invention solves the problem that the external interface of the existing product does not realize isolation design;
2. the invention has various communication interfaces and high-speed buses, and solves the problem that the data of a single CPU can not be effectively transmitted to a measurement system;
3. the invention improves the resolution ratio of collecting multi-channel time sequence signals, greatly improves the capacity of collecting the time sequence signals by the module, and has the minimum recovery pulse width of 50us compared with other common computers.
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Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
FIG. 1 is a block diagram of a module model;
fig. 2 is a functional schematic diagram of an FPGA control unit.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.
As shown in fig. 1, the design of the computation self-test module of the launch vehicle based on DSP and FPGA provided by the present invention includes: the system comprises a hardware product and matched software, wherein the hardware part consists of a DSP main processing unit 1, an FPGA control unit 2 and a communication unit 3, and the software part comprises guide software, control software and application program software. The main processing unit is a DSP processor, and the FPGA control unit is an FPGA chip. Connected to the main processing unit: clock circuit, reset circuit and LDO circuit. The self-checking structure is in a half-wrapping type, and the surface of the structural part is subjected to conductive oxidation treatment.
The DSP processing unit 1 adopts a domestic high-reliability military DSP (DSP processor of the Middle 58), is mainly responsible for multitask scheduling and data processing, and controls and allocates resources to the FPGA control unit and the communication unit through a bus;
the FPGA control unit 2 recovers the multi-channel time sequence instruction signals and provides the signals for the DSP to read, receives the remote sensing information of the DSP main processor, and responds to the word code synchronous signals of the system remote sensing subframe synchronous signals to carry out information transmission. An SRAM type FPGA chip (SMQV series of Shenzhen national micro) is mainly used for generating system control signals, managing and using the storage unit and controlling each communication interface;
the communication unit 3 comprises all communication interfaces of the self-checking system, wherein the communication interfaces comprise various interfaces such as a CAN bus, an isolated serial port signal, an isolated PCM signal and the like, a subframe synchronizing signal and a word code synchronizing signal are input signals, and output drive is a PCM output signal.
The connector is mainly used for inputting 48 paths of time sequence command signals, CAN bus signals and takeoff signals to the power supply and supplying +5V working power required by the power supply.
The 25M crystal oscillator is a clock signal provided for the DSP processing unit, the LDO is a level conversion chip, and a +5V power supply provided by the connector is converted into +3.3V, +2.5V and +1.8V power supplies required by the work of the DSP processing unit and the FPGA control unit.
And the boot software runs on the DSP processing unit and is responsible for hardware equipment initialization, storage area self-correction self-checking and loading and reconstructing application program software.
The application program software runs on the DSP processing unit and comprises functions of receiving measurement information of other CPUs through a CAN interface, reading timing sequence extraction information in the FPGA, responding to a subframe synchronization signal, framing and writing telemetering information into the FPGA, transmitting framing ground measurement information through a serial port, and executing bus communication protocol initialization and task scheduling. The system is responsible for bus communication protocol initialization, multitask scheduling and the like, and additionally supports user software customization.
The control software runs on the FPGA control unit and executes the steps of time sequence signal extraction filtering and counting, DSP read-write control, reset control and ground test communication interface control. And the system is responsible for time sequence data recovery, decoding control, reset control, communication interface control and the like.
As shown in fig. 2, the FPGA control unit functions include reset control, PCM communication control, time instruction recovery and counting, and DSP read-write control functions.
The reset control generates a reset signal, the power-on reset is input into the FPGA, the DONE signal and the non-reset signal are generated after the configuration of the FPGA is completed after the transfer of the logic circuit, and the DONE signal and the non-reset signal are output to the CPU and other devices needing to be reset on the board.
The FPGA supports external communication of a PCM interface, and the PCM interface comprises a subframe synchronous signal, a word code synchronous signal and a data signal; when the subframe synchronizing signal is low and effective, the transmission data is transmitted on the rising edge of the word code synchronizing signal, and the communication speed can reach 1 Mbps.
The FPGA supports 48 maximum 15-31V time instruction signal recovery (with a filtering function, the filtering width can be set by the DSP), and the DSP can carry out value taking and outputs the rising edge (falling edge) times and the current level state of 48 time instruction signals.
The FPGA supports DSP read-write control, and internal register data can be read/written by the DSP.
In this embodiment, the FPGA unit is the SMQV300 of the SRAM type FPGA chip shenzhen guo, and is mainly responsible for generating a system reset signal, performing stope counting on 48 time instruction signals, performing communication control on an external PCM interface, and controlling each communication interface.
The communication unit comprises a CAN bus, an isolation RS422 serial port and an isolation PCM code transmission interface. The CAN interface chip is connected between the DSP chip and the connector, and an SN65HVD233 chip of TI company is selected. The chip is supplied with power by a single power supply of 3.3V and is compatible with ISO 11898. The connectors use the RS422 series from Airborn corporation for stand-alone internal signal interconnection. Serial port interface chip connects between isolation conversion and external signal, chooses for use the chip model to be MAX490, keeps apart and level conversion design through the opto-coupler between serial port interface chip and the DSP processing unit, effectively improves the circuit reliability, and maximum transmission rate is 2.5 Mbps. The PCM signal port is isolated from the input subframe synchronization signal, the word code synchronization signal and the output PCM output signal through an optical coupler, the communication protocol is realized by an FPGA internal program, and PCM code measurement data are output. The serial port signal and the PCM signal are connected with the outside by adopting a highly reliable J36A aviation socket connection mode.
Those skilled in the art will appreciate that, in addition to implementing the system and its various devices, modules, units provided by the present invention as pure computer readable program code, the system and its various devices, modules, units provided by the present invention can be fully implemented by logically programming method steps in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Therefore, the system and various devices, modules and units thereof provided by the invention can be regarded as a hardware component, and the devices, modules and units included in the system for realizing various functions can also be regarded as structures in the hardware component; means, modules, units for performing the various functions may also be regarded as structures within both software modules and hardware components for performing the method.
Those skilled in the art will appreciate that, in addition to implementing the systems, apparatus, and various modules thereof provided by the present invention in purely computer readable program code, the same procedures can be implemented entirely by logically programming method steps such that the systems, apparatus, and various modules thereof are provided in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Therefore, the system, the device and the modules thereof provided by the present invention can be considered as a hardware component, and the modules included in the system, the device and the modules thereof for implementing various programs can also be considered as structures in the hardware component; modules for performing various functions may also be considered to be both software programs for performing the methods and structures within hardware components.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.
Claims (4)
1. A carrier rocket computer self-checking system based on DSP and FPGA is characterized by comprising:
the DSP main processing module: executing task scheduling and data processing, and performing management and control and resource allocation through a communication bus;
the FPGA control module: the method comprises the following steps of (1) acquiring a plurality of paths of timing sequence command signals for the DSP to read, receiving remote-measuring information of a DSP main processor, responding to a remote-measuring subframe synchronizing signal and a word code synchronizing signal, and transmitting the information;
the FPGA control module is characterized by comprising:
the reset control module: electrifying and generating a first reset signal, generating a first signal after the first reset signal is switched by a logic circuit, and carrying out NAND on the first signal and a DONE signal generated by the configuration completion of the FPGA to form a second reset signal and outputting the second reset signal to a CPU and other devices needing to be reset;
the PCM communication control module: processing the subframe synchronizing signal, the word code synchronizing signal and the transmission data signal through a PCM interface;
a time instruction extraction module: supporting the recovery of 48 paths of time command signals, performing filtering and anti-interference processing, then counting data, outputting the rising edge times and/or the falling edge times of the 48 paths of time command signals, and outputting the current level state;
DSP read-write control module: the DSP read-write control is supported, the sending data of the CPU is received, and the DSP reads and/or writes the data into an internal register;
the system is characterized by also comprising a communication module, wherein the communication module comprises a CAN bus, an isolated serial port and an isolated PCM code transmission interface, a subframe synchronous signal and a word code synchronous signal are used as input signals, and an output driver is used as a PCM output signal;
the subframe synchronizing signal is active at a low level, and a transmission data signal is sent at a rising edge of the codeword synchronizing signal for data transmission.
2. A computer self-test system for carrier rockets based on DSP and FPGA as claimed in claim 1, wherein said DSP host processing module is connected to a connector through a CAN interface chip, said connector using RS422 interface for single machine internal signal interconnection.
3. A carrier rocket computer self-checking method based on DSP and FPGA is characterized by comprising the following steps:
and DSP main processing step: executing task scheduling and data processing, and performing management and control and resource allocation through a communication bus;
FPGA control: the method comprises the following steps of (1) acquiring a plurality of paths of timing sequence command signals for the DSP to read, receiving remote-measuring information of a DSP main processor, responding to a remote-measuring subframe synchronizing signal and a word code synchronizing signal, and transmitting the information;
the FPGA control method is characterized by comprising the following steps of:
a reset control step: electrifying and generating a first reset signal, generating a first signal after the first reset signal is switched by a logic circuit, and carrying out NAND on the first signal and a DONE signal generated by the configuration completion of the FPGA to form a second reset signal and outputting the second reset signal to a CPU and other devices needing to be reset;
PCM communication control step: processing the subframe synchronizing signal, the word code synchronizing signal and the transmission data signal through a PCM interface;
a time instruction recovery step: supporting the recovery of 48 paths of time command signals, performing filtering and anti-interference processing, then counting data, outputting the rising edge times and/or the falling edge times of the 48 paths of time command signals, and outputting the current level state;
DSP read-write control step: the DSP read-write control is supported, the sending data of the CPU is received, and the DSP reads and/or writes the data into an internal register;
the method is characterized by also comprising a communication step, wherein the communication step comprises a CAN bus, an isolated serial port and an isolated PCM code transmission interface, a subframe synchronous signal and a word code synchronous signal are used as input signals, and an output driver is used as a PCM output signal;
the subframe synchronizing signal is active at a low level, and a transmission data signal is sent at a rising edge of the codeword synchronizing signal for data transmission.
4. The DSP and FPGA-based launch vehicle computer self-inspection method according to claim 3, wherein the management and control and resource allocation through the communication bus are connected with a connector through a CAN interface chip, and the connector adopts an RS422 interface to perform single-machine internal signal interconnection.
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| CN115075985B (en) * | 2022-05-27 | 2025-06-24 | 华东计算技术研究所（中国电子科技集团公司第三十二研究所） | Method, system and medium for launch vehicle sequential command recovery |
| CN115051770A (en) * | 2022-06-13 | 2022-09-13 | 上海宇航系统工程研究所 | Baseband communication interface, communication system and communication method for carrier rocket |
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| JPH08204626A (en) * | 1995-01-27 | 1996-08-09 | Nec Corp | Radio communication system for stable transmission over long range |
| RU2345933C1 (en) * | 2007-05-29 | 2009-02-10 | Александр Сергеевич Квашин | Multistage carrier rocket |
| CN102135920B (en) * | 2011-01-17 | 2013-06-05 | 中国航天科技集团公司第九研究院第七七一研究所 | Fault injection system for embedded spaceborne computer and injection method thereof |
| CN106507995B (en) * | 2012-04-05 | 2014-10-22 | 上海新跃仪表厂 | A kind of implementation method of the carrier rocket control unit based on 1553B buses |
| CN104569793A (en) * | 2013-10-23 | 2015-04-29 | 上海航天设备制造总厂 | Automatic testing system for multiple rocket carrying instruction converters |
| CN106325292B (en) * | 2016-10-17 | 2019-04-12 | 湖北航天技术研究院总体设计所 | A kind of space transporter general purpose controller |
| US11228880B2 (en) * | 2017-07-01 | 2022-01-18 | Intel Corporation | Methods and devices for vehicular radio communications |
| DE102019106566B3 (en) * | 2019-03-14 | 2020-09-10 | Samson Aktiengesellschaft | Configuration of a two-pole input |
| CN110908274A (en) * | 2019-11-07 | 2020-03-24 | 北京宇航系统工程研究所 | SSPC-based high-reliability redundancy measurement and control system for carrier rocket |
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