CN111510127B - Output Buffer Control Circuit - Google Patents
Output Buffer Control Circuit Download PDFInfo
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- CN111510127B CN111510127B CN202010489741.6A CN202010489741A CN111510127B CN 111510127 B CN111510127 B CN 111510127B CN 202010489741 A CN202010489741 A CN 202010489741A CN 111510127 B CN111510127 B CN 111510127B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
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Abstract
本发明揭示了一种输出缓冲器控制电路，所述控制电路包括：运算放大器；反馈电阻RF；分压电阻；浮动开关，包括第一浮动开关SW1及第二浮动开关SW2，第一浮动开关SW1一端与第一分压电阻R1和第二分压电阻R2电连接，另一端与运算放大器的第二输入端电连接，第二浮动开关SW2一端与第二分压电阻R2和反馈电阻RF电连接，另一端与运算放大器的第二输入端电连接；MOS管开关，包括共栅连接的第一MOS管开关SW3和第二MOS管开关SW4，第一MOS管开关SW3和第二MOS管SW4开关分别与第一分压电阻R1电连接。本发明的输出缓冲器控制电路通过浮动开关控制电压域之间的切换，MOS管开关的漏电流不会流过电阻，大大提高了输出电压的线性度。
The present invention discloses an output buffer control circuit, the control circuit comprising: an operational amplifier; a feedback resistor RF ; a voltage-dividing resistor; a floating switch, comprising a first floating switch SW1 and a second floating switch SW2, one end of the first floating switch SW1 being electrically connected to the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2 , and the other end being electrically connected to the second input end of the operational amplifier, one end of the second floating switch SW2 being electrically connected to the second voltage-dividing resistor R2 and the feedback resistor RF , and the other end being electrically connected to the second input end of the operational amplifier; a MOS tube switch, comprising a first MOS tube switch SW3 and a second MOS tube switch SW4 connected in common gate, the first MOS tube switch SW3 and the second MOS tube switch SW4 being electrically connected to the first voltage-dividing resistor R1, respectively. The output buffer control circuit of the present invention controls the switching between voltage domains through the floating switch, the leakage current of the MOS tube switch will not flow through the resistor, and the linearity of the output voltage is greatly improved.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to an output buffer control circuit.
Background
The output buffer needs to support the output of several voltage domains simultaneously, including switching between outputting positive and negative voltages, e.g. between four voltage domains +va/+vb/-VA/-VB, which needs to be controlled by switches.
Referring to fig. 1, a control circuit in the prior art includes an amplifier, voltage dividing resistors R 1 and R 2(R2＝aR1), a feedback resistor R F, and four MOS transistor switches (NMOS transistor SW1', PMOS transistor SW2', NMOS transistor SW3', PMOS transistor SW 4'), wherein the four MOS transistor switches control the switching of four voltage domains +va/+vb/-VA/-VB, and only one of the four switches can be turned on at the same time. The control circuit has the advantages of convenient switch control and no need of using a level shifter (LEVEL SHIFTER). However, the Leakage current (Leakage) of the MOS transistor of the control circuit at high temperature may affect the output accuracy, for example, when +va voltage domain output is selected, the NMOS transistor SW1' is turned on, the rest of the MOS transistors are turned off, at this time, the Leakage currents of the NMOS transistor SW3' and the PMOS transistor SW4' may flow through the voltage dividing resistor, when the Leakage current is 1nA, the 100k ohm resistor may generate a voltage of 0.1mV, and after the output is amplified, the effect on the linearity of the output voltage may be great.
Accordingly, in view of the above-described problems, it is necessary to provide an output buffer control circuit.
Disclosure of Invention
The invention aims to provide an output buffer control circuit for improving the linearity of an output buffer.
In order to achieve the above object, an embodiment of the present invention provides the following technical solution:
An output buffer control circuit, the control circuit comprising:
The operational amplifier comprises a first input end, a second input end and an output end;
The feedback resistor R F is electrically connected with the output end of the operational amplifier;
The divider resistor comprises a first divider resistor R 1 and a second divider resistor R 2, and is arranged in series with the feedback resistor R F;
The floating switch comprises a first floating switch SW1 and a second floating switch SW2, wherein one end of the first floating switch SW1 is electrically connected with a first voltage dividing resistor R 1 and a second voltage dividing resistor R 2, the other end of the first floating switch SW is electrically connected with a second input end of the operational amplifier, one end of the second floating switch SW2 is electrically connected with a second voltage dividing resistor R 2 and a feedback resistor R F, and the other end of the second floating switch SW2 is electrically connected with the second input end of the operational amplifier;
the MOS tube switch comprises a first MOS tube switch SW3 and a second MOS tube switch SW4 which are connected in a common gate mode, and the first MOS tube switch SW3 and the second MOS tube switch SW4 are respectively and electrically connected with a first voltage dividing resistor R 1.
In an embodiment, the first floating switch SW1 and the second floating switch SW2 are NMOS transistors, the first MOS transistor switch SW3 is an NMOS transistor, and the second MOS transistor switch SW4 is a PMOS transistor.
In one embodiment, the control circuit:
The drain electrode of the first floating switch SW1 is electrically connected with the first voltage dividing resistor R 1 and the second voltage dividing resistor R 2, the source electrode of the second floating switch SW2 is electrically connected with the second voltage dividing resistor R 2 and the feedback resistor R F, the source electrode of the second floating switch SW2 is electrically connected with the second input end of the operational amplifier, the drain electrode voltage of the second floating switch SW2 is V 1, the source electrode voltage is V IM, the grid control voltage of the second floating switch SW2 is V G, and the Bulk voltage is V B;
The source voltage of the first MOS transistor switch SW3 is 0, the source voltage of the second MOS transistor switch SW4 is V R, the drain electrode of the first MOS transistor switch SW3 and the drain electrode of the second MOS transistor switch SW4 are electrically connected with the first voltage dividing resistor R 1, the drain voltage is V RI, and the grid electrode of the first MOS transistor switch SW3 and the grid electrode of the second MOS transistor switch SW4 are connected with the control signal VSEL.
In an embodiment, the input voltage of the first input end of the operational amplifier is V IP, V IP≤VI,VI is a preset voltage threshold, and the source voltage V R of the first MOS switch SW3 is greater than the preset voltage threshold V I.
In one embodiment, the control circuit includes:
A first state, in which the first floating switch SW1 is on, the second floating switch SW2 is off, when V RI = 0 and V IM = 0, V 1 = 0, when V RI＝VR and V IM = 0, V 1＝-aVR, when V RI = 0 and V IM＝VI, V 1＝(1+a)VI, when V RI＝VR and V IM＝VI, V 1＝-aVR+(1+a)VI, wherein a = R 2/R1;
In the second state, the first floating switch SW1 is turned off, and the second floating switch SW2 is turned on, V 1＝VIM,0≤V1≤VI.
In an embodiment, the control circuit further comprises a voltage generating unit for generating a voltage following V 1 or V IM.
In one embodiment, the voltage follower unit includes:
A first voltage comparing unit for acquiring a lower voltage min (V 1,VIM) of V 1 and V IM;
A second voltage comparing unit for acquiring a higher voltage max (V 1,VIM) of V 1 and V IM;
the third resistor and the first control switch are sequentially and electrically connected between the first voltage comparison unit and the second voltage comparison unit;
the first level shifter and the second control switch are electrically connected between the third resistor and the first control switch.
In an embodiment, the voltage follower unit is in a first state, the first level shifter is shorted by the second control switch, min (V 1,VIM) obtained by the first voltage comparing unit is used as the gate control voltage V G and V B＝VG of the second floating switch SW2, max (V 1,VIM) obtained by the first voltage comparing unit is used as the gate control voltage V G and V B＝min(V1,VIM of the second floating switch SW2 after being raised by the first level shifter in a second state, and V G-max(V1,VIM)≥bVTH is used in the second state, wherein b is greater than or equal to 1 and V TH is the threshold voltage of the second floating switch SW 2.
In an embodiment, the voltage follower unit further includes a second level shifter electrically connected to the first voltage comparing unit, where the second level shifter is configured to step down the min (V 1,VIM) obtained by the first voltage comparing unit and output the step down min as V B.
In an embodiment, the first voltage comparing unit includes a first differential pair composed of two PMOS transistors, and the second voltage comparing unit includes a second differential pair composed of two NMOS transistors.
Compared with the prior art, the invention has the following advantages:
According to the output buffer control circuit, the voltage domains are controlled to be switched by the floating switch, so that leakage current of the MOS transistor switch cannot flow through the resistor, and the linearity of output voltage is greatly improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present invention, and other drawings may be obtained according to the drawings without inventive effort to those skilled in the art.
FIG. 1 is a schematic diagram of an output buffer control circuit in the prior art;
FIG. 2 is a schematic diagram of an output buffer control circuit according to an embodiment of the invention;
FIGS. 3a and 3b are schematic diagrams illustrating an output buffer control circuit according to an embodiment of the present invention in a first state and a second state, respectively;
FIG. 4 is a schematic diagram of a voltage follower unit according to an embodiment of the invention;
fig. 5 is a circuit diagram of a specific implementation of the voltage follower unit according to an embodiment of the present invention.
Detailed Description
The present invention will be described in detail below with reference to the embodiments shown in the drawings. The embodiments are not intended to limit the invention, but structural, methodological, or functional modifications of the invention from those skilled in the art are included within the scope of the invention.
Referring to fig. 2, an output buffer control circuit according to an embodiment of the present invention includes:
The operational amplifier comprises a first input end (the same-direction input end+), a second input end (the reverse input end-) and an output end;
The feedback resistor R F is electrically connected with the output end of the operational amplifier;
The divider resistor comprises a first divider resistor R 1 and a second divider resistor R 2, and is arranged in series with the feedback resistor R F;
The floating switch comprises a first floating switch SW1 and a second floating switch SW2, wherein one end of the first floating switch SW1 is electrically connected with a first voltage dividing resistor R 1 and a second voltage dividing resistor R 2, the other end of the first floating switch SW is electrically connected with a second input end of the operational amplifier, one end of the second floating switch SW2 is electrically connected with a second voltage dividing resistor R 2 and a feedback resistor R F, and the other end of the second floating switch SW2 is electrically connected with the second input end of the operational amplifier;
the MOS tube switch comprises a first MOS tube switch SW3 and a second MOS tube switch SW4 which are connected in a common gate mode, and the first MOS tube switch SW3 and the second MOS tube switch SW4 are respectively and electrically connected with a first voltage dividing resistor R 1.
Specifically, the drain electrode of the first floating switch SW1 is electrically connected to the first voltage dividing resistor R 1 and the second voltage dividing resistor R 2, the source electrode is electrically connected to the second input terminal of the operational amplifier, the drain electrode of the second floating switch SW2 is electrically connected to the second voltage dividing resistor R 2 and the feedback resistor R F, the source electrode is electrically connected to the second input terminal of the operational amplifier, the drain electrode voltage of the second floating switch SW2 is V 1, the source electrode voltage is V IM, the gate control voltage of the second floating switch SW2 is V G, and the Bulk voltage is V B;
The source voltage of the first MOS transistor switch SW3 is 0, the source voltage of the second MOS transistor switch SW4 is V R, the drain electrode of the first MOS transistor switch SW3 and the drain electrode of the second MOS transistor switch SW4 are electrically connected with the first voltage dividing resistor R 1, the drain voltage is V RI, and the grid electrode of the first MOS transistor switch SW3 and the grid electrode of the second MOS transistor switch SW4 are connected with the control signal VSEL.
The input voltage of the first input end of the operational amplifier is V IP, the voltage which is more than or equal to 0 and less than or equal to V IP≤VI,VI is a preset voltage threshold, and the source voltage V R of the first MOS transistor switch SW3 is larger than the preset voltage threshold V I.
In this embodiment, the first floating switch SW1 and the second floating switch SW2 are NMOS transistors, the first MOS transistor switch SW3 is an NMOS transistor, and the second MOS transistor switch SW4 is a PMOS transistor. Wherein, SW1, SW3 and SW4 can be controlled by low voltage logic, and the control circuit comprises the following two states according to the control condition of SW 1:
A first state, as shown with reference to fig. 3a, the first floating switch SW1 is on, the second floating switch SW2 is off, V 1 = 0 when V RI = 0 and V IM = 0, V 1＝-aVR when V RI＝VR and V IM = 0, V 1＝(1+a)VI when V RI = 0 and V IM＝VI, V 1＝-aVR+(1+a)VI when V RI＝VR and V IM＝VI, wherein a = R 2/R1;
in the second state, referring to FIG. 3b, the first floating switch SW1 is closed and the second floating switch SW2 is turned on, V 1＝VIM,0≤V1≤VI.
When the first floating switch SW1 is turned on in the first state, a negative voltage occurs at one end (V 1 end) of the second floating switch SW2, which is described as follows:
Let a=1, when VSEL selects the second MOS transistor switch SW4 (PMOS transistor) to be turned on, i.e., V RI＝VR, while SW1 is turned on SW2 to be turned off, V IP =0v, at this time V 1＝-VR, if the gate voltage V G =0v of SW2 cannot be completely turned off, a voltage lower than-V R is required to control the gate of SW2 to turn off SW 2. In addition, the substrate of SW2 also needs to be switched to a more negative voltage between source and drain, at which time V IM>V1.
When V RI =0v, the voltage of V 1 can be up to 2*V I, at which time V IM<V1.
The relationship of V RI、V1、VIM in both cases is shown in the following table:
| VRI | V1(VIM=0) | V1(VIM＝VI) |
| 0V | 0 | (1+a)VI |
| VR | -aVR | -aVR+(1+a)VI |
Thus, in different cases, SW2 needs to generate a voltage control gate that needs to be switched lower than the source and drain to turn off SW2.
V 1＝VIM, i.e., V 1, needs to vary between 0~V I when SW1 is off and SW2 is on in the first state. At this time, the gate of SW2 needs to be higher than the V 1/VIM terminal by at least 1V TH or more, and preferably 2V TH or more in order to ensure a sufficiently small on-resistance.
In this embodiment, the VSEL control is used to control the output of the positive voltage domain or the negative voltage domain, and the switch between the voltage domains is controlled by the SW1 and SW2 switches. Leakage current of the MOS transistor switches SW3 and SW4 does not flow through the resistor, so that output accuracy is not affected. The floating switches SW1 and SW2 are made small because they do not need to flow current during operation, and the leakage current is negligible.
According to the above description, in order to control the gate voltage V G of SW2 and generate the corresponding Bulk voltage V B, a voltage following V 1 or V IM needs to be generated according to different applications.
Referring to fig. 4, the voltage follower unit in the present embodiment includes:
A first voltage comparing unit (smaller) for acquiring a lower voltage min (V 1,VIM) of V 1 and V IM;
A second voltage comparing unit (larger) for acquiring a higher voltage max (V 1,VIM) of V 1 and V IM;
the third resistor R3 and the first control switch are sequentially and electrically connected between the first voltage comparison unit (smaller) and the second voltage comparison unit (larger);
The first level shifter (LEVEL SHIFTER) and the second control switch are electrically connected between the third resistor R3 and the first control switch.
In the first state, the voltage follower unit is shorted by the second control switch, min (V 1,VIM) obtained by the first voltage comparing unit is used as the gate control voltage V G and V B＝VG of the second floating switch SW 2;
In the second state, the voltage follower unit adopts max (V 1,VIM) obtained by the first voltage comparing unit and uses the max as the gate control voltage V G and V B＝min(V1,VIM of the second floating switch SW2 after being raised by the first level shifter. At this time, V G-max(V1,VIM)≥bVTH, where b.gtoreq.1, V TH is the threshold voltage of the second floating switch SW 2.
Specifically, when VSW is at a high level, SW2 needs to be turned off, and the lower of V 1/VIM is selected as the gate control signal V G of SW2 by the first voltage comparing unit, at which time the second control switch in the middle shorts the first level shifter, causing V G＝VB.
When VSW is low level [ ]High level), SW2 needs to be turned on, the higher one of V 1/VIM is selected by the second voltage comparing unit, and V G is 2V TH higher than max (V 1,VIM) by the first level shifter, so that SW2 can have smaller on-resistance.
Since Bulk voltage V B always uses the lower of V 1/VIM, bulk voltage can be guaranteed to be the lowest voltage of the NMOS transistor.
Referring to fig. 5, a specific implementation circuit of the voltage follower unit in this embodiment is shown, where the first voltage comparing unit (smaller) includes a first differential pair composed of two PMOS transistors, and the second voltage comparing unit (larger) includes a second differential pair composed of two NMOS transistors.
Specifically, the first voltage comparing unit (smaller) includes a first differential pair formed by two PMOS transistors P1 and P2, the gate voltages of the PMOS transistors P1 and P2 are V 1 and V IM respectively, the source is connected to the current source I1, the drain is connected to the resistor R 5、R6 in series and then connected to the current source I2, and the voltage between the resistor R 5 and the current source I2 is V B.
The second voltage comparing unit (lager) comprises a second differential pair consisting of two NMOS tubes N1 and N2, the grid voltages of the NMOS tubes N1 and N2 are V 1 and V IM respectively, the source electrode is connected with a resistor R 3 and then is electrically connected with a current source I2, the drain electrode is connected with a resistor R 7、R8 in series and then is electrically connected with a switch S1 and a current source I3, the switch S1 is a PMOS tube, the switch S1 is used for controlling whether the second voltage comparing unit works, and the grid driving signal is VSW. The voltage between the second voltage comparing unit and the resistor R 3 is V B.
The first level shifter comprises two NMOS transistors N3 and N4 connected in series, and the two NMOS transistors are used for outputting the acquired max (V 1,VIM) as V G after being raised. N4 has its source electrode connected to V A, its gate electrode and drain electrode electrically connected to the source electrode of N3, N3 has its gate electrode and drain electrode voltage V G, and its connection resistor R 4 is electrically connected to resistor R 3, N3 and N4 are electrically connected to current source I4 via switch S2, switch S2 is a PMOS tube for controlling the first level converter to work or not, its gate driving signal is
The second level shifter comprises two NMOS tubes N5 and N6 connected in series, and the two NMOS tubes are used for reducing the voltage of min (V 1,VIM) acquired by the first voltage comparison unit and then outputting the reduced voltage as V B.
Specifically, in this embodiment, min (V 1,VIM) and max (V 1,VIM) are selected by the NMOS and PMOS differential pairs as the first voltage comparing unit (smaller) and the second voltage comparing unit (larger), respectively. Wherein min (V 1,VIM) is reduced by two V GS, and then used as Bulk voltage V B.
The switch S1 controls whether the second voltage comparing unit (larger) is operated, and when S1 is turned off, a current does not flow through the second voltage comparing unit (larger), which is not operated. At this time S2 is on, and since no current flows through R3 and R4, V A＝VG＝VB, switch SW2 is on.
When S1 is on, S2 is off, and the second voltage comparing unit (larger) can work normally, V A＝max(V1,VIM) and current flows through the first level converter formed by a plurality of V GS through S2, so that a V G with higher voltage is generated to open SW2.
It should be understood that the voltage follower unit in the above embodiment is only one implementation circuit of the present invention, and that other voltage follower circuits may be used in other embodiments to follow the voltage V 1 or V IM, which is not illustrated here.
The technical scheme shows that the invention has the following beneficial effects:
According to the output buffer control circuit, the voltage domains are controlled to be switched by the floating switch, so that leakage current of the MOS transistor switch cannot flow through the resistor, and the linearity of output voltage is greatly improved.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment contains only one independent technical solution, and that such description is provided for clarity only, and that the technical solutions of the embodiments may be appropriately combined to form other embodiments that will be understood by those skilled in the art.
Claims (10)
1. An output buffer control circuit, the control circuit comprising:
The operational amplifier comprises a first input end, a second input end and an output end;
The feedback resistor R F is electrically connected with the output end of the operational amplifier;
The divider resistor comprises a first divider resistor R 1 and a second divider resistor R 2, and is arranged in series with the feedback resistor R F;
the floating switch comprises a first floating switch SW1 and a second floating switch SW2, wherein one end of the first floating switch SW1 is electrically connected with a first voltage dividing resistor R 1 and a second voltage dividing resistor R 2, the other end of the first floating switch SW is electrically connected with a second input end of the operational amplifier, one end of the second floating switch SW2 is electrically connected with a second voltage dividing resistor R 2 and a feedback resistor R F, the other end of the second floating switch SW2 is electrically connected with the second input end of the operational amplifier, signals of a control end of the first floating switch SW1 and signals of a control end of the second floating switch SW2 are opposite signals, and the floating switch is used for controlling switching between voltage domains;
the MOS tube switch comprises a first MOS tube switch SW3 and a second MOS tube switch SW4 which are connected in a common gate mode, and the first MOS tube switch SW3 and the second MOS tube switch SW4 are respectively and electrically connected with a first voltage dividing resistor R 1.
2. The output buffer control circuit of claim 1, wherein the first floating switch SW1 and the second floating switch SW2 are NMOS transistors, the first MOS transistor switch SW3 is an NMOS transistor, and the second MOS transistor switch SW4 is a PMOS transistor.
3. The output buffer control circuit according to claim 2, wherein in the control circuit:
The drain electrode of the first floating switch SW1 is electrically connected with the first voltage dividing resistor R 1 and the second voltage dividing resistor R 2, the source electrode of the second floating switch SW2 is electrically connected with the second voltage dividing resistor R 2 and the feedback resistor R F, the source electrode of the second floating switch SW2 is electrically connected with the second input end of the operational amplifier, the drain electrode voltage of the second floating switch SW2 is V 1, the source electrode voltage is V IM, the grid control voltage of the second floating switch SW2 is V G, and the Bulk voltage is V B;
The source voltage of the first MOS transistor switch SW3 is 0, the source voltage of the second MOS transistor switch SW4 is V R, the drain electrode of the first MOS transistor switch SW3 and the drain electrode of the second MOS transistor switch SW4 are electrically connected with the first voltage dividing resistor R 1, the drain voltage is V RI, and the grid electrode of the first MOS transistor switch SW3 and the grid electrode of the second MOS transistor switch SW4 are connected with the control signal VSEL.
4. The output buffer control circuit of claim 3, wherein the input voltage at the first input terminal of the operational amplifier is V IP, V IP≤VI,VI is a predetermined voltage threshold, and the source voltage V R of the first MOS transistor switch SW3 is greater than the predetermined voltage threshold V I.
5. The output buffer control circuit of claim 4, wherein the control circuit comprises:
A first state, in which the first floating switch SW1 is on, the second floating switch SW2 is off, when V RI = 0 and V IM = 0, V 1 = 0, when V RI＝VR and V IM = 0, V 1＝-aVR, when V RI = 0 and V IM＝VI, V 1＝(1+a)VI, when V RI＝VR and V IM＝VI, V 1＝-aVR+(1+a)VI, wherein a = R 2/R1;
In the second state, the first floating switch SW1 is turned off, and the second floating switch SW2 is turned on, V 1＝VIM,0≤V1≤VI.
6. The output buffer control circuit of claim 5, further comprising a voltage follower unit for generating a voltage that follows V 1 or V IM.
7. The output buffer control circuit according to claim 6, wherein the voltage following unit includes:
A first voltage comparing unit for acquiring a lower voltage min (V 1,VIM) of V 1 and V IM;
A second voltage comparing unit for acquiring a higher voltage max (V 1,VIM) of V 1 and V IM;
the third resistor and the first control switch are sequentially and electrically connected between the first voltage comparison unit and the second voltage comparison unit;
the first level shifter and the second control switch are electrically connected between the third resistor and the first control switch.
8. The output buffer control circuit according to claim 7, wherein the voltage follower unit is short-circuited by the second control switch in a first state, min (V 1,VIM) obtained by the first voltage comparing unit is used as the gate control voltage V G and V B＝VG of the second floating switch SW2, max (V 1,VIM) obtained by the first voltage comparing unit is used as the gate control voltage V G and V B＝min(V1,VIM of the second floating switch SW2 after being raised by the first level shifter in a second state, and V G-max(V1,VIM)≥bVTH is used as the gate control voltage V3962 of the second floating switch SW2 in a second state, wherein b is equal to or greater than 1 and V TH is the threshold voltage of the second floating switch SW 2.
9. The output buffer control circuit according to claim 8, wherein the voltage follower unit further comprises a second level shifter electrically connected to the first voltage comparator unit, the second level shifter being configured to step down min (V 1,VIM) obtained by the first voltage comparator unit and output the stepped down min as V B.
10. The output buffer control circuit of claim 7, wherein the first voltage comparison unit comprises a first differential pair of two PMOS transistors and the second voltage comparison unit comprises a second differential pair of two NMOS transistors.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110771043A (en) * | 2017-06-19 | 2020-02-07 | 派赛公司 | Timing controller for dead time control |
| CN107659304A (en) * | 2017-09-13 | 2018-02-02 | 宁波大学 | Pre-add redrive circuit based on cascade pseudo differential architectures |
| CN211930619U (en) * | 2020-06-02 | 2020-11-13 | 思瑞浦微电子科技（苏州）股份有限公司 | Output buffer control circuit |
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|---|---|
| CN111510127A (en) | 2020-08-07 |
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