CN111509971B - Integrated circuit, packaging structure and manufacturing method - Google Patents

Abstract

The present invention provides an integrated circuit, a package structure and a manufacturing method, wherein the integrated circuit includes a first power transistor, a second power transistor and an isolator. The first power transistor is integrated with the first driving circuit. The second power transistor is integrated with the second driving circuit. The isolator provides a first control signal to the first power transistor and a second control signal to the second power transistor according to the input signal.

Description

Integrated circuit, package structure, and manufacturing method

technical field

The present invention relates to a driving circuit integrating a gallium nitride (GaN) power transistor, in particular to a package structure including a driving circuit, an isolator and a gallium nitride power transistor.

Background technique

In a power circuit, it is often necessary to use a charge pump to boost the supply voltage to a higher voltage to drive the power transistors. Figure 1 shows a general power circuit. In the power circuit 100 shown in FIG. 1 , the upper bridge driving circuit DRV1 is used to drive the first power transistor 110A, and the lower bridge driving circuit DRV2 is used to drive the second power transistor 110B. In addition, the boosting capacitor CB and the boosting diode DB are used to boost the supply voltage VDD to the boosting voltage VB, so that the first power transistor 110A can be fully turned on. Therefore, the first power transistor 110A is supplied by the input voltage VIN, and the second power transistor 110B can drive the load device RL through the inductor L and the capacitor C.

Because the inductance L will produce significant parasitic effects on the switching node SW, such as a negative voltage surge on the switching node SW through the conducting body diode of the second power transistor 110B, these parasitic effects will be The boost capacitor CB interferes with the boost voltage VB when charged through the power transistor. Therefore, it is necessary to reduce the parasitic effect of the driving circuit.

SUMMARY OF THE INVENTION

In view of this, the present invention provides an integrated circuit including a first power transistor, a second power transistor and an isolator. The above-mentioned first power transistor is integrated with a first driving circuit. The above-mentioned second power transistor is integrated with a second driving circuit. The isolator can provide a first control signal to a first power transistor and a second control signal to a second power transistor according to an input signal.

According to an embodiment of the present invention, the integrated circuit further includes a first power circuit and a second power circuit. The first power circuit includes the first drive circuit and the first power transistor, and the second power circuit includes the second drive circuit and the second power transistor.

According to an embodiment of the present invention, the integrated circuit further includes a bootstrap diode and a bootstrap capacitor. The bootstrap diode includes a bootstrap anode and a bootstrap cathode, wherein the bootstrap anode is coupled to a first supply voltage, and the bootstrap cathode is coupled to a second supply voltage. The bootstrap capacitor is coupled to the second supply voltage and a switch voltage of a switch node.

According to an embodiment of the present invention, the first driving circuit is powered by the second supply voltage and the switching voltage, and can generate a first driving voltage at a first driving node according to the first control signal, wherein the above The first power transistor can supply a high voltage to the switching node according to the driving voltage.

According to an embodiment of the present invention, the second driving circuit is powered by the first supply voltage and a second ground terminal, and can generate a second driving voltage at a second driving node according to the second control signal, The second power transistor can pull down the switching voltage to the first ground terminal according to the second driving voltage.

According to an embodiment of the present invention, each of the first power transistor and the second power transistor is a gallium nitride transistor.

According to an embodiment of the present invention, the high voltage exceeds the first supply voltage and the second supply voltage.

According to an embodiment of the present invention, the above-mentioned isolator includes a first sub-isolator and a second sub-isolator. The first sub-isolator includes a first transmitter, a first receiver, and a first isolation barrier. The first transmitter is powered by a third supply voltage and a second ground terminal, and can transmit a first radio frequency signal according to the input signal. The first receiver is powered by a second supply voltage and the switching voltage, and can generate the first control signal according to the first radio frequency signal. The first isolation barrier is used to electrically isolate the first transmitter and the first receiver. The second sub-isolator includes a second transmitter, a second receiver, and a second isolation barrier. The second transmitter is powered by a third supply voltage and a second ground terminal, and can transmit a second radio frequency signal according to the input signal. The second receiver is powered by the first supply voltage and the first ground terminal, and can generate the second control signal according to the second radio frequency signal. The second isolation barrier is used to electrically isolate the second transmitter and the second receiver.

According to an embodiment of the present invention, the above-mentioned isolator includes a transmitter, a first receiver, a first isolation barrier, a second receiver, and a second isolation barrier. The transmitter is powered by a third supply voltage and a second ground terminal, and can transmit a first radio frequency signal and a second radio frequency signal according to the input signal. The first receiver is powered by the second supply voltage and the switching voltage, and can generate the first control signal according to the first radio frequency signal. The first isolation barrier is used to electrically isolate the transmitter and the first receiver. The second receiver is powered by the first supply voltage and the first ground terminal, and can generate the second control signal according to the first radio frequency signal. The second isolation barrier is used to electrically isolate the transmitter and the second receiver.

According to an embodiment of the present invention, the integrated circuit further includes a decoupling capacitor. The decoupling capacitor is coupled between the high voltage and the first ground terminal, wherein the first sub-isolator, the second sub-isolator, the first power circuit, the second power circuit and the decoupling capacitor packaged together.

According to an embodiment of the present invention, each of the first power circuit and the second power circuit includes a pre-driver circuit. The pre-driving circuit can generate the first internal signal according to a control signal, wherein the pre-driving circuit is used to improve the driving capability of the control signal, and a driving circuit can generate a driving voltage according to the first internal signal.

According to an embodiment of the present invention, each of the first power circuit and the second power circuit further includes an upper-bridge transistor, a lower-bridge transistor, and a charge pump. The above-mentioned high-bridge transistor can provide a supply voltage to a driving node according to a high-bridge voltage of a high-bridge node. The lower bridge transistor can couple the driving node to a ground terminal according to the first internal signal. The charge pump is coupled to the upper bridge node and the driving node, wherein the charge pump is used for generating the upper bridge voltage exceeding the supply voltage according to the first internal signal.

According to an embodiment of the present invention, each of the first power circuit and the second power circuit further includes a hysteresis circuit. The hysteresis circuit is coupled between the control signal and the pre-driving circuit, and can be used to receive the control signal to generate a second internal signal, so that the pre-driving circuit can generate the first internal signal according to the second internal signal. The internal signal, wherein the hysteresis circuit is used to provide a hysteresis function to the control signal.

According to an embodiment of the present invention, each of the first power circuit and the second power circuit further includes an upper-bridge normally-on transistor. The above-mentioned high-bridge normally-on transistor includes a source terminal coupled to the above-mentioned driving node, a gate terminal coupled to the above-mentioned driving node, and a drain terminal powered by the above-mentioned supply voltage, wherein the above-mentioned high-bridge normally-on transistor is used to improve the above-mentioned high drive capability of the bridge transistor.

The present invention further provides a package structure, comprising: a substrate, a decoupling capacitor, an integrated circuit and a wire layer. The decoupling capacitor is located on the substrate. The integrated circuit and the decoupling capacitor are fixed in a first dielectric layer. The wire layer is used for electrically coupling the decoupling capacitor to the integrated circuit, wherein the wire layer is located in the first dielectric layer and passes through a second dielectric layer.

According to an embodiment of the present invention, the decoupling capacitor includes a first conductive unit, a first dielectric unit and a second conductive unit. The first conductive unit is formed in the first dielectric layer. The first dielectric unit is formed on the first conductive unit. The second conductive unit is formed on the first dielectric unit.

According to an embodiment of the present invention, the package structure further includes a bootstrap capacitor. The bootstrap capacitor is located on the substrate, wherein the integrated circuit and the bootstrap capacitor are fixed in the first dielectric layer or the second dielectric layer.

According to an embodiment of the present invention, the bootstrap capacitor includes a third conductive unit, a second dielectric unit and a fourth conductive unit. The third conductive unit is formed in the first dielectric layer. The second dielectric unit is formed on the first conductive unit. The fourth conductive unit is formed on the second dielectric unit.

According to an embodiment of the present invention, the materials of the first dielectric unit and the second dielectric unit are different from the materials of the first dielectric layer and the second dielectric layer.

According to an embodiment of the present invention, the above-mentioned integrated circuit includes an isolator, a first power circuit and a second power circuit. The isolator can provide a first control signal and a second control signal according to an input signal. The above-mentioned first power circuit includes a first driving circuit and a first power transistor. The first driving circuit is powered by a second supply voltage and a switching voltage, and can generate a first driving voltage at a first driving node according to the first control signal, wherein a bootstrap diode and the bootstrap capacitor for boosting a first supply voltage to the second supply voltage, wherein the bootstrap diode includes a bootstrap anode coupled to the first supply voltage and a bootstrap cathode coupled to the second supply voltage , wherein the bootstrap capacitor is coupled between the second supply voltage and the switch voltage of a switch node. The first power transistor can supply a high voltage to the switching node according to the first driving voltage. The above-mentioned second power circuit includes a second driving circuit and a second power transistor. The second driving circuit is powered by the first supply voltage and a first ground terminal, and generates a second driving voltage at a second driving node according to the second control signal. The second power transistor can pull down the switching voltage to the first ground terminal according to the second driving voltage.

According to an embodiment of the present invention, each of the first power transistor and the second power transistor is a gallium nitride transistor.

According to an embodiment of the present invention, the above-mentioned isolator includes a first sub-isolator and a second sub-isolator. The first sub-isolator includes a first transmitter, a first receiver, and a first isolation barrier. The first transmitter is powered by a third supply voltage and a second ground terminal, and can transmit a first radio frequency signal according to the input signal. The first receiver is powered by a second supply voltage and the switching voltage, and can generate the first control signal according to the first radio frequency signal. The first isolation barrier is used to electrically isolate the first transmitter and the first receiver. The second sub-isolator includes a second transmitter, a second receiver, and a second isolation barrier. The second transmitter is powered by a third supply voltage and a second ground terminal, and can transmit a second radio frequency signal according to the input signal. The second receiver is powered by the first supply voltage and the first ground terminal, and can generate the second control signal according to the second radio frequency signal. The second isolation barrier is used to electrically isolate the second transmitter and the second receiver.

According to an embodiment of the present invention, the above-mentioned isolator includes a transmitter, a first receiver, a first isolation barrier, a second receiver, and a second isolation barrier. The transmitter is powered by a third supply voltage and a second ground terminal, and can transmit a first radio frequency signal and a second radio frequency signal according to the input signal. The first receiver is powered by the second supply voltage and the switching voltage, and can generate the first control signal according to the first radio frequency signal. The first isolation barrier is used to electrically isolate the transmitter and the first receiver. The second receiver is powered by the first supply voltage and the first ground terminal, and can generate the second control signal according to the first radio frequency signal. The second isolation barrier is used to electrically isolate the transmitter and the second receiver.

According to an embodiment of the present invention, the decoupling capacitor is coupled between the high voltage and the first ground terminal.

According to an embodiment of the present invention, each of the first power circuit and the second power circuit includes a pre-driver circuit. The pre-driving circuit can generate the first internal signal according to a control signal, wherein the pre-driving circuit is used to improve the driving capability of the control signal, and a driving circuit generates a driving voltage according to the first internal signal.

According to an embodiment of the present invention, each of the first power circuit and the second power circuit includes an upper-bridge transistor, a lower-bridge transistor, and a charge pump. The above-mentioned high-bridge transistor can provide a supply voltage to a driving node according to a high-bridge voltage of a high-bridge node. The lower bridge transistor can couple the driving node to a ground terminal according to the first internal signal. The charge pump is coupled to the upper bridge node and the driving node, wherein the charge pump is used for generating the upper bridge voltage exceeding the supply voltage according to the first internal signal.

According to an embodiment of the present invention, the upper-bridge transistor and the lower-bridge transistor are both normally-off transistors.

The present invention also provides a manufacturing method for manufacturing a package structure, comprising: providing a decoupling capacitor and placing it on a substrate; providing an integrated circuit and placing it on the substrate;

The decoupling capacitor and the integrated circuit are fixed by a first dielectric, and a first dielectric layer is formed; a wire layer is formed on the first dielectric layer, so that the decoupling capacitor is electrically connected through the wire layer. coupled to the integrated circuit; and fix the wire layer and the first dielectric layer through a second dielectric, and form a second dielectric layer and place it on the first dielectric layer.

According to an embodiment of the present invention, the step of providing the decoupling capacitor and placing it on the substrate further includes: forming a first conductive unit in the first dielectric layer; forming a first dielectric unit on the first on the conductive unit; and forming a second conductive unit on the first dielectric unit.

According to an embodiment of the present invention, the manufacturing method further includes: providing a bootstrap capacitor on the substrate; and fixing the bootstrap capacitor, the decoupling capacitor and the integrated circuit through the first dielectric, and forming the first dielectric layer.

According to an embodiment of the present invention, the step of providing the bootstrap capacitor to be placed on the substrate further includes: forming a third conductive unit in the first dielectric layer; forming a second dielectric unit on the third on the conductive unit; and forming a fourth conductive unit on the second dielectric unit.

According to an embodiment of the present invention, the above-mentioned integrated circuit includes an isolator, a first power circuit and a second power circuit. The isolator includes a first supply node, a second supply node, a third supply node, a fourth supply node, a first reference node, a second reference node, a third reference node, and a fourth reference node node, a first input node, a second input node, a first output node, and a second output node. The first power circuit includes a fifth supply node coupled to the second supply node, a sixth supply node, a fifth reference node coupled to the second reference node, and a power supply coupled to the first output node. a first PWM node. The second power circuit includes a seventh supply node coupled to the fourth supply node, an eighth reference node coupled to the fifth reference node, a sixth reference node and coupled to the second output node a second PWM node.

According to an embodiment of the present invention, the manufacturing method further includes: forming a first conductive layer on the substrate, wherein the first power circuit and the bootstrap capacitor are placed on the first conductive layer. The first conductive layer is coupled to a first end of the bootstrap capacitor and the fifth reference node, a second end of the bootstrap capacitor is coupled to the fifth supply node through the wire layer, wherein the sixth The supply node is coupled to a third terminal of the decoupling capacitor through the wire layer.

According to an embodiment of the present invention, the manufacturing method further includes: forming a second conductive layer on the substrate. The second power circuit and the decoupling capacitor are placed on the second conductive layer, wherein the second conductive layer is coupled to a fourth end of the decoupling capacitor and a sixth reference node.

According to an embodiment of the present invention, the manufacturing method further includes: forming a third conductive layer on the substrate, wherein the spacer is located on the third conductive layer.

According to an embodiment of the present invention, the first supply node and the third supply node are powered by a third supply voltage, the second supply node and the fifth supply node are powered by a second supply voltage, The first input node receives an input signal, the second input node receives an inverted input signal, the first output node generates a first control signal, the second output node generates a second control signal, and the fourth supply The node and the seventh supply node are powered by a first supply voltage, the sixth supply node is powered by a high voltage, the first reference node and the third reference node are coupled to a second ground terminal, The fourth reference node and the sixth reference node are coupled to a first ground terminal, wherein the input signal and the inverted input signal are inverted.

According to an embodiment of the present invention, the first power circuit includes a first driving circuit and a first power transistor. The first driving circuit is powered by the second supply voltage and a switching voltage, and generates a first driving voltage at a first driving node according to the first control signal. The first power transistor couples the sixth supply node to the fifth reference node according to the first driving voltage.

According to an embodiment of the present invention, the second power circuit includes a second driving circuit and a second power transistor. The second driving circuit is powered by the first supply voltage and a first ground terminal, and generates a second driving voltage at a second driving node according to the second control signal. The second power transistor couples an eighth supply node to the first ground terminal according to the second driving voltage.

According to an embodiment of the present invention, any one of the first power transistor and the second power transistor is a gallium nitride transistor.

According to an embodiment of the present invention, the above-mentioned integrated circuit further includes a bootstrap diode. The bootstrap diode includes a bootstrap anode terminal and a bootstrap cathode terminal, wherein the bootstrap anode terminal is coupled to a first supply voltage, and the bootstrap cathode terminal is coupled to a second supply voltage.

According to an embodiment of the present invention, the high voltage exceeds the first supply voltage and the second supply voltage.

According to an embodiment of the present invention, the above-mentioned isolator includes a first sub-isolator and a second sub-isolator. The above-mentioned first sub-isolator includes: a first transmitter, a first receiver and a first isolation barrier. The first transmitter is powered by a third supply voltage and a second ground terminal, and transmits a first radio frequency signal according to the input signal. The first receiver is powered by a second supply voltage and the switching voltage, and generates the first control signal according to the first radio frequency signal. The first isolation barrier is used to electrically isolate the first transmitter and the first receiver. The second sub-isolator includes a second transmitter, a second receiver, and a second isolation barrier. The second transmitter is powered by a third supply voltage and a second ground terminal, and transmits a second radio frequency signal according to the input signal. The second receiver is powered by the first supply voltage and the first ground terminal, and generates the second control signal according to the second radio frequency signal. The second isolation barrier is used to electrically isolate the second transmitter and the second receiver.

According to an embodiment of the present invention, each of the first power circuit and the second circuit includes a pre-driver circuit. The pre-driving circuit generates the first internal signal according to a control signal, wherein the pre-driving circuit is used to improve the driving capability of the control signal, and a driving circuit generates a driving voltage according to the first internal signal.

According to an embodiment of the present invention, each of the first power circuit and the second circuit includes an upper-bridge transistor, a lower-bridge transistor, and a charge pump. The above-mentioned upper bridge transistor provides a supply voltage to a driving node according to an upper bridge voltage of an upper bridge node. The lower bridge transistor couples the driving node to a ground terminal according to the first internal signal. The charge pump is coupled to the upper bridge node and the driving node, wherein the charge pump is used for generating the upper bridge voltage exceeding the supply voltage according to the first internal signal.

According to an embodiment of the present invention, each of the first power circuit and the second circuit includes a hysteresis circuit. The hysteresis circuit is coupled between the control signal and the pre-driver circuit, wherein the hysteresis circuit receives the control signal and generates a second internal signal, so that the pre-driver circuit generates the first internal signal according to the second internal signal. an internal signal, wherein the hysteresis circuit is used to provide a hysteresis function to the control signal.

Description of drawings

Figure 1 shows a general power circuit;

FIG. 2 shows a block diagram of a power circuit according to an embodiment of the present invention;

FIG. 3 shows a circuit diagram of the charge pump of the power circuit 200 of FIG. 2 according to an embodiment of the present invention;

FIG. 4 shows a block diagram of a power circuit according to another embodiment of the present invention;

FIG. 5 shows a block diagram of a power circuit according to another embodiment of the present invention;

FIG. 6 shows a block diagram of a power circuit according to another embodiment of the present invention;

7 shows a block diagram of a power circuit according to another embodiment of the present invention;

8 shows a block diagram of a power circuit according to another embodiment of the present invention;

9 shows a block diagram of a power circuit according to another embodiment of the present invention;

10 shows a block diagram of a power circuit according to another embodiment of the present invention;

11 shows a block diagram of an integrated circuit according to another embodiment of the present invention;

12 shows a block diagram of an integrated circuit according to another embodiment of the present invention;

13 shows a block diagram of an integrated circuit according to another embodiment of the present invention;

14 shows a top view of a package structure according to an embodiment of the present invention;

15 shows a cross-sectional view of a package structure according to an embodiment of the present invention;

16A-16B show a top view and a cross-sectional view of a first power circuit according to an embodiment of the present invention; and

FIGS. 17A-17F show a manufacturing flow chart of the package structure 1400 of FIG. 14 and the package structure 1500 of FIG. 15 according to an embodiment of the present invention.

Description of reference numbers:

100, 200, 400, 500, 600, 700, 800, 900, 1000 Power Circuits

110A first power transistor

110B second power transistor

210, 410, 510, 610, 710, 810, 910 power transistors

220, 420, 520, 620, 720, 820, 920, 1020 drive circuit

221 high-side transistor

222 lower bridge transistor

230 Charge Pump

310 The first one-way conduction device

320 Second one-way conduction device

330 Third one-way conduction device

340 switches

421 high-side transistor

423 High Bridge Normally On Transistor

530 first pre-driver circuit

531 The first normally on transistor

532 The first normally closed transistor

630, 730 first pre-driver circuit

640, 740 second pre-driver circuit

641 Second normally on transistor

642 Second normally closed transistor

750, 850, 950, 1050 first hysteresis circuit

751 Third normally closed transistor

752 Fourth normally closed transistor

753 Fifth normally closed transistor

830, 930, 1030 pre-driver circuit

931, 1031 The first sub-pre-driver circuit

932, 1032 Second sub-pre-driver circuit

1033 The third sub-pre-driver circuit

1034 Fourth sub-pre-driver circuit

1100, 1200, 1300 integrated circuits

1110 Isolator

1120 First power circuit

1121 The first drive circuit

1122 first power transistor

1130 Second power circuit

1131 Second drive circuit

1132 second power transistor

1400, 1500 package structure

1401 The first conductive layer

1402 second conductive layer

1403 The third conductive layer

1411 First conductor

1412 Second conductor

1510 first dielectric layer

1520 second dielectric layer

1520a First pinned layer

1520b second fixed layer

1521 Wire Layer

1521a First Metal Unit

1521b Metal Unit

1522 The first conductive unit

1523 First Dielectric Unit

1524 Second Conductive Unit

1525 Third Conductive Unit

1526 Second Dielectric Unit

1527 Fourth Conductive Unit

14 substrate

141 The first carrier

142 Second carrier

143 Third Carrier

DB bootstrap diode

CB bootstrap capacitor

NBA bootstrap anode

NBC Bootstrap Cathode

NSW switch node

SIN input signal

SC1 first control signal

SC2 second control signal

SIN input signal

SINB inverted input signal

VDD1 first supply voltage

VDD2 second supply voltage

VDD3 third supply voltage

VSW switch voltage

VD1 first drive voltage

VD2 second driving voltage

VHV high voltage

GND1 first ground terminal

GND2 Second ground terminal

TX transmitter

T1 first transmitter

T2 second transmitter

R1 first receiver

R2 second receiver

IB1 First Isolation Barrier

IB2 Second Isolation Barrier

RF1 first radio frequency signal

RF2 second radio frequency signal

CD Decoupling Capacitor

NR5 Fifth Reference Node

NR6 sixth reference node

S1, S2 source terminal

G1 gate terminal

D1 drain terminal

H hole

C Capacitor

CB boost capacitor

DRV1 upper bridge driver circuit

DRV2 lower bridge driver circuit

DB boost diode

E1 first sub normally closed transistor

E2 Second sub normally closed transistor

E3 third sub normally closed transistor

E4 fourth sub normally closed transistor

E5 fifth sub normally closed transistor

E6 sixth sub normally closed transistor

E7 seventh sub normally closed transistor

E8 Eighth sub normally closed transistor

D1 first sub normally-on transistor

D2 Second sub normally-on transistor

D3 third sub normally on transistor

D4 fourth sub normally-on transistor

L Inductance

IP power current

R1 first resistor

R2 second resistor

RL load device

RD discharge resistance

SW switch node

VB boost voltage

VDD supply voltage

VD drive voltage

VH high-side voltage

VIN input voltage

SC control signal

SB1 First sub internal signal

SB2 Second sub internal signal

SB3 Third sub internal signal

SI1 First internal signal

SI2 Second internal signal

SI3 Third internal signal

ND driver node

NH bridge node

N1 first node

N2 second node

N3 third node

N4 fourth node

Detailed ways

The following descriptions are examples of the present invention. Its purpose is to illustrate the general principles of the present invention, and should not be regarded as a limitation of the present invention, and the scope of the present invention should be defined by the relevant application documents.

Notably, the following disclosure may provide multiple embodiments or examples for practicing various features of the present invention. The specific component examples and arrangements described below are only used to briefly and briefly illustrate the concept of the present invention, and are not intended to limit the scope of the present invention. Furthermore, the following description may reuse the same reference numerals or words in multiple instances. However, the purpose of re-use is merely to provide a simplified and clear illustration, and not to limit the relationship between the various embodiments and/or configurations discussed below. Furthermore, descriptions in the following description of a feature being connected to, coupled to and/or formed on another feature, etc., may actually encompass a number of different embodiments, including direct contact of the feature, or including other additional The features are formed between the features, etc., such that the features are not in direct contact.

FIG. 2 shows a block diagram of a power circuit according to an embodiment of the present invention. As shown in FIG. 2 , the power circuit 200 includes a power transistor 210 and a driving circuit 220 . The power transistor 210 draws the power current IP according to the driving voltage VD of the driving node ND. According to an embodiment of the present invention, the power transistor 210 is a gallium nitride (GaN) transistor.

The driving circuit 220 includes an upper bridge transistor 221 , a lower bridge transistor 222 and a charge pump 230 . The upper bridge transistor 221 supplies the supply voltage VDD to the driving node ND according to the upper bridge voltage VH of the upper bridge node NH. The lower bridge transistor 222 is coupled between the driving node ND and the ground terminal, and pulls the driving voltage VD to the ground level (level) according to the control signal SC. According to an embodiment of the present invention, the upper bridge transistor 221 and the lower bridge transistor 222 are normally closed transistors.

The charge pump 230 is supplied by the supply voltage VDD and the ground terminal, and the charge pump 230 is coupled to the upper bridge node NH and the driving node ND. In order to turn on the high-side transistor 221 completely, the charge pump 230 is used to generate the high-side voltage VH that exceeds the supply voltage VDD, so that the gate-source voltage of the high-side transistor 221 at least exceeds the threshold voltage (threshold voltage) to supply the voltage VDD is applied to the drive node ND. According to an embodiment of the present invention, the driving circuit 220 is a rail-to-rail driving circuit, so that the driving voltage VD ranges from the supply voltage VDD to the ground level.

FIG. 3 shows a circuit diagram of the charge pump of the power circuit 200 of FIG. 2 according to an embodiment of the present invention. As shown in FIG. 3 , the charge pump 300 coupled to the driving node ND and the upper bridge node NH includes a first one-way conduction device 310, a discharge resistor RD, a capacitor C, a second one-way conduction device 320, and a third one-way conduction device 320. device 330 and switch 340 .

When the supply voltage VDD exceeds the voltage of the first node N1, the first unidirectional conduction device 310 is turned on. When the supply voltage VDD does not exceed the voltage of the first node N1, the first unidirectional conduction device 310 is non-conductive. The capacitor C is coupled between the first node N1 and the second node N2, and the discharge resistor RD is coupled between the first node N1 and the upper bridge node NH.

The second unidirectional conduction device 320 is coupled between the second node N2 and the upper bridge node NH. When the voltage of the second node N2 exceeds the upper bridge voltage VH, the second unidirectional conduction device 320 is turned on. When the voltage of the second node N2 does not exceed the upper bridge voltage VH, the second unidirectional conduction device 320 is non-conductive.

The third unidirectional conduction device 330 is coupled between the driving node ND and the second node N2. When the driving voltage VD of the driving node ND exceeds the voltage of the second node N2, the third unidirectional conduction device 330 is turned on. When the driving voltage VD does not exceed the voltage of the second node N2, the third one-way conduction device 330 is non-conductive.

The switch 340 receives the control signal SC and is coupled between the upper bridge node NH and the ground terminal. In addition, the switch 340 is used for coupling the upper bridge node NH to the ground terminal according to the control signal SC.

To simplify the description, the switch 340 is taken as an example of an N-type transistor. According to an embodiment of the present invention, when the control signal SC is at a high voltage level (eg, the supply voltage VDD), the switch 340 is turned on and the supply voltage VDD charges the capacitor C and passes through the first one-way conduction device 310, the second The two one-way conducting devices 320 and the switch 340 are connected to the ground.

According to another embodiment of the present invention, when the control signal SC is at a low voltage level (eg, ground level), the switch 340 is non-conductive, and the third unidirectional conduction device 330 provides the driving voltage VD to the second node N2 , so that the capacitor C is discharged to the drive node ND through the discharge resistor RD.

According to an embodiment of the present invention, the resistance value of the discharge resistor RD determines the highest voltage that the capacitor C can charge, and also determines the highest voltage that the high-bridge voltage VH can reach. In addition, the larger the resistance value of the discharge resistor RD is, the slower the rise time of the upper bridge voltage VD will be. Therefore, there is a trade-off in the resistance value of the discharge resistor RD.

According to an embodiment of the present invention, each of the first one-way conduction device 310 , the second one-way conduction device 320 and the third one-way conduction device 330 is a diode. According to other embodiments of the present invention, each of the first one-way conduction device 310 , the second one-way conduction device 320 and the third one-way conduction device 330 is a normally-off transistor coupled in the form of a diode.

FIG. 4 shows a block diagram of a power circuit according to another embodiment of the present invention. In the power circuit 400 shown in FIG. 4 , the power transistor 410 and the driving circuit 420 correspond to the power transistor 210 and the driving circuit 220 in FIG. 2 , respectively.

The driving circuit 420 also includes a high-bridge normally-on transistor 423 . Both the source terminal and the gate terminal of the high-bridge normally-on transistor 423 are coupled to the driving node ND, and the drain terminal of the high-bridge normally-on transistor 423 is powered by the supply voltage VDD. The high-bridge normally-on transistor 423 is continuously turned on to improve the driving capability of the high-bridge transistor 221 .

FIG. 5 shows a block diagram of a power circuit according to another embodiment of the present invention. As shown in FIG. 5 , the power circuit 500 includes a power transistor 510 , a driving circuit 520 and a first pre-driving circuit 530 , wherein the power transistor 510 and the driving circuit 520 correspond to the power transistor 210 and the driving circuit 220 in FIG. 2 , respectively.

The first pre-driving circuit 530 receives the control signal SC to generate a first internal signal SI1 to the driving circuit 520 for improving the driving capability of the control signal SC. The first pre-driver circuit 530 includes a first normally-on transistor 531 and a first normally-off transistor 532 .

The gate terminal and the source terminal of the first normally-on transistor 531 are both coupled to the driving circuit 520, and the drain terminal of the first normally-on transistor 531 is powered by the supply voltage. The gate terminal of the first normally closed transistor 532 receives the control signal SC, the source terminal of the first normally closed transistor 532 is coupled to the ground terminal, and the drain terminal of the first normally closed transistor 532 is coupled to the driving circuit 520 .

6 shows a block diagram of a power circuit according to another embodiment of the present invention. As shown in FIG. 6 , the power circuit 600 includes a power transistor 610 , a driving circuit 620 , a first pre-driving circuit 630 and a second pre-driving circuit 640 , wherein the power transistor 610 , the driving circuit 620 and the first pre-driving circuit 630 Corresponding to the power transistor 510 , the driving circuit 520 and the first pre-driving circuit 530 in FIG. 5 , respectively.

The second pre-driving circuit 640 receives the control signal SC to generate a second internal signal SI2 to the first pre-driving circuit 630, so as to further improve the driving capability of the control signal SC. The second pre-driver circuit 640 includes a second normally-on transistor 641 and a second normally-off transistor 642 .

The gate terminal and the source terminal of the second normally-on transistor 641 are both coupled to the gate terminal of the first normally-off transistor 532 of the first pre-driver circuit 630, and the drain terminal of the second normally-on transistor 641 is powered by the supply voltage Powered by VDD. The gate terminal of the second normally closed transistor 642 receives the control signal SC, the source terminal of the second normally closed transistor 642 is coupled to the ground terminal, and the drain terminal of the second normally closed transistor 642 is coupled to the first pre-driving circuit 630 The gate terminal of the first normally closed transistor 532 .

FIG. 7 shows a block diagram of a power circuit according to another embodiment of the present invention. As shown in FIG. 7 , the power circuit 700 includes a power transistor 710, a driving circuit 720, a first pre-driving circuit 730, a second pre-driving circuit 740 and a first hysteresis circuit 750, wherein the power transistor 710, the driving circuit 720, the first A pre-driving circuit 730 and a second pre-driving circuit 740 correspond to the power transistor 610 , the driving circuit 620 , the first pre-driving circuit 630 and the second pre-driving circuit 640 in FIG. 6 , respectively.

The first hysteresis circuit 750 receives the control signal SC to generate a third internal signal SI3 for further providing a hysteresis function to the control signal SC. The first hysteresis circuit 750 includes a first resistor R1, a third normally-closed transistor 751, a fourth normally-closed transistor 752, a fifth normally-closed transistor 753, and a second resistor R2.

The first resistor R1 is coupled between the supply voltage VDD and the gate terminal of the second normally-closed transistor 642 of the second pre-driving circuit 740. The gate terminal of the third normally-closed transistor 751 is coupled to the third node N3, and the third The source terminal of the normally closed transistor 751 is coupled to the fourth node N4 , and the drain terminal of the third normally closed transistor 751 is coupled to the first resistor R1 and the gate terminal of the second normally closed transistor 642 of the second pre-driver circuit 740 . The gate terminal of the fourth normally closed transistor 752 is coupled to the third node N3, the source terminal of the fourth normally closed transistor 752 is coupled to the ground terminal, and the drain terminal of the fourth normally closed transistor is coupled to the fourth node N4.

The gate terminal of the fifth normally closed transistor 753 is coupled to the first resistor R1 and the gate terminal of the second normally closed transistor 642 of the second pre-driver circuit 740 , and the source terminal of the fifth normally closed transistor 753 is coupled to the fourth node N4, the drain terminal of the fifth normally closed transistor 753 is powered by the supply voltage VDD. The second resistor R2 is coupled to the third node N3 and receives the control signal SC.

FIG. 8 shows a block diagram of a power circuit according to another embodiment of the present invention. As shown in FIG. 8 , the power circuit 800 includes a power transistor 810 , a driving circuit 820 , a pre-driving circuit 830 and a first hysteresis circuit 850 , wherein the power transistor 810 , the driving circuit 820 and the first hysteresis circuit 850 correspond to those shown in FIG. 7 , respectively. The power transistor 710 , the driving circuit 720 and the first hysteresis circuit 750 .

According to an embodiment of the present invention, the pre-driving circuit 830 generates the first internal signal SI1 according to the second internal signal SI2 to improve the driving capability of the control signal SC. According to an embodiment of the present invention, the first internal signal SI1 and the second internal signal SI2 are in the same phase.

FIG. 9 shows a block diagram of a power circuit according to another embodiment of the present invention. As shown in FIG. 9 , the power circuit 900 includes a power transistor 910 , a driving circuit 920 , a pre-driving circuit 930 and a first hysteresis circuit 950 , wherein the power transistor 910 , the driving circuit 920 , the pre-driving circuit 930 and the first hysteresis circuit 950 Corresponding to the power transistor 810 , the driving circuit 820 , the pre-driving circuit 830 and the first hysteresis circuit 850 in FIG. 8 , respectively.

As shown in FIG. 9 , the pre-driver circuit 930 includes a first sub-pre-driver circuit 931 and a second sub-pre-driver circuit 932 . The first sub-pre-driver circuit 931 includes a first sub-normally closed transistor E1, a second sub-normally-closed transistor E2 and a first sub-normally-on transistor D1, wherein the first sub-pre-driver circuit 931 is based on the first sub-internal signal SB1 And the first internal signal SI1 is generated.

The gate terminal of the first sub-normally closed transistor E1 receives the first sub-internal signal SB1, and the source terminal of the first sub-normally closed transistor E1 is coupled to the ground terminal. The gate terminal of the second sub normally-off transistor E2 receives the second internal signal SI2. That is, the gate terminal of the second sub-normally closed transistor E2 is coupled to the gate terminal of the third sub-normally closed transistor E3. The drain terminal of the second sub-normally closed transistor E2 is powered by the supply voltage VDD.

The source terminal of the second sub-normally closed transistor E2 is coupled to the drain terminal of the first sub-normally closed transistor E1 , wherein the drain terminal of the first sub-normally closed transistor E1 generates the first internal signal SI1 and is provided to the driving circuit 920 . The gate terminal and the source terminal of the first sub-normally-on transistor D1 are coupled together, and the source terminal of the first sub-normally-on transistor D1 is powered by the supply voltage VDD.

The second sub-pre-driver circuit 932 includes a third sub-normally-closed transistor E3, a fourth sub-normally-closed transistor E4 and a second sub-normally-on transistor D2, wherein the second sub-pre-driver circuit 932 operates according to the second internal signal SI2. A first sub-internal signal SB1 is generated.

The gate terminal of the third sub-normally closed transistor E3 receives the second internal signal SI2, and the source terminal of the third sub-normally closed transistor E3 is coupled to the ground terminal. The gate terminal of the fourth sub-normally closed transistor E4 is coupled to the third node N3 of the first hysteresis circuit 950, and the drain terminal of the fourth sub-normally closed transistor E4 is powered by the supply voltage VDD.

The source terminal of the fourth sub-normally closed transistor E4 is coupled to the drain terminal of the third sub-normally closed transistor E3, wherein the drain terminal of the third sub-normally closed transistor E4 generates the first sub-internal signal SB1 and provides it to the first sub-front-end drive circuit 931 . The gate terminal and the source terminal of the second normally-on transistor D2 are coupled together, and the drain terminal of the second normally-on transistor D2 is powered by the supply voltage VDD.

10 shows a block diagram of a power circuit according to another embodiment of the present invention. As shown in FIG. 10 , the power circuit 1000 includes a power transistor 1010 , a driving circuit 1020 , a pre-driving circuit 1030 and a first hysteresis circuit 1050 , wherein the power transistor 1010 , the driving circuit 1020 , the pre-driving circuit 1030 and the first hysteresis circuit 1050 Corresponding to the power transistor 910 , the driving circuit 920 , the pre-driving circuit 930 and the first hysteresis circuit 950 in FIG. 9 , respectively.

As shown in FIG. 10, the pre-driver circuit 1030 includes a first sub-pre-driver circuit 1031, a second sub-pre-driver circuit 1032, a third sub-pre-driver circuit 1033 and a fourth sub-pre-driver circuit 1034, wherein the first sub-pre-driver circuit 1034 A sub-pre-driving circuit 1031 and a second sub-pre-driving circuit 1032 respectively correspond to the first sub-pre-driving circuit 931 and the second sub-pre-driving circuit 932 in FIG. 9 , and details are not repeated here.

The second sub-pre-driver circuit 1032 includes a third sub-normally closed transistor E3, a fourth sub-normally-closed transistor E4 and a second sub-normally-on transistor D2, wherein the second sub-pre-driver circuit 1032 is based on the second sub-internal signal SB2 And the first sub-internal signal SB1 is generated.

The gate terminal of the third sub-normally closed transistor E3 receives the second sub-internal signal SB2, and the source terminal of the third sub-normally closed transistor E3 is coupled to the ground terminal. The gate terminal of the fourth sub normally closed transistor E4 receives the third sub internal signal SB3. The drain terminal of the fourth sub-normally closed transistor E4 is powered by the supply voltage VDD.

The source terminal of the fourth sub-normally closed transistor E4 is coupled to the drain terminal of the third sub-normally closed transistor E3, wherein the drain terminal of the third sub-normally closed transistor E3 generates the second sub-internal signal SB2 to the first sub-pre-driver circuit 1031. The gate terminal and the source terminal of the second normally-on transistor D2 are coupled together, and the drain terminal of the second normally-on transistor D2 is powered by the supply voltage VDD.

The third sub-pre-driving circuit 1033 includes a fifth sub-normally closed transistor E5, a sixth sub-normally-closed transistor E6 and a third sub-normally-on transistor D3, wherein the third sub-driving circuit 1033 generates the third sub-internal signal SB3 according to the The second sub-internal signal SB2.

The gate terminal of the fifth sub-normally closed transistor E5 receives the third sub-internal signal SB3, and the source terminal of the fifth sub-normally closed transistor E5 is coupled to the ground terminal. The gate terminal of the sixth sub-normally closed transistor E6 receives the second internal signal SI2, and the drain terminal of the sixth sub-normally closed transistor E6 is powered by the supply voltage VDD.

The source terminal of the sixth sub-normally closed transistor E6 is coupled to the drain terminal of the fifth sub-normally closed transistor E5, wherein the drain terminal of the fifth sub-normally closed transistor E5 generates the second sub-internal signal SB2 to the second sub-pre-driver circuit 1032. The gate terminal and the source terminal of the third normally-on transistor D3 are coupled together, and the drain terminal of the third normally-on transistor D3 is powered by the supply voltage VDD.

The fourth sub-pre-driver circuit 1034 includes a seventh sub-normally-closed transistor E7, an eighth sub-normally-closed transistor E8 and a fourth sub-normally-on transistor D4, wherein the fourth sub-pre-driver circuit 1034 operates according to the second internal signal SI2. A third sub-internal signal SB3 is generated.

The gate terminal of the seventh sub-normally closed transistor E7 receives the second internal signal SI2, and the source terminal of the seventh sub-normally closed transistor E7 is coupled to the ground terminal. The gate terminal of the eighth sub normally-off transistor E8 is coupled to the third node N3 of the first hysteresis circuit 1050 . The drain terminal of the eighth sub-normally closed transistor E8 is powered by the supply voltage VDD.

The source terminal of the eighth sub-normally closed transistor E8 is coupled to the drain terminal of the seventh sub-normally closed transistor E7, wherein the drain terminal of the seventh sub-normally closed transistor E7 generates the third sub-internal signal SB3 to the third sub-pre-driver circuit 1033. The gate terminal and the source terminal of the fourth sub-normally-on transistor D4 are coupled together, and the drain terminal of the fourth sub-normally-on transistor D4 is powered by the supply voltage VDD.

According to other embodiments of the present invention, the pre-driver circuit 830 of FIG. 8 may include an even number of sub-pre-driver circuits, so that the phases of the first internal signal SI1 and the second internal signal SI2 are in the same phase.

11 shows a block diagram of an integrated circuit according to another embodiment of the present invention. As shown in FIG. 11 , the integrated circuit 1100 includes an isolator 1110 , a first power circuit 1120 , a second power circuit 1130 , a bootstrap diode DB, and a bootstrap capacitor CB.

The isolator 1110 generates the first control signal SC1 and the second control signal SC2 according to the input signal SIN. According to some embodiments of the present invention, the input signal SIN may be generated externally. As shown in FIG. 11, the inverted input signal SINB is generated by the inverter INV. The isolator 1110 generates the first control signal SC1 according to the inverted input signal SINB, and generates the second control signal SC2 according to the input signal SIN. According to other embodiments of the present invention, the inverted input signal SINB and the input signal SIN may be generated externally.

The first power circuit 1120 includes a first drive circuit 1121 and a first power transistor 1122 , and the second power circuit 1130 includes a second drive circuit 1131 and a second power transistor 1132 . According to an embodiment of the present invention, the first driving circuit 1121 and the second driving circuit 1131 are the same, and the first power transistor 1122 and the second power transistor 1132 are the same.

According to an embodiment of the present invention, both the first driving circuit 1121 and the second driving circuit 1131 may correspond to the driving circuit 220 of FIG. 2 and FIG. 3 , the driving circuit 420 of FIG. 4 , the driving circuit 520 of FIG. The combination of the drive circuit 530, the drive circuit 620 of FIG. 6, the combination of the first pre-drive circuit 630 and the second pre-drive circuit 640, the drive circuit 720 of FIG. 7, the first pre-drive circuit 730, the second pre-drive circuit The combination of the set driving circuit 740 and the first hysteresis circuit 750, the combination of the driving circuit 820, the pre-driving circuit 830, and the first hysteresis circuit 850 of FIG. 8, the driving circuit 920, the pre-driving circuit 930 of FIG. A combination of the hysteresis circuit 950 and one of the combination of the driver circuit 1020 , the pre-driver circuit 1030 , and the first hysteresis circuit 1050 of FIG. 10 .

According to an embodiment of the present invention, both the first power transistor 1122 and the second power transistor 1132 may correspond to the power transistor 210 of FIG. 2 , the power transistor 410 of FIG. 4 , the power transistor 510 of FIG. 5 , and the power transistor 610 of FIG. 6 . , any one of the power transistor 710 of FIG. 7 , the power transistor 810 of FIG. 8 , the power transistor 910 of FIG. 9 , and the power transistor 1010 of FIG. 10 .

As shown in FIG. 11 , the bootstrap diode DB includes a bootstrap anode NBA and a bootstrap cathode NBC, wherein the bootstrap anode NBA is coupled to the first supply voltage VDD1 , and the bootstrap cathode NBC is coupled to the second supply voltage VDD2 . The bootstrap capacitor CB is coupled to the second supply voltage VDD2 and the switch node NSW. According to an embodiment of the present invention, the bootstrap diode DB and the bootstrap capacitor CB are used to push the first supply voltage VDD1 to the second supply voltage VDD2 according to the switching voltage VSW of the switching node NSW.

The first driving circuit 1121 is powered by the second supply voltage VDD2 and the switching voltage VSW, and generates the first driving voltage VD1 according to the first control signal SC1. The first power transistor 1122 provides the high voltage VHV to the switching node NSW according to the first driving voltage VD1.

The second driving circuit 1131 is powered by the first supply voltage VDD1 and the first ground terminal GND1, and generates the second driving voltage VD2 according to the second control signal SC2. The second power transistor 1132 couples the switch node NSW to the first ground terminal GND1 according to the second driving voltage VD2.

According to an embodiment of the present invention, when the first power transistor 1122 is turned off and the second power transistor 1132 is turned on, the switching voltage VSW is coupled to the first ground terminal GND1, and the second supply voltage VDD2 is equal to the first supply voltage The forward voltage of the bootstrap diode DB is subtracted from the voltage VDD1.

According to another embodiment of the present invention, when the first power transistor 1122 is turned on and the second power transistor 1132 is turned off, the switching voltage VSW is coupled to the high voltage VHV, so that the second supply voltage VDD2 is boosted to a high voltage The sum of VHV and the first supply voltage VDD1, thus completely turning on the first power transistor 1122.

12 shows a block diagram of an integrated circuit according to another embodiment of the present invention. As shown in FIG. 12, the integrated circuit 1200 includes an isolator 1110, a first power transistor 1120, a second power circuit 1130, a bootstrap diode DB and a bootstrap capacitor CB, wherein the isolator 1110 includes a transmitter TX, a first receiver R1 , a first isolation barrier IB1, a second receiver R2 and a second isolation barrier IB2.

The transmitter TX is powered by the third supply voltage VDD3 and the second ground terminal GND2, wherein the transmitter TX modulates the input signal SIN to generate the first radio frequency signal RF1 across the first isolation barrier IB1, and modulates the inverted input signal SINB And the second radio frequency signal RF2 that crosses the second isolation barrier IB2 is generated.

The first receiver R1 is powered by the second supply voltage VDD2 and the second switching voltage VSW, wherein the first receiver R1 demodulates the first radio frequency signal RF1 to generate the first control signal SC1. The first isolation barrier IB1 is used to electrically isolate the transmitter TX and the first receiver R1.

The second receiver R2 is powered by the first supply voltage VDD1 and the first ground terminal GND1, wherein the second receiver R2 demodulates the second radio frequency signal RF2 to generate the second control signal SC2. The second isolation barrier IB2 is used to electrically isolate the transmitter TX and the second receiver R2.

According to an embodiment of the present invention, the first ground terminal GND1 may be the same as the second ground terminal GND2. According to another embodiment of the present invention, the first ground terminal GND1 may be different from the second ground terminal GND2. According to an embodiment of the present invention, the high voltage VHV exceeds the first supply voltage VDD1 , the second supply voltage VDD2 and the third supply voltage VDD3 .

According to an embodiment of the present invention, the first supply voltage VDD1 may be the same as the third supply voltage VDD3. According to another embodiment of the present invention, the first supply voltage VDD1 may be different from the third supply voltage VDD3.

As shown in FIG. 12, the integrated circuit 1200 further includes a decoupling capacitor CD. The decoupling capacitor CD is coupled to the high voltage VHV and the first ground terminal GND1. According to an embodiment of the present invention, the isolator 1110, the first power circuit 1120, the second power circuit 1130, and the decoupling capacitor CD are packaged together. According to another embodiment of the present invention, the isolator 1110, the first power circuit 1120, the second power circuit 1130, the bootstrap capacitor CB, and the decoupling capacitor CD are packaged together.

13 shows a block diagram of an integrated circuit according to another embodiment of the present invention. As shown in FIG. 13 , the integrated circuit 1300 includes an isolator 1110 , a first power circuit 1120 , a second power circuit 1130 , a bootstrap diode DB and a bootstrap capacitor CB, wherein the isolator 1110 includes a first sub-isolator 1111 and a second sub-isolator 1110 Sub-isolator 1112.

The first sub-isolator 1111 includes a first transmitter T1, a first receiver R1, and a first isolation barrier IB1. The first transmitter T1 is powered by the third supply voltage VDD3 and the second ground terminal GND2, wherein the first transmitter T1 modulates the input signal SIN to generate the first radio frequency signal RF1 across the first isolation barrier IB1. The first receiver R1 is powered by the second supply voltage VDD2 and the switch voltage SW, wherein the first receiver R1 demodulates the first radio frequency signal RF1 to generate the first control signal SC1. The first isolation barrier IB1 is used to electrically isolate the first transmitter T1 and the first receiver R1.

The second sub-isolator 1112 includes a second transmitter T2, a second receiver R2, and a second isolation barrier IB2. The second transmitter T2 is powered by the third supply voltage VDD3 and the second ground terminal GND2, wherein the second transmitter T2 modulates the inverted input signal SINB to generate the second radio frequency signal RF2 across the second isolation barrier IB2. The second receiver R2 is powered by the first supply voltage VDD1 and the first ground terminal GND1, wherein the second receiver R2 demodulates the second radio frequency signal RF2 to generate the second control signal SC2. The second isolation barrier IB2 is used to electrically isolate the second transmitter T2 and the second receiver R2.

According to an embodiment of the present invention, the first ground terminal GND1 may be the same as the second ground terminal GND2. According to another embodiment of the present invention, the first ground terminal GND1 may be different from the second ground terminal GND2. According to an embodiment of the present invention, the high voltage VHV exceeds the first supply voltage VDD1 , the second supply voltage VDD2 and the third supply voltage VDD3 .

According to an embodiment of the present invention, the first supply voltage VDD1 may be the same as the third supply voltage VDD3. According to another embodiment of the present invention, the first supply voltage VDD1 may be different from the third supply voltage VDD3.

As shown in FIG. 13, the integrated circuit 1300 further includes a decoupling capacitor CD. The decoupling capacitor CD is coupled between the high voltage VHV and the first ground terminal GND1. According to an embodiment of the present invention, the first sub-isolator 1111 , the second sub-isolator 1112 , the first power circuit 1120 , the second power circuit 1130 and the decoupling capacitor CD are packaged together. According to another embodiment of the present invention, the first sub-isolator 1111 , the second sub-isolator 1112 , the first power circuit 1120 , the second power circuit 1130 , the bootstrap capacitor CB and the decoupling capacitor CD are packaged together.

FIG. 14 is a top view showing a package structure according to an embodiment of the present invention. As shown in FIG. 14 , the package structure 1400 includes the decoupling capacitor CD, the bootstrap capacitor CB, the first sub-isolator 1111 , the second sub-isolator 1112 , the first power circuit 1120 and the second power circuit 1130 as shown in FIG. 13 . . According to an embodiment of the present invention, the package structure 1400 is located on the substrate 14 .

As shown in FIG. 14 , the package structure 1400 further includes a first conductive layer 1401 , a second conductive layer 1402 and a third conductive layer 1403 . The first conductive layer 1401 , the second conductive layer 1402 and the third conductive layer 1403 are formed on the substrate 14 .

As shown in FIG. 14 , the first power circuit 1120 and the bootstrap capacitor CB are located on the first conductive layer 1401 . The second power circuit 1130 and the decoupling capacitor CD are located on the second conductive layer 1402 . The first sub-isolator 1111 and the second sub-isolator 1112 are located on the third conductive layer 1403 .

According to an embodiment of the present invention, the first conductive layer 1401 , the second conductive layer 1402 and the third conductive layer 1403 are electrically isolated from each other. According to an embodiment of the present invention, the first conductive layer 1401 is electrically coupled to the first ground terminal GND1, and the second conductive layer 1402 is electrically coupled to the switching voltage VSW, wherein the switching voltage VSW is coupled to the fifth reference node NR5 .

As shown in FIG. 14 , the fifth reference node NR5 is coupled to the source terminal S1 of the first power transistor 1122 , wherein the fifth reference node NR5 is electrically coupled to the first conductive layer 1401 through the wire layer and the first conductor 1411 .

The sixth reference node NR6 is coupled to the source terminal S2 of the second power transistor 1132 , wherein the sixth reference node NR6 is used to electrically connect the wire layer to the second conductive layer 1402 .

According to an embodiment of the present invention, the bootstrap diode DB shown in FIG. 13 is placed outside the package structure 1400 .

15 shows a cross-sectional view of a package structure according to an embodiment of the present invention. As shown in FIG. 15 , the package structure 1500 is shown as a cross-sectional view along the dotted line from the first terminal A to the second terminal A′ in FIG. 14 .

The package structure 1500 includes a substrate 14 , a first sub-isolator 1111 , a first power circuit 1120 , a bootstrap capacitor CB, a decoupling capacitor CD, and a wire layer 1521 . The substrate 14 includes a first carrier 141 , a second carrier 142 and a third carrier 143 , wherein the first carrier 141 , the second carrier 142 and the third carrier 143 are isolated from each other.

The first power circuit 1120 and the bootstrap capacitor CB are located on the first carrier 141 , and the decoupling capacitor CD and the second power circuit 1130 (not shown in FIG. 15 ) are located on the second carrier 142 . The first sub-isolator 1111 and the second sub-isolator 1112 (not shown in FIG. 15 ) are located on the third carrier 143 .

According to some embodiments of the present invention, the first conductive unit 1522 and the first power circuit 1120 are located on the first conductive layer 1401 , wherein the first conductive layer 1401 is located on the first carrier 141 . The decoupling capacitor CD and the second power circuit 1130 (not shown in FIG. 15 ) are located on the second conductive layer 1402 , wherein the second conductive layer 1402 is located on the second carrier 142 . The first sub-isolator 1111 and the second sub-isolator 1112 (not shown in FIG. 15 ) are located on the third conductive layer 1403 , wherein the third conductive layer 1403 is located on the third carrier 143 .

Materials of the first carrier 141 , the second carrier 142 and the third carrier 143 may be (or include) copper, aluminum, gold, silver, tin, platinum, alloys thereof, and the like. The first carrier 141 and the first conductive layer 1401 may be of the same or different materials. The third carrier 143 and the third conductive layer 1403 may be the same or different materials.

The package structure 1500 further includes a first dielectric layer 1510 and a second dielectric layer 1520, a first sub-isolator 1111, a second sub-isolator 1112 (not shown in FIG. 15), a first power circuit 1120, a second power circuit Circuit 1130 (not shown in FIG. 15 ), bootstrap capacitor CB, and decoupling capacitor CD are held together in first dielectric layer 1510 .

The wire layer 1521 is located on the first dielectric layer 1510 and passes through the second dielectric layer 1520 . In some embodiments, the first dielectric layer 1510 is formed by a molding process of the first dielectric, thereby fixing the first sub-isolator 1111 , the second sub-isolator 1112 , and the first power circuit 1120 and a second power circuit 1130.

The wire layer 1521 is used for electrically coupling the first sub-isolator 1111 , the second sub-isolator 1112 , the first power circuit 1120 and the second power circuit 1130 . In some embodiments, the material of the wire layer 1521 is metal, and is fabricated by laser drilling and metal plating processes. A detailed manufacturing method will be described in detail below.

As shown in FIG. 15 , the bootstrap capacitor CB includes a first conductive unit 1522 , a first dielectric unit 1523 and a second conductive unit 1524 . The first conductive unit 1522 and the second conductive unit 1524 may be copper pillars. The first conductive unit 1522 is located in the first dielectric layer 1510 . Likewise, the decoupling capacitor CD includes a third conductive unit 1525 , a second dielectric unit 1526 and a fourth conductive unit 1527 . The first conductive unit 1522, the second conductive unit 1524, the third conductive unit 1525, and the fourth conductive unit 1527 may be copper pillars. The third conductive unit 1525 is located in the first dielectric layer 1510 .

As shown in FIG. 15 , the first dielectric unit 1523 and the second conductive unit 1524 are located on the first conductive unit 1522 , and the second dielectric unit 1526 and the fourth conductive unit 1527 are located on the third conductive unit 1525 . The first conductive unit 1522, the first dielectric unit 1523 and the second conductive unit 1524 form a bootstrap capacitor CB, and the third conductive unit 1525, the second dielectric unit 1526 and the fourth conductive unit 1527 form a decoupling capacitor CD.

In order to adjust the capacitance value of the bootstrap capacitor CB, the material of the first dielectric unit 1523 may be different from the material of the first dielectric layer 1510 and the material of the second dielectric layer 1520 . For example, the first dielectric unit 1523 can be ceramic or mica, wherein the material of the first dielectric unit 1523 is different from the material of the first dielectric. In some other embodiments, the bootstrap capacitor CB does not include the first dielectric unit 1523 . The first conductive unit 1522 and the second conductive unit 1524 are separated by a first distance, and the first dielectric of the first dielectric layer 1510 can fill the space between the first conductive unit 1522 and the second conductive unit 1524 . In other words, the material of the first dielectric unit 1523 may be the same as the material of the first dielectric layer 1510 .

In order to adjust the capacitance value of the decoupling capacitor CD, the material of the second dielectric unit 1526 may be different from the material of the first dielectric layer 1510 and the material of the second dielectric layer 1520 . For example, the material of the second dielectric unit 1526 may be ceramic or mica, wherein the material of the second dielectric unit 1526 is different from the material of the first dielectric. In all other embodiments, the decoupling capacitor CD does not include the second dielectric unit 1525 . The third conductive unit 1525 and the fourth conductive unit 1527 are separated by a second distance, and the first dielectric of the first dielectric layer 1510 can fill the space between the third conductive unit 1525 and the fourth conductive unit 1527 . In other words, the material of the second dielectric unit 1526 may be the same as the material of the first dielectric layer 1510 .

According to some embodiments of the present invention, the first distance of the bootstrap capacitor CB is the same as or different from the second distance of the decoupling capacitor CD.

As shown in FIG. 15 , in some embodiments, the first conductive unit 1522 and the first dielectric unit 1523 are located in the first dielectric layer 1510 , and the second conductive unit 1524 is located in the second dielectric layer 1520 . The second conductive unit 1524 and the wire layer 1521 are fixed by the second dielectric layer 1520 , and the second conductive unit 1524 is electrically coupled to the first power circuit 1120 through the wire layer 1521 . However, in other embodiments, according to different manufacturing methods, the first conductive unit 1522 , the first dielectric unit 1523 and the second conductive unit 1524 may all be located in the first dielectric layer 1510 and pass through the first dielectric layer The first dielectric of 1510 is fixed. The second conductive unit 1524 is electrically coupled to the first power circuit 1120 through the wire layer 1521 . A detailed manufacturing method will be described in detail below.

As shown in FIG. 15 , in some embodiments, the third conductive unit 1525 and the second dielectric unit 1526 are both located in the first dielectric layer 1510 , and the fourth conductive unit 1527 is located in the second dielectric layer 1520 . The fourth conductive unit 1527 and the wire layer 1521 are fixed by the second dielectric layer 1520 , and the fourth conductive unit 1527 is electrically coupled to the first power circuit 1120 by the wire layer 1521 . However, in other embodiments, according to different manufacturing methods, the third conductive unit 1525 , the second dielectric unit 1526 and the fourth conductive unit 1527 can all be located in the first dielectric layer 1510 and pass through the first dielectric The first dielectric of layer 1510 is fixed. The fourth conductive unit 1527 is electrically coupled to the first power circuit 1120 through the wire layer 1521 . A detailed manufacturing method will be described in detail below.

16A-16B show a top view and a cross-sectional view of a first power circuit according to an embodiment of the present invention. FIG. 16A shows a top view of the first power circuit 1120 . As shown in FIG. 16A , the source terminal S1 , the gate terminal G1 and the drain terminal D1 of the first power transistor 1122 are as shown in the figure. The first driving circuit 1121 is located below the source terminal S1 and the gate terminal G1 of the first power transistor 1122 .

FIG. 16B shows a cross-sectional view of the first power circuit 1120 . As shown in FIG. 16B , the first power transistor 1122 is located below the first driving circuit 1121 and the drain terminal D1 of the first power transistor 1122 .

Referring to FIG. 14 and FIG. 15 , the first conductor 1411 of FIG. 14 may be a copper pillar. The first conductor 1411 is located above the first carrier 141 and is coupled to one end (ie, the bottom surface) of the bootstrap capacitor CB through the first conductive layer 1401 , and the wire layer 1521 of FIG. 15 is electrically coupled to the bootstrap capacitor CB the other end (ie, the top surface). In other words, the source terminal S1 (ie, the fifth reference node NR5 ) of the first power transistor 1122 is electrically coupled to the first conductive layer 1401 through the wire layer 1521 and the first conductor 1411 .

The second conductor 1412 of FIG. 14 may be a copper pillar. The second conductor 1412 is located above the second carrier 142 and is electrically coupled to one end (ie, the bottom surface) of the decoupling capacitor CD through the second conductive layer 1402 . The wire layer 1521 of FIG. 15 is electrically coupled to the other end (ie, the top surface) of the decoupling capacitor CD. In other words, the source terminal S2 (ie, the sixth reference node NR6 ) of the second power transistor 1132 is electrically coupled to the second conductive layer 1402 through the wire layer 1521 and the second conductor 1412 .

FIGS. 17A-17F show a manufacturing flow chart of the package structure 1400 of FIG. 14 and the package structure 1500 of FIG. 15 according to an embodiment of the present invention. As shown in FIG. 17A, the first conductive unit 1522, the third conductive unit 1525, the first sub-isolator 1111, the second sub-isolator 1112, the first power circuit 1120, the second power circuit 1130, the first conductor 1411, and the first The two conductors 1412 are located on the substrate 14 .

In some embodiments, the first conductive unit 1522 of the bootstrap capacitor CB is formed on the first carrier 141 , and the first conductive layer 1401 is located between the first conductive unit 1522 and the first carrier 141 . The first power circuit 1120 and the second power circuit 1130 are located on the first carrier 141 . The decoupling capacitor CD is formed on the second carrier 142 , and the second conductive layer 1402 is located between the decoupling capacitor CD and the second carrier 142 . The first sub-isolator 1111 and the second sub-isolator 1112 are located on the third carrier 143 , and the third conductive layer 1403 is located between the first sub-isolator 1111 and the second sub-isolator 1112 and the third carrier 143 .

As shown in FIG. 17A , the first dielectric unit 1523 and the second dielectric unit 1526 are respectively formed on the first conductive unit 1522 and the third conductive unit 1525 .

As shown in FIG. 17B, the first conductive unit 1522, the first dielectric unit 1523, the third conductive unit 1525, the second dielectric unit 1526, the first sub-isolator 1111, the second sub-isolator 1112, the first power circuit 1120 and the second power circuit 1130 are fixed together by a first dielectric, and a first dielectric layer 1510 is formed. In some embodiments, the material of the first dielectric may be epoxy resin (Epoxy) or BT resin (Bismaleimide Triazine Resin).

As shown in FIG. 17C to FIG. 17E , the first fixing layer 1520a located above the first dielectric layer 1510 is formed by an encapsulation process. Next, a plurality of first metal units 1521a are formed by laser drilling and metal plating processes. In some embodiments, as shown in FIG. 17C and FIG. 17D , after the first fixed layer 1520a is formed by an encapsulation process, the first fixed layer 1520a is etched to generate first conductors corresponding to the first first dielectric units 1522 . 1411 , the second conductor 1412 and a plurality of holes H at all terminals of the first sub-isolator 1111 , the second sub-isolator 1112 , the first power circuit 1120 and the second power circuit 1130 . Next, as shown in FIG. 17E , a first metal unit 1521 a is formed on the first dielectric layer 1510 through the laser drilling and the first fixing layer 1520 a processed by the metal plating process. In some embodiments, one of the first metal units 1521a becomes the second conductive unit 1524 and one of the first metal units 1521a becomes the fourth conductive unit 1527 . The first fixing layer 1520a on the first dielectric layer 1510 is used for fixing the second conductive unit 1524, the fourth conductive unit 1527 and the first metal unit 1521a.

Referring to FIG. 17F , after the first pinned layer 1520a travels, a second pinned layer 1520b and a plurality of second metal units 1521b are formed on the first pinned layer 1520a. The first metal unit 1521a and the second metal unit 1521b form the wire layer 1521, so that the first sub-isolator 1111, the second sub-isolator 1112, the first power single circuit 1120, the second power circuit 1130, the bootstrap capacitor CB and the solution The coupling capacitors CD are electrically coupled as shown in FIG. 13 .

In the manufacturing method provided herein, the bootstrap capacitor CB and the decoupling capacitor CD packaged in the same package structure can be directly placed on the substrate 14 . That is, the first conductive unit 1522, the first dielectric unit 1523 and the second conductive unit 1524 are first formed as the bootstrap capacitor CB, and the third conductive unit 1525, the second dielectric unit 1526 and the fourth conductive unit 1527 are first formed as Decoupling capacitor CD. Next, the bootstrap capacitor CB and the decoupling capacitor CD are placed on the substrate 14 .

According to other embodiments of the present invention, the first conductive unit 1522 , the first dielectric unit 1523 , the third conductive unit 1525 and the second dielectric unit 1526 are packaged together first, and then placed on the substrate 14 . Next, after forming the first dielectric layer 1510 and covering the first conductive unit 1522 , the first dielectric unit 1523 , the third conductive unit 1525 and the second dielectric unit 1526 , the second conductive unit 1524 and the fourth conductive unit 1527 is formed over the first dielectric layer 1510.

In the embodiment shown in FIGS. 17A to 17F , the second conductive unit 1524 is formed on the first dielectric unit 1523 and on the second dielectric layer 1520 , and the fourth conductive unit 1527 is formed on the second dielectric layer 1520 . Above cell 1526 and above second dielectric layer 1520 . In some embodiments of other manufacturing methods, after the first dielectric unit 1523 and the second dielectric unit 1526 are formed on the first conductive unit 1522 and the third conductive unit 1525, respectively, the second conductive unit 1522 is formed on the On the first dielectric unit 1523, and a fourth conductive unit 1527 is formed on the second dielectric unit 1526.

Next, the first conductive unit 1522 , the first dielectric unit 1523 , the second conductive unit 1524 , the third conductive unit 1525 , the second dielectric unit 1526 and the fourth conductive unit 1527 are fixed by using the first dielectric material. That is, the first conductive unit 1522 , the first dielectric unit 1523 , the second conductive unit 1524 , the third conductive unit 1525 , the second dielectric unit 1526 and the fourth conductive unit 1527 are all located in the first dielectric layer 1510 .

In some embodiments, after the first conductive unit 1522 and the third conductive unit 1526 are formed on the substrate 14 , the first dielectric material fixes the first conductive unit 1522 , the third conductive unit 1526 , and the first sub-isolator 1111 , the second sub-isolator 1112 , the first power circuit 1120 and the second power circuit 1130 . In this embodiment, the first dielectric is used as the material of the first dielectric unit 1523 and/or the second dielectric unit 1526 .

After the first dielectric layer 1510 is formed, the second conductive unit 1524 is located on the first dielectric layer 1510 , and the fourth conductive unit 1527 is located on the first dielectric layer 1510 . The first conductive unit 1522 and the second conductive unit 1524 are separated by a first distance, and the third conductive unit 1525 and the fourth conductive unit 1527 are separated by a second distance, wherein the first distance and the second distance are the same or different.

Therefore, the first conductive unit 1522, the second conductive unit 1524 and the first dielectric between the first conductive unit 1522 and the second conductive unit 1524 form a bootstrap capacitor CB, the third conductive unit 1525, the fourth conductive unit 1525 The unit 1527 and the first dielectric between the third conductive unit 1525 and the fourth conductive unit 1527 form a decoupling capacitor CD.

According to some embodiments of the present invention, after the metal unit 1521a is formed using the laser drilling and metal plating process, the second dielectric layer 1520 is formed again, and a plurality of holes are formed again. Next, the metal unit 1522b is formed by laser drilling and metal plating processes. Therefore, the first sub-isolator 1111 , the second sub-isolator 1112 , the first power circuit 1120 , the second power circuit 1130 , the bootstrap capacitor CB and the decoupling capacitor CD are thus electrically coupled together.

The foregoing are general features of the embodiments. Those skilled in the art will readily be able to utilize the present invention as a basis for designing or adapting to carry out the same purposes and/or achieve the same advantages of the embodiments presented herein. Those skilled in the art should also understand that the same configuration can make various changes, substitutions and alternations without departing from the spirit and scope of the present invention. The illustrative methods represent exemplary steps only, and the steps do not necessarily have to be performed in the order presented. Additional steps may be added, substituted, changed order, and/or eliminated to adjust as appropriate and consistent with the spirit and scope of the disclosed embodiments.

Claims (29)

1. A package structure for an integrated circuit, comprising:

the substrate comprises at least a first carrier and a second carrier, wherein the first carrier and the second carrier are isolated from each other;

a decoupling capacitor located on the second carrier;

an integrated circuit fixed in a first dielectric layer together with the decoupling capacitor, the integrated circuit being located on a first carrier;

a bootstrap capacitor on the substrate, wherein the integrated circuit and the bootstrap capacitor are fixed in the first dielectric layer on the first carrier; and

a conductive layer for electrically coupling the decoupling capacitor to the integrated circuit, wherein the conductive layer is disposed on the first dielectric layer and penetrates a second dielectric layer.

2. The package structure of claim 1, wherein the decoupling capacitor comprises:

a first conductive unit formed in the first dielectric layer;

a first dielectric element formed on the first conductive element; and

a second conductive element formed on the first dielectric element.

3. The package structure of claim 2, wherein the bootstrap capacitor comprises:

a third conductive unit formed in the first dielectric layer;

a second dielectric unit formed on the first conductive unit; and

a fourth conductive element formed on the second dielectric element.

4. The package structure of claim 3, wherein the material of the first dielectric element and the second dielectric element is different from the material of the first dielectric layer and the material of the second dielectric layer.

5. The package structure of claim 1, wherein said integrated circuit comprises:

an isolator for providing a first control signal and a second control signal according to an input signal;

a first power circuit comprising:

a first driving circuit powered by a second supply voltage and a switching voltage and generating a first driving voltage at a first driving node according to the first control signal, wherein a bootstrap diode and the bootstrap capacitor are used to boost a first supply voltage to the second supply voltage, wherein the bootstrap diode includes a bootstrap anode coupled to the first supply voltage and a bootstrap cathode coupled to the second supply voltage, and wherein the bootstrap capacitor is coupled between the second supply voltage and the switching voltage at a switching node; and

a first power transistor for supplying a high voltage to the switching node according to the first driving voltage; and

a second power circuit, comprising:

a second driving circuit, powered by the first supply voltage and a first ground terminal, for generating a second driving voltage at a second driving node according to the second control signal; and

a second power transistor, pulling down the switch voltage to the first ground terminal according to the second driving voltage.

6. The package structure of claim 5, wherein each of the first power transistor and the second power transistor is a GaN transistor.

7. The package structure of claim 5, wherein the isolator comprises:

a first sub-isolator comprising:

a first transmitter powered by a third supply voltage and a second ground and capable of transmitting a first RF signal according to the input signal;

a first receiver powered by a second supply voltage and the switching voltage and generating the first control signal according to the first RF signal; and

a first isolation barrier for electrically isolating the first transmitter from the first receiver; and

a second sub-isolator comprising:

a second transmitter, powered by a third supply voltage and a second ground terminal, for transmitting a second radio frequency signal according to the input signal;

a second receiver powered by the first supply voltage and the first ground and capable of generating the second control signal according to the second RF signal; and

a second isolation barrier for electrically isolating the second transmitter from the second receiver.

8. The package structure of claim 5, wherein said isolator comprises:

a transmitter, powered by a third supply voltage and a second ground terminal, for transmitting a first RF signal and a second RF signal according to the input signal;

a first receiver powered by the second supply voltage and the switching voltage and generating the first control signal according to the first RF signal;

a first isolation barrier for electrically isolating the transmitter from the first receiver;

a second receiver powered by the first supply voltage and the first ground and capable of generating the second control signal according to the first RF signal; and

a second isolation barrier for electrically isolating the transmitter from the second receiver.

9. The package structure of claim 5, wherein the decoupling capacitor is coupled between the high voltage and the first ground.

10. The package structure of claim 5, wherein each of the first power circuit and the second power circuit comprises:

the pre-driver circuit generates a first internal signal according to a control signal, wherein the pre-driver circuit is used for improving the driving capability of the control signal, and a driver circuit generates a driving voltage according to the first internal signal.

11. The package structure of claim 10, wherein each of the first power circuit and the second power circuit comprises:

an upper bridge transistor for providing a supply voltage to a driving node according to an upper bridge voltage of an upper bridge node;

a lower bridge transistor for coupling the driving node to a ground terminal according to the first internal signal; and

a charge pump coupled to the upper bridge node and the driving node for generating the upper bridge voltage exceeding the supply voltage according to the first internal signal.

12. The package structure of claim 11 wherein the top bridge transistor and the bottom bridge transistor are both normally-off transistors.

13. A method of manufacturing a package structure for an integrated circuit, comprising:

providing a decoupling capacitor on a substrate, wherein the substrate comprises at least a first carrier and a second carrier, the first carrier and the second carrier are isolated from each other, and the decoupling capacitor is positioned on the second carrier;

providing an integrated circuit on the substrate, wherein the integrated circuit is positioned on the first carrier;

providing a bootstrap capacitor on the first carrier; and

fixing the bootstrap capacitor, the decoupling capacitor and the integrated circuit through a first dielectric substance to form a first dielectric layer;

forming a conductive line layer on the first dielectric layer to electrically couple the decoupling capacitor to the integrated circuit through the conductive line layer; and

the conductive layer and the first dielectric layer are fixed by a second dielectric substance, and a second dielectric layer is formed and placed on the first dielectric layer.

14. The method of claim 13, wherein the step of providing a decoupling capacitor on a substrate further comprises:

forming a first conductive unit in the first dielectric layer;

forming a first dielectric unit on the first conductive unit; and

a second conductive element is formed over the first dielectric element.

15. The method of claim 13, wherein the step of providing a bootstrap capacitor on the first carrier further comprises:

forming a third conductive unit in the first dielectric layer;

forming a second dielectric unit on the third conductive unit; and

forming a fourth conductive unit on the second dielectric unit.

16. The method of manufacturing of claim 13, wherein said integrated circuit comprises:

an isolator including a first supply node, a second supply node, a third supply node, a fourth supply node, a first reference node, a second reference node, a third reference node, a fourth reference node, a first input node, a second input node, a first output node, and a second output node;

a first power circuit including a fifth supply node coupled to the second supply node, a sixth supply node, a fifth reference node coupled to the second reference node, and a first PWM node coupled to the first output node; and

a second power circuit includes a seventh supply node coupled to the fourth supply node, an eighth reference node coupled to the fifth reference node, a sixth reference node, and a second PWM node coupled to the second output node.

17. The manufacturing method of claim 16, further comprising:

forming a first conductive layer on the substrate, wherein the first power circuit and the bootstrap capacitor are disposed on the first conductive layer, wherein the first conductive layer is coupled to a first terminal of the bootstrap capacitor and the fifth reference node, a second terminal of the bootstrap capacitor is coupled to the fifth supply node through the conductive line layer, and the sixth supply node is coupled to a third terminal of the decoupling capacitor through the conductive line layer.

18. The manufacturing method of claim 17, further comprising:

forming a second conductive layer on the substrate, wherein the second power circuit and the decoupling capacitor are disposed on the second conductive layer, and wherein the second conductive layer is coupled to a fourth terminal of the decoupling capacitor and a sixth reference node.

19. The manufacturing method of claim 18, further comprising:

forming a third conductive layer on the substrate, wherein the isolator is located on the third conductive layer.

20. The method of claim 19, wherein the first supply node and the third supply node are powered by a third supply voltage, the second supply node and the fifth supply node are powered by a second supply voltage, the first input node receives an input signal, the second input node receives an inverted input signal, the first output node generates a first control signal, the second output node generates a second control signal, the fourth supply node and the seventh supply node are powered by a first supply voltage, the sixth supply node is powered by a high voltage, the first reference node and the third reference node are coupled to a second ground, the fourth reference node and the sixth reference node are coupled to a first ground, wherein the input signal and the inverted input signal are inverted.

21. The method of manufacturing of claim 20, wherein said first power circuit comprises:

a first driving circuit powered by the second supply voltage and a switching voltage and generating a first driving voltage at a first driving node according to the first control signal; and

a first power transistor couples the sixth supply node to the fifth reference node according to the first driving voltage.

22. The method of manufacturing of claim 21, wherein said second power circuit comprises:

a second driving circuit, powered by the first supply voltage and a first ground terminal, for generating a second driving voltage at a second driving node according to the second control signal; and

a second power transistor, coupling an eighth supply node to the first ground terminal according to the second driving voltage.

23. The method of claim 22, wherein either of the first power transistor and the second power transistor is a gan transistor.

24. The method of manufacturing of claim 22, wherein said integrated circuit further comprises:

the bootstrap diode includes a bootstrap anode terminal and a bootstrap cathode terminal, wherein the bootstrap anode terminal is coupled to a first supply voltage, and the bootstrap cathode terminal is coupled to a second supply voltage.

25. The method of claim 22, wherein the high voltage exceeds the first supply voltage and the second supply voltage.

26. The method of manufacturing of claim 22, wherein said isolator comprises:

a first sub-isolator comprising:

a first transmitter powered by a third supply voltage and a second ground terminal and transmitting a first RF signal according to the input signal;

a first receiver powered by a second supply voltage and the switching voltage and generating the first control signal according to the first RF signal; and

a first isolation barrier for electrically isolating the first transmitter from the first receiver; and

a second sub-isolator comprising:

a second transmitter, powered by a third supply voltage and a second ground terminal, for transmitting a second radio frequency signal according to the input signal;

a second receiver powered by the first supply voltage and the first ground, the second receiver generating the second control signal according to the second RF signal; and

a second isolation barrier for electrically isolating the second transmitter from the second receiver.

27. The method of manufacturing of claim 22, wherein each of the first power circuit and the second power circuit comprises:

the pre-driver circuit generates a first internal signal according to a control signal, wherein the pre-driver circuit is used for improving the driving capability of the control signal, and a driver circuit generates a driving voltage according to the first internal signal.

28. The method of manufacturing of claim 27, wherein each of the first power circuit and the second power circuit comprises:

an upper bridge transistor for providing a supply voltage to a driving node according to an upper bridge voltage of an upper bridge node;

a lower bridge transistor coupling the driving node to a ground terminal according to the first internal signal; and

a charge pump coupled to the upper bridge node and the driving node, wherein the charge pump is configured to generate the upper bridge voltage exceeding the supply voltage according to the first internal signal.

29. The method of manufacturing of claim 28, wherein each of the first power circuit and the second power circuit comprises:

a hysteresis circuit coupled between the control signal and the pre-driver circuit, wherein the hysteresis circuit receives the control signal to generate a second internal signal, such that the pre-driver circuit generates the first internal signal according to the second internal signal, and the hysteresis circuit is configured to provide a hysteresis function to the control signal.

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