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CN111508919A - 半导体装置及半导体装置的制作方法 - Google Patents

半导体装置及半导体装置的制作方法 Download PDF

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Publication number
CN111508919A
CN111508919A CN201910096745.5A CN201910096745A CN111508919A CN 111508919 A CN111508919 A CN 111508919A CN 201910096745 A CN201910096745 A CN 201910096745A CN 111508919 A CN111508919 A CN 111508919A
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China
Prior art keywords
layer
opening
stress buffer
semiconductor device
buffer layer
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CN201910096745.5A
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English (en)
Inventor
林裕杰
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United Microelectronics Corp
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United Microelectronics Corp
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Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to CN201910096745.5A priority Critical patent/CN111508919A/zh
Priority to US16/294,906 priority patent/US10903179B2/en
Publication of CN111508919A publication Critical patent/CN111508919A/zh
Priority to US17/123,132 priority patent/US11476212B2/en
Pending legal-status Critical Current

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Abstract

本发明公开一种半导体装置及半导体装置的制作方法，该半导体装置包括：具有金属垫的半导体基材、第一保护层、第二保护层、凸块下金属层、应力缓冲层、铜柱及焊料结构。第一保护层形成于半导体基材上且覆盖部分金属垫，第一保护层具有第一保护层开口，以显露部分金属垫；第二保护层形成于第一保护层上，第二保护层具有第二保护层开口，以显露部分金属垫；凸块下金属层形成于经第二保护层开口显露的部分金属垫；应力缓冲层形成于凸块下金属层上；铜柱设置于应力缓冲层上。此半导体装置可防止分层缺陷及裂缝问题的产生。

Description

半导体装置及半导体装置的制作方法
技术领域
本发明涉及一种半导体技术，尤其涉及一种具有铜柱结构的半导体装置及半导体装置的制作方法。
背景技术
集成电路是由数百万的主动装置所组成，这些装置起初为彼此相互隔离，之后再借由内连线以形成功能电路。在倒装封装技术中，为获得精细间距，常使用铜柱凸块结构作为内连线与封装体表面或其他管芯连接的连接结构，其中内连线接点上设置有金属垫。传统铜柱凸块结构主要包含有凸块下金属层、铜柱与铜柱上方的焊帽。
其中，铜柱虽具有良好的导电性、导热性以及优异的抗电迁移性，但是铜柱的杨氏模量和热膨胀系数较高，当铜柱应用在倒装封装技术时，在封装过程时容易产生较大的热机械应力。又铜柱通常为设置在凸块下金属层上，目前的凸块下金属层不足以显着降低热机械应力，因此具有铜柱的半导体封装元件因电镀铜的线路与聚合物介电层(PolymerDielectric layer)间的黏着度不好，易造成聚合物介电层与线路分层(delamination)的缺陷。此分层缺陷不仅造成产品在长期可靠度测试中失败，在可靠度温度循环测试(Thermal Cycling Test,TCT)过程中，因材料间的热膨胀系数的差异，导致裂缝(Crack)现象的产生于线路与聚合物介电层之间，而影响产品功能及寿命。
发明内容
本发明提供了一种半导体装置及半导体装置的制作方法，解决半导体装置容易产生的分层缺陷及裂缝的问题。
本发明所提供的半导体装置，包括：半导体基材、第一保护层、第二保护层、凸块下金属层、应力缓冲层、铜柱及焊料结构。半导体基材具有金属垫；第一保护层形成于半导体基材上且覆盖部分金属垫，第一保护层具有第一保护层开口，以显露部分金属垫；第二保护层形成于第一保护层上，第二保护层具有第二保护层开口，以显露部分金属垫；凸块下金属层至少形成于经第二保护层开口显露的部分金属垫；应力缓冲层形成于凸块下金属层上；铜柱设置于应力缓冲层上。
在本发明的一实施例中，上述应力缓冲层的材料选自锡、锡银、锡合金、铟及铟合金其中之一。上述凸块下金属层的材料选自钛、钛钨及铜其中之一。
在本发明的一实施例中，上述半导体装置还包含一焊料结构，设置于所述铜柱上。
在本发明的一实施例中，上述半导体装置还包含阻障层，设置于铜柱与应力缓冲层之间。
在本发明的一实施例中，上述阻障层的材料为镍、钛或钽。
在本发明的一实施例中，上述应力缓冲层的表面不高于第二保护层的表面。
在本发明的一实施例中，上述铜柱的横截面积大于或等于应力缓冲层的横截面积。
在本发明的一实施例中，上述第一保护层开口的面积大于第二保护层开口的面积，且铜柱的横截面积大于第一保护层开口及第二保护层开口的面积。
在本发明的一实施例中，上述第一保护层开口小于第二保护层开口的面积，且凸块下金属层直接接触第一保护层及第二保护层。
在本发明的一实施例中，上述凸块下金属层更形成于第二保护层开口的内壁及第二保护层开口周缘的部分第二保护层上。
在本发明的一实施例中，上述铜柱更覆盖第二保护层开口周缘的部分第二保护层。
本发明所提供的半导体装置的制作方法包括：提供半导体基材，半导体基材具有金属垫；形成第一保护层于半导体基材上且覆盖部分金属垫，第一保护层具有第一保护层开口，以显露部分金属垫；形成第二保护层于第一保护层上，第二保护层具有第二保护层开口，以显露部分金属垫；形成凸块下金属层于显露的部分金属垫、第二保护层开口的内壁及部分第二保护层上；形成应力缓冲层于金属垫上方的部分凸块下金属层上；形成铜柱于应力缓冲层上，以覆盖应力缓冲层及部分凸块下金属层；以及形成焊料结构于铜柱上。
在本发明的一实施例中，在形成上述铜柱之前，更先形成阻障层于应力缓冲层上，使得阻障层位于应力缓冲层及铜柱之间，阻障层的材料为镍、钛或钽。
在本发明的一实施例中，上述应力缓冲层、铜柱及焊料结构的形成包含以下步骤：形成第一光致抗蚀剂层于凸块下金属层上，并形成第一开口于第一光致抗蚀剂层，以经由第一开口显露部分凸块下金属层；电镀应力缓冲层于第一开口显露的部分凸块下金属层上；电镀铜柱于第一开口显露的应力缓冲层上；电镀焊料结构于铜柱上；以及移除第一光致抗蚀剂层。
在本发明的一实施例中，上述铜柱还覆盖应力缓冲层周边的部分凸块下金属层。
在本发明的一实施例中，在移除上述第一光致抗蚀剂层之后或者同时，并移除未被铜柱覆盖的部分凸块下金属层。
在本发明的一实施例中，上述应力缓冲层、铜柱及焊料结构的形成包含以下步骤：形成第一光致抗蚀剂层于凸块下金属层上，并形成第一开口于第一光致抗蚀剂层中，以经由第一开口显露部分凸块下金属层；电镀应力缓冲层于第一开口显露的部分凸块下金属层上；移除第一光致抗蚀剂层；形成第二光致抗蚀剂层于凸块下金属层上，并形成第二开口于第二光致抗蚀剂层中，第二开口大于第一开口，以经由第二开口显露应力缓冲层及凸块下金属层；电镀铜柱于第二开口显露的应力缓冲层及部分凸块下金属层上；电镀焊料结构于铜柱上；以及移除第一光致抗蚀剂层及第二光致抗蚀剂层。
在本发明的一实施例中，在移除上述第二光致抗蚀剂层之后或者同时，并移除未被铜柱覆盖的部分凸块下金属层。
本发明因在铜柱及凸块下金属层之间设置应力缓冲层，因此可避免铜柱因杨氏模量和热膨胀系数较高而容易在封装过程时产生较大的热机械应力而造成半导体基材内部产生分层缺陷的问题，更可减少材料间因热膨胀系数的差异，所导致的裂缝产生问题。
上述说明仅是本发明技术方案的概述，为了能够更清楚了解本发明的技术手段，而可依照说明书的内容予以实施，并且为了让本发明的上述和其他目的、特征和优点能够更明显易懂，以下特举优选实施例，并配合附图,详细说明如下。
附图说明
图1是本发明一第一实施例半导体装置的结构示意图；
图2是本发明一第二实施例半导体装置的结构示意图；
图3是本发明一第三实施例半导体装置的结构示意图；
图4是本发明一第四实施例半导体装置的结构示意图；
图5是本发明一实施例半导体装置与另一电性元件电连接示意图；
图5A是本发明一实施例半导体装置应用于扇出型封装的部分结构示意图；
图6A至图6L是发明一实施例半导体装置的制作方法的流程示意图；
图7A至图7I是本发明又一实施例半导体装置的制作方法的流程示意图；
图8A至图8G是本发明又一实施例半导体装置的制作方法的流程示意图。
具体实施方式
图1是本发明一第一实施例半导体装置的结构示意图，如图所示，半导体装置10包含：半导体基材12、第一保护层(Passivation Layer，PASV)14、第二保护层(Re-passivation layer，Re-PASV)16、凸块下金属层(Under bump metal，UBM)18、应力缓冲层20、铜柱(copper pillar)22及焊料(solder)结构24。
半导体基材12上具有金属垫26。半导体基材12可以是硅晶片或含硅的材料层，且集成电路可形成于其中或其上。半导体基材12的各个层状结构及特征结构，包括晶体管、内连线层状结构、保护后内连线结构、重新分配层以及类似的结构等受到省略而未显示于图式中。在一实施例中，金属垫26例如位于芯片或者晶片的主动(有源)表面，且金属垫26例如为铝垫；在另一实施例中，因应半导体基材10上的不同接点位置，可设置重新分配层，金属垫26例如位于重新分配层上，且金属垫26例如为铜垫。
第一保护层14形成于半导体基材10上且覆盖部分金属垫26，第一保护层14定义有第一保护层开口141，以经由第一保护层开口141露出部分的金属垫26，例如第一保护层14覆盖半导体基材10及金属垫26的外缘而经第一保护层开口141露出金属垫26的中间部分。在一实施例中，第一保护层14例如由非掺杂硅玻璃(USG)、氮化硅、氮氧化硅、氧化硅等非有机材料组成；抑或由环氧化物、苯环丁烯(BCB)、聚苯恶唑(PBO)等聚合物所构成。
第二保护层16形成于第一保护层14上且覆盖部分金属垫26，第二保护层16定义有第二保护层开口161，第二保护层开口161可小于、等于或大于第一开口；在图1所示的第一实施例中，第二保护层开口161小于第一保护层开口141，第二保护层16并覆盖经第一保护层开口141所露出金属垫26的外缘，使金属垫26的显露部分缩小。在一实施例中，第二保护层16例如由聚亚酰胺或其它性质柔软的聚合物所形成。
凸块下金属层18形成于经第二保护层开口161显露的部分金属垫26、第二保护层开口161的内壁及第二保护层开口161周缘的部分第二保护层16上。在一实施例中，凸块下金属层18略呈凹形，具有底部181、侧部182及上缘部183，其中底部181位于金属垫26显露的部分，侧部182位于第二保护层开口161的内壁，上缘部183位于第二保护层开口161周缘的部分第二保护层16。在一实施例中，凸块下金属层18例如由钛、钛钨、铜或类似的材料所组成。
应力缓冲层20形成于凸块下金属层18上。具体来说，应力缓冲层20形成于凸块下金属层18的底部181及侧部182；在一实施例中，应力缓冲层20的高度介于5微米至7.5微米之间，应力缓冲层20的高度不高于第二保护层16的表面。又应力缓冲层20的材料选自锡、锡银、锡合金、铟及铟合金其中之一。
铜柱22设置于应力缓冲层20上，铜柱22例如呈圆柱状，铜柱22的横截面积可大于或等于应力缓冲层20的横截面积。在如图1所示的第一实施例中，铜柱22的横截面积大于应力缓冲层20的最大横截面积，且铜柱22除了覆盖应力缓冲层20之外，更覆盖凸块下金属层18的上缘部183。又铜柱22的高度介于20微米至30微米之间。
焊料结构24设置于铜柱22上，在一实施例中，焊料结构24可以是球状、半球状、凸块或类似的结构；焊料结构24的材料选自锡、锡银及锡合金其中之一。
图2是本发明一第二实施例半导体装置的结构示意图，如图2所示，第二实施例半导体装置10A与第一实施例半导体装置10的差异在于半导体装置10A还包含阻障层26设置于铜柱22及应力缓冲层20之间，阻障层26的材料例如是镍、钛或钽。借由阻障层26的设置可以减少回焊过程和设备操作过程中应力缓冲层20的损耗，以延长半导体装置10A的使用寿命。
图3是本发明一第三实施例半导体装置的结构示意图，如图3所示，第三实施例半导体装置10B包含半导体基材12、第一保护层14、第二保护层16B、凸块下金属层18B、应力缓冲层20B、铜柱22及焊料结构24。半导体装置10B与半导体装置10的差异在于第二保护层16B、凸块下金属层18B及应力缓冲层20B的结构。如图3所示，在半导体装置10B中，第二保护层16B形成于第一保护层14上，第二保护层16B定义有第二保护层开口161B，第二保护层开口161B大于第一保护层开口141，亦即经由第二保护层开口161B显露金属垫26以及环绕于第一保护层开口141周边的第一保护层14的表面142。
接续上述说明，如图3所示，凸块下金属层18B形成于经第一保护层开口141显露的部分金属垫26、第一保护层开口141内壁、第一保护层14经第二保护层开口161B显露的部分表面142、第二保护层开口161B的内壁及第二保护层开口161B周缘的部分第二保护层16B上。在一实施例中，凸块下金属层18B略呈凹形，具有底部181B、阶梯侧部182B及上缘部183B，其中底部181B位于金属垫26显露的部分，阶梯侧部182B位于第一保护层开口141内壁、第一保护层14经第二保护层开口161B显露的部分表面142及第二保护层开口161B的部分内壁，上缘部183B位于第二保护层开口161B周缘的部分第二保护层16B上。换句话说，半导体装置10B的凸块下金属层18B的阶梯侧部182B会直接接触到第一保护层14及第二保护层16，而非如半导体装置10的凸块下金属层18仅接触到第二保护层16。
接续上述说明，如图3所示，应力缓冲层20B形成于凸块下金属层18B上。具体来说，应力缓冲层20B形成于凸块下金属层18B的底部181B及阶梯侧部182B。又与第一实施例半导体装置10相同地，在应力缓冲层20B上依序形成有铜柱22及焊料结构24，于此不再赘述。
图4是本发明一第四实施例半导体装置的结构示意图，如图4所示，第四实施例半导体装置10C与第三实施例半导体装置10B的差异在于半导体装置10C还包含阻障层26设置于铜柱22及应力缓冲层20B之间，阻障层26的材料例如是镍、钛或钽。借由阻障层26的设置可以减少回焊过程和设备操作过程中应力缓冲层20B的损耗，以延长半导体装置10C使用寿命。
图5是本发明一实施例半导体装置与另一电性元件电连接示意图，如图5所，以第一实施例所示的半导体装置10为例，半导体装置10的焊料结构24可供接触到另一电性元件30，并借由回焊将半导体装置10与电性元件30接合在一起。在一实施例中，电性元件30可为具有保护层32的印刷电路板、晶片或芯片等基材，其中保护层32具有开口321，以露出印刷电路板、晶片或芯片上的焊垫34，以便借由露出的焊垫34与半导体装置10的焊料结构24接合。在一实施例中，若电性元件30为印刷电路板，则保护层32即为印刷电路板上的阻焊层。在一实施例中，若电性元件30为晶片或芯片，则保护层32即为聚合物保护层(PASV或Re-PASV)。
图5A是本发明一实施例半导体装置应用于扇出型封装(Fan-out package)的部分结构示意图，如图5A所示，在此实施例中，模塑料50用以包覆铜柱22及半导体基材12，例如芯片，又铜柱22的一端露出模塑料50，并利用导线重新分配层52将铜柱22的露出端扇出以设置焊料结构24，焊料结构24例如为锡球。虽未图示，应了解，本发明实施例半导体装置应用于扇出型封装时，半导体基材12与铜柱22之间，如前述实施例所示，可包含保护层、凸块下金属层、应力缓冲层及阻障层等、在此不再赘述。
图6A至图6L是本发明一实施例半导体装置的制作方法的流程示意图。如图6A所示，提供半导体基材12，半导体基材12上具有金属垫26。接着，如图6B所示，形成第一保护层14于半导体基材12上且覆盖部分金属垫26，其中第一保护层14具有第一保护层开口141，以显露部分金属垫26。在一实施例中，第一保护层14覆盖金属垫26的外缘而露出金属垫26的中间部分。接着，如图6C所示，形成第二保护层16于第一保护层14上，其中第二保护层16具有第二保护层开口161。在一实施例中，第二保护层开口161小于第一保护层开口141(标示于图6B)，第二保护层16除了完全覆盖第一保护层14之外，也会覆盖经第一保护层开口141所露出金属垫26的外缘。之后，如图6D所示，形成凸块下金属层18’于显露的金属垫26、第二保护层开口161(标示图6C)的内壁及第二保护层16上。凸块下金属层18’例如以溅镀、蒸镀或电镀的方式形成，凸块下金属层18’于对应金属垫26的位置略呈凹形，具有一容置部184。
接续上述说明，如图6E所示，形成第一光致抗蚀剂层40于凸块下金属层18’上，并利用曝光、显影的成像技术于第一光致抗蚀剂层40形成第一开口401。在一实施例中，第一开口401的位置及大小对应于容置部184的位置及大小，经由第一开口401显露部分凸块下金属层18’，例如显露凸块下金属层18’与金属垫26接触的部分。接着，如图6F所示，以第一光致抗蚀剂层40为掩模，电镀应力缓冲层20于凸块下金属层18’的容置部184(标示于图6E)，应力缓冲层20的材料选自锡、锡银、锡合金、铟及铟合金其中之一。在一实施例中，应力缓冲层20的高度不超过容置部184的高度，例如应力缓冲层20的表面不高于第二保护层16的表面，在一实施例中，应力缓冲层20的高度介于5微米至7.5微米之间。之后，移除第一光致抗蚀剂层40，如图6G所示，露出未被应力缓冲层20覆盖的凸块下金属层18’。
接续上述说明，如图6H所示，形成第二光致抗蚀剂层42于凸块下金属层18’上，并利用曝光、显影的成像技术于第二光致抗蚀剂层42形成第二开口421。在一实施例中，第二开口421大于前述第一光致抗蚀剂层40的第一开口401(标示于图6E)，经由第二开口421显露应力缓冲层20及部分的凸块下金属层18’。接着，如图6I所示，以第二光致抗蚀剂层42为掩模，进行铜电镀处理，使得电镀液中铜的析出物能附着在应力缓冲层20及显露的凸块下金属层18’上，以形成如铜柱22的凸块结构，其中铜柱22同时覆盖应力缓冲层20以及应力缓冲层20周边的凸块下金属层18’。在一实施例中，电镀的铜柱22未完全填满第二光致抗蚀剂层42的第二开口421，铜柱22的高度介于20微米至30微米之间。
之后，如图6J所示，以同一第二光致抗蚀剂层为掩模，进行焊料电镀处理，以形成类似蘑菇(mushroom)状的焊料结构24’于铜柱22的表面上，其中，焊料结构24’填满第二光致抗蚀剂层42的第二开口421(标示于图6I)且突出于第二光致抗蚀剂层42上；又焊料结构24’例如为低熔点的锡、锡银或锡合金。
之后，去除第二光致抗蚀剂层42，并于去除第二光致抗蚀剂层42的同时或之后，蚀刻未被铜柱22所覆盖的凸块下金属层18’，如图6K所示，保留了铜柱22底部的凸块下金属层18’。最后，回焊焊料结构24’，如图6L所示，使焊料结构24’熔融为球体状或半球体状。
其中，在未绘示的实施例中，可于应力缓冲层20形成后，再次以第一光致抗蚀剂层40作为掩模，电镀阻障层于应力缓冲层20上，之后再移除第一光致抗蚀剂层40，并进行上述的铜柱22及焊料结构24’制程。阻障层的材料例如为镍、钛或钽。如此，使得阻障层位于应力缓冲层20及铜柱22之间。
图7A至图7I是本发明又一实施例半导体装置的制作方法的流程示意图。图7A绘示了具有金属垫26的半导体基材12上已形成有第一保护层14、第二保护层16B及凸块下金属层18B’。其中，第一保护层14覆盖金属垫26的外缘而经由第一保护层开口141露出金属垫26的中间部分；第二保护层16B形成于第一保护层14上，第二保护层开口161B大于第一保护层开口141，经由第二保护层开口161B显露金属垫26以及第一保护层开口141周边的第一保护层14的表面142；凸块下金属层18B’形成于金属垫26经第一保护层开口141显露的部分、第一保护层开口141内壁、第一保护层14经第二保护层开口161B显露的部分表面142、第二保护层开口161B的内壁及第二保护层16B上。凸块下金属层18B’于对应金属垫26的位置略呈凹形，具有容置部184B，容置部184B包含底部181B及阶梯侧部182B。
接着，如图7B所示，形成具有第一开口401的第一光致抗蚀剂层40于凸块下金属层18’上，经由第一开口401显露部分凸块下金属层18B’，例如显露容置部184B的底部181B及阶梯侧部182B。接着，如图7C所示，以第一光致抗蚀剂层40为掩模，电镀应力缓冲层20B于凸块下金属层18B’的容置部184B(标示于图7B)；应力缓冲层20的材料选自锡、锡银、锡合金、铟及铟合金其中之一；在一实施例中，应力缓冲层20B的表面不高于第二保护层16B的表面。之后，如图7D所示，移除第一光致抗蚀剂层40，露出未被应力缓冲层20B覆盖的凸块下金属层18B’。
接续上述说明，如图7E及图7F所示，形成具有第二开口421的第二光致抗蚀剂层42于凸块下金属层18B’上，第二开口421大于前述第一光致抗蚀剂层40的第一开口401，并以第二光致抗蚀剂层42为掩模，在应力缓冲层20B及显露的凸块下金属层18B’上，形成如铜柱22的凸块结构，其中铜柱22同时覆盖应力缓冲层20B以及应力缓冲层20B周边的凸块下金属层18B’。接着，如图7G至图7I所示，以同一第二光致抗蚀剂层42为掩模，形成焊料结构24’，之后移除第二光致抗蚀剂层42及未被铜柱22所覆盖的凸块下金属层18B’，且回焊焊料结构24’，使焊料结构24’熔融为球体状或半球体状接合于铜柱22上。
上述图7B至图7I所示流程与图6E至图6L所示流程大致相同，因具体或详细流程已叙述于图6E至图6L的说明中，在此不再赘述。其中，也可于应力缓冲层20B形成后，以第一光致抗蚀剂层40作为掩模，电镀阻障层于应力缓冲层20B上，之后再移除第一光致抗蚀剂层40。
在上述半导体装置的制作方法中，借由第一光致抗蚀剂层40及第二光致抗蚀剂层42两光致抗蚀剂层的使用以形成应力缓冲层20/20B、铜柱22及焊料结构24’。但是不限于此，可使用单一光致抗蚀剂层作为掩模以形成应力缓冲层20/20B、铜柱22及焊料结构24’。图8A至图8G是本发明又一实施例半导体装置的制作方法的流程示意图，图8A绘示了具有金属垫26的半导体基材12上已形成有第一保护层14、第二保护层16及凸块下金属层18’，其形成方法已绘示于图6A及图6D中，在此不再赘述。其中，凸块下金属层18’于对应金属垫26的位置略呈凹形，具有一容置部184。
图8B所示，形成第一光致抗蚀剂层40于凸块下金属层18’上，并利用曝光、显影的成像技术于第一光致抗蚀剂层40形成第一开口401。在一实施例中，第一开口401的位置对应于容置部184的位置，且第一开口401的大小可等于或略大于容置部184的大小，以经由第一开口401显露部分凸块下金属层18’，例如显露凸块下金属层18’与金属垫26接触的部分。接着，如图8C所示，以第一光致抗蚀剂层40为掩模，电镀应力缓冲层20于凸块下金属层18’上，应力缓冲层20的材料选自锡、锡银、锡合金、铟及铟合金其中之一。在一实施例中，应力缓冲层20的高度不超过容置部184(标示于8B)的高度，例如应力缓冲层20的表面不高于第二保护层16的表面。
接着，如图8D所示，继续以第一光致抗蚀剂层40作为掩模，进行铜电镀处理，使得电镀液中铜的析出物能附着在应力缓冲层20上，以形成如铜柱22的凸块结构，其中铜柱22同时覆盖应力缓冲层20以及应力缓冲层20周边的凸块下金属层18’，且铜柱22未完全填满第一光致抗蚀剂层40的第一开口401。之后，如图8E所示，以同一第一光致抗蚀剂层40为掩模，进行焊料电镀处理，以形成类似蘑菇状的焊料结构24’于铜柱22的表面上，其中，焊料结构24’填满第一光致抗蚀剂层40的第一开口401(标示图8D)且突出于第一光致抗蚀剂层40上。
接着，如图8F所示，去除第一光致抗蚀剂层40，并于去除第一光致抗蚀剂层40的同时或之后，蚀刻未被铜柱22所覆盖的凸块下金属层18’。最后，回焊焊料结构24’，如图8G所示，使焊料结构24’熔融为球体状或半球体状。
其中，在未绘示的实施例中，可于应力缓冲层20形成后且铜柱22形成前，以第一光致抗蚀剂层40作为掩模，电镀阻障层于应力缓冲层20上，以使得阻障层位于应力缓冲层20及铜柱22之间。
在本发明半导体装置中，借由应力缓冲层的设置可避免铜柱因杨氏模量和热膨胀系数较高而容易在封装过程时产生较大的热机械应力而造成半导体基材内部产生分层缺陷的问题，更可减少材料间的热膨胀系数的差异，所导致的裂缝产生问题。此外，借由应力缓冲层及铜柱之间阻障层的设置，可以减少回焊过程和设备操作过程中应力缓冲层的损耗，以延长半导体装置的使用寿命。
以上所述，仅是本发明的优选实施例而已，并非对本发明作任何形式上的限制，虽然已以优选实施例揭露了本发明，然而并非用以限定本发明,任何熟悉本专业的技术人员,在不脱离本发明技术方案范围内，可利用上述揭示的方法及技术内容作出些许的更动或修饰为等同变化的等效实施例，但凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本发明技术方案的范围内。

Claims (20)

1.一种半导体装置，其特征在于，包括：
半导体基材，具有至少一金属垫；
第一保护层，形成于所述半导体基材上且覆盖部分所述至少一金属垫，所述第一保护层具有至少一第一保护层开口，以显露部分所述至少一金属垫；
第二保护层，形成于所述第一保护层上，所述第二保护层具有至少一第二保护层开口，以显露部分所述至少一金属垫；
凸块下金属层，至少形成于经所述第二保护层开口显露的部分所述至少一金属垫；
应力缓冲层，形成于所述凸块下金属层上；以及
铜柱，设置于所述应力缓冲层上。
2.如权利要求1所述的半导体装置，其特征在于，所述应力缓冲层的材料选自锡、锡银、锡合金、铟及铟合金其中之一，以及所述凸块下金属层的材料选自钛、钛钨及铜其中之一。
3.如权利要求1所述的半导体装置，其特征在于，所述半导体装置还包含焊料结构，设置于所述铜柱上。
4.如权利要求1所述的半导体装置，其特征在于，所述半导体装置还包含阻障层，设置于所述铜柱与所述应力缓冲层之间。
5.如权利要求4所述的半导体装置，其特征在于，所述阻障层的材料为镍、钛或钽。
6.如权利要求1所述的半导体装置，其特征在于，所述应力缓冲层的表面不高于所述第二保护层的表面。
7.如权利要求1所述的半导体装置，其特征在于，所述铜柱的横截面积大于或等于所述应力缓冲层的横截面积。
8.如权利要求1所述的半导体装置，其特征在于，所述第一保护层开口的面积大于所述第二保护层开口的面积，且所述铜柱的横截面积大于所述第一保护层开口及所述第二保护层开口的面积。
9.如权利要求1所述的半导体装置，其特征在于，所述第一保护层开口小于所述第二保护层开口的面积，且所述凸块下金属层直接接触所述第一保护层及所述第二保护层。
10.如权利要求1所述的半导体装置，其特征在于，所述凸块下金属层还形成于所述第二保护层开口的内壁及所述第二保护层开口周缘的部分所述第二保护层上。
11.如权利要求10所述的半导体装置，其特征在于，所述铜柱还覆盖所述第二保护层开口周缘的部分所述第二保护层。
12.一种半导体装置的制作方法，其特征在于，包括：
提供半导体基材，所述半导体基材具有至少一金属垫；
形成第一保护层于所述半导体基材上且覆盖部分所述至少一金属垫，所述第一保护层具有至少一第一保护层开口，以显露部分所述至少一金属垫；
形成第二保护层于所述第一保护层上，所述第二保护层具有至少一第二保护层开口，以显露部分所述至少一金属垫；
形成凸块下金属层于显露的部分所述至少一金属垫、所述第二保护层开口的内壁及部分所述第二保护层上；
形成应力缓冲层于所述至少一金属垫上方的部分所述凸块下金属层上；
形成铜柱于所述应力缓冲层上，以覆盖所述应力缓冲层及部分所述凸块下金属层；以及
形成焊料结构于所述铜柱上。
13.如权利要求12所述的半导体装置的制作方法，其特征在于，所述应力缓冲层的材料选自锡、锡银、锡合金、铟及铟合金其中之一。
14.如权利要求12所述的半导体装置的制作方法，其特征在于，在形成铜柱之前，还先形成阻障层于所述应力缓冲层上，使得所述阻障层位于所述应力缓冲层及所述铜柱之间，所述阻障层的材料为镍、钛或钽。
15.如权利要求12所述的半导体装置的制作方法，其特征在于，所述应力缓冲层的表面不高于所述第二保护层的表面。
16.如权利要求12所述的半导体装置的制作方法，其特征在于，所述应力缓冲层、所述铜柱及所述焊料结构的形成包含以下步骤：
形成第一光致抗蚀剂层于所述凸块下金属层上，并形成至少一第一开口于所述第一光致抗蚀剂层，以经由所述第一开口显露部分所述凸块下金属层；
电镀所述应力缓冲层于所述第一开口显露的部分所述凸块下金属层上；
电镀所述铜柱于所述第一开口显露的所述应力缓冲层上；
电镀所述焊料结构于所述铜柱上；以及
移除所述第一光致抗蚀剂层。
17.如权利要求16所述的半导体装置的制作方法，其特征在于，所述铜柱还覆盖所述应力缓冲层周边的部分所述凸块下金属层。
18.如权利要求17所述的半导体装置的制作方法，其特征在于，在移除所述第一光致抗蚀剂层之后或者同时，并移除未被所述铜柱覆盖的部分所述凸块下金属层。
19.如权利要求12所述的半导体装置的制作方法，其特征在于，所述应力缓冲层、所述铜柱及所述焊料结构的形成包含以下步骤：
形成第一光致抗蚀剂层于所述凸块下金属层上，并形成至少一第一开口于所述第一光致抗蚀剂层中，以经由所述第一开口显露部分所述凸块下金属层；
电镀所述应力缓冲层于所述第一开口显露的部分所述凸块下金属层上；
移除所述第一光致抗蚀剂层；
形成第二光致抗蚀剂层于所述凸块下金属层上，并形成至少一第二开口于所述第二光致抗蚀剂层中，所述第二开口大于所述第一开口，以经由所述第二开口显露所述应力缓冲层及部分所述凸块下金属层；
电镀所述铜柱于所述第二开口显露的所述应力缓冲层及部分所述凸块下金属层上；
电镀所述焊料结构于所述铜柱上；以及
移除所述第一光致抗蚀剂层及所述第二光致抗蚀剂层。
20.如权利要求19所述的半导体装置的制作方法，其特征在于，在移除所述第二光致抗蚀剂层之后或者同时，并移除未被所述铜柱覆盖的部分所述凸块下金属层。
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