CN111508828A - 3D memory device and method of manufacturing the same - Google Patents

Abstract

The application discloses a 3D memory device and a method of manufacturing the same. The method includes forming a first wafer including a first substrate, a first connection structure on a first surface of the first substrate, at least one conductive structure extending down the first surface of the first substrate and through a partial region of the first substrate; forming a second wafer comprising a second substrate and a third connection structure on the surface of the second substrate; the first wafer is bonded with the second wafer, the first connecting structure is electrically connected with the third connecting structure, and the position of the conductive structure corresponds to that of the first connecting structure. The present application forms conductive structures in a first wafer prior to bonding between the wafers, and exposes existing conductive structures after bonding to enable connection to external circuitry. The process difficulty is simplified, the alignment degree between the conductive channel and the semiconductor structure on the substrate is optimized, and the yield of the semiconductor device is improved.

Description

3D memory device and method of manufacturing the same

technical field

The present invention relates to semiconductor process technology, and more particularly, to a 3D memory device and a method of manufacturing the same.

Background technique

3D memory devices include multiple memory cells stacked in a vertical direction, which can exponentially increase the integration level on a wafer per unit area, and can reduce costs. Electrical connections are made between the plurality of memory cells, and the substrate of the semiconductor structure is thinned from the backside to form conductive vias in the substrate for external connections.

Currently, in the fabrication of 3D memory, at least two wafers in a semiconductor structure are first bonded, followed by thinning the substrate on the backside and forming conductive vias in the substrate that connect the substrate surface through the array connection structure and external electrical connection. However, since the bonding process requires the center of the top film to be pressed down with a thimble, and the edge of the substrate is fixed by a robot, the film will be bent and deformed, and this process will cause irreversible distortion of each exposure unit in the semiconductor structure. deformation, resulting in poor control of alignment in the via process after the bonding process is completed.

It is expected to further improve the 3D memory device manufacturing method to improve the yield and reliability of the 3D memory device.

SUMMARY OF THE INVENTION

The object of the present invention is to provide a 3D memory device and a method for manufacturing the same, wherein, by fabricating the conductive structure connected to the outside before wafer bonding, after bonding at least two wafers, on the first wafer In the process of thinning the first substrate, the existing conductive structure is exposed to realize the connection with the external circuit, which avoids exposure after wafer bonding, simplifies the process difficulty, and optimizes the conductive channel and the external connection. Alignment between semiconductor structures, thereby improving the yield of semiconductor devices.

According to an aspect of the present invention, there is provided a method for manufacturing a 3D memory device, comprising: forming a first wafer including a first substrate, a first connection structure on a first surface of the first substrate, and at least one conductive structure extending downward from a first surface of a first substrate and penetrating a partial region of the first substrate; and forming a second wafer including a second substrate and a third connection structure on the surface of the second substrate; The first wafer is bonded to the second wafer, and the first connection structure is electrically connected to the third connection structure, wherein the conductive structure corresponds to the position of the first connection structure.

Preferably, the step of forming the first connection structure includes: forming the first connection structure in contact with the conductive structure above the conductive structure.

Preferably, after the first wafer and the second wafer are bonded, the method further includes: forming a conductive channel through the first substrate from the conductive structure, and one end of the conductive channel is exposed on the first substrate. Outside the second surface of a substrate, the other end of the conductive channel is in contact with the first connection structure for electrical connection.

Preferably, the method further includes: a second connection structure electrically connected to the first connection structure is provided in the first wafer, one end of the second connection structure is connected to the first connection structure, and the second connection structure is connected to the first connection structure. The other end of the structure is connected to the third connecting structure.

Preferably, the step of forming the conductive structure includes: forming at least one groove extending downward along the first surface of the first substrate through a partial region of the first substrate; depositing glue in the groove layer and/or barrier layer, metal layer to form the conductive structure.

Preferably, the step of forming the conductive channel includes: after turning the bonded semiconductor structure over, thinning the first substrate along the second surface of the first substrate, so that the conductive structure penetrates through all the conductive channels. The first substrate after the thinning process is described.

Preferably, the step of forming the conductive structure comprises: extending downward along the first surface of the first substrate to form at least one trench penetrating a partial region of the first substrate; In the step of forming the first connection structure on the surface, the conductive structure is formed in the groove.

Preferably, the step of forming the groove comprises: forming a sacrificial layer on the first surface of the first substrate; patterning on the sacrificial layer; and etching to form at least one in the first substrate one of the grooves.

Preferably, the first wafer is a CMOS circuit or a memory cell array, and the second wafer is a CMOS circuit or a memory cell array.

According to another aspect of the present invention, there is provided a 3D memory device including: a first wafer including a first substrate, a first connection structure on a first surface of the first substrate, and a first wafer along the first substrate. at least one conductive structure extending downward from a first surface of a substrate and penetrating a partial region of the first substrate; and a second wafer bonded to the first wafer, including a second substrate and a surface on the second substrate the third connection structure; the first connection structure is electrically connected with the third connection structure; wherein, the conductive structure corresponds to the position of the first connection structure.

Preferably, the first connection structure is located above and in contact with the conductive structure.

Preferably, the conductive structure is exposed as a conductive channel through the first substrate, one end of the conductive channel is exposed outside the second surface of the first substrate, and the other end of the conductive channel is connected to the first substrate. The first connection structure contacts to realize electrical connection.

Preferably, it also includes: a second connection structure, located in the first wafer and electrically connected to the first connection structure, one end of the second connection structure is connected to the first connection structure, the second connection structure The other end of the connection structure is connected to the third connection structure.

Preferably, the first wafer is a CMOS circuit or a memory cell array, and the second wafer is a CMOS circuit or a memory cell array.

According to the 3D memory device obtained by the manufacturing method of the 3D memory device provided by the embodiment of the present invention, the three-dimensional bonding process is used to realize electrical connection between the wafers. Before performing the bonding process between the wafers, by providing grooves along the first surface of the first substrate corresponding to the positions of the first connection structures formed on the first substrate, and after performing the bonding process, thinning The second surface of the first substrate exposes the recess and forms a conductive channel in the recess for connecting the semiconductor structure to the outside. The alignment of the conductive channel connected to the outside and the connection structure in the semiconductor structure is not affected by the bonding process, the process difficulty is simplified without increasing the cost, and the conductive channel and the wafer for connection to the external are optimized. The alignment between the semiconductor structures on the substrate improves the yield of the semiconductor device.

Description of drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings.

FIG. 1 shows a schematic flowchart of a method for manufacturing a 3D memory device according to an embodiment of the present invention.

FIG. 2 shows a schematic flowchart of forming a first wafer in a method for manufacturing a 3D memory device according to an embodiment of the present invention.

3 to 9 illustrate cross-sectional views of various stages of a method of fabricating a 3D memory device according to an embodiment of the present invention.

Detailed ways

The present invention will be described in more detail below with reference to the accompanying drawings. In the various figures, like elements are designated by like reference numerals. For the sake of clarity, various parts in the figures have not been drawn to scale. Additionally, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be depicted in one figure.

It will be understood that, in describing the structure of a device, when a layer or region is referred to as being "on" or "over" another layer or region, it can be directly on the other layer or region, or Other layers or regions are also included between it and another layer, another region. And, if the device is turned over, the layer, one region, will be "under" or "under" another layer, another region.

In this application, the term "semiconductor structure" refers collectively to the entire semiconductor structure formed during the various steps of fabricating a memory device, including all layers or regions that have already been formed. Numerous specific details of the present invention are described below, such as device structures, materials, dimensions, processing techniques and techniques, in order to provide a clearer understanding of the present invention. However, as can be understood by one skilled in the art, the present invention may be practiced without these specific details.

The inventors of the present application have noticed the above-mentioned problems affecting the yield and reliability of 3D memory devices, and thus propose a further improved manufacturing method of 3D memory devices.

The invention may be embodied in various forms, some examples of which will be described below.

FIG. 1 shows a schematic flowchart of a method for manufacturing a 3D memory device according to an embodiment of the present invention. FIG. 2 shows a schematic flowchart of forming a first wafer in a method for manufacturing a 3D memory device according to an embodiment of the present invention. 3 to 9 illustrate cross-sectional views of various stages of a method of fabricating a 3D memory device according to an embodiment of the present invention.

The 3D memory device manufacturing method adopts the above-mentioned 3D memory device manufacturing method to improve the yield and reliability of the 3D memory device. The manufacturing method of the 3D memory device includes the following steps:

In step S10, a first wafer is provided. A first wafer includes a first substrate, a first connection structure on a first surface of the first substrate, and at least a portion of the first substrate extending downwardly along the first surface of the first substrate a conductive structure. Specifically, in conjunction with accompanying drawing 2, this step comprises the following steps:

In step S11, at least one groove is formed along the first surface of the first substrate. Specifically, with reference to FIG. 3 , at least one groove 201 extending through a partial region of the first substrate 101 extends downward along the first surface of the first substrate 101 . Further, a patterned mask is employed on the first surface of the first substrate 101 to form at least one groove 201 in the first substrate 101 .

In step S12, an adhesive layer and/or a barrier layer and a metal layer are deposited in the groove to form a conductive structure. Specifically, with reference to FIG. 4 , an adhesive layer and/or a barrier layer and a metal layer are sequentially deposited along the first surface of the first substrate 101 toward the groove 201 to form the conductive structure 102 .

In step S13, a first interconnect structure is formed on the first surface of the first substrate. Specifically, with reference to FIG. 5 , a first connection structure 111 is formed on the first surface of the first substrate 101 . For example, the first wafer has a CMOS circuit structure or a memory cell array structure. In this embodiment, the first wafer is described by taking a memory cell array as an example, and a first array structure 110 is formed on the first surface of the first substrate 101 , and the first array structure 110 is a memory cell array. Then, a first connection structure 111 is formed through the first array structure 110 , wherein the first connection structure 111 corresponds to the position of the conductive structure 102 .

In other preferred embodiments, step S14 is further included: a second connection structure is further formed on the surface of the first array structure 110 facing away from the first surface of the first substrate 101 . Specifically, with reference to FIG. 6 , the second connection structure includes a first insulating layer 112 on the surface of the first array structure 110 facing away from the first surface of the first substrate 101 , a first insulating layer 112 located in the first insulating layer 112 and connected to the first A first connection portion 113 connected by the connection structure 110 , a first metal layer 114 located in the first insulating layer 112 and connected to the first connection portion 113 , a second connection located in the first insulating layer 112 and connected to the first metal layer 114 part 115 , a second metal layer 116 located in the first insulating layer 112 and connected to the second connection part 115 , and a third connection part 117 located in the first insulating layer 112 and connected to the second metal layer 116 . The second connection structure is used to achieve electrical connection between the first connection structure 110 and the subsequent semiconductor structures connected to the first array structure. The second connection structure is, for example, a CMOS circuit structure.

In step S20, a second wafer is provided. The second wafer includes a second substrate and a third connection structure on a surface of the second substrate. Specifically, in conjunction with FIG. 7 , a second wafer 120 is provided. The second wafer 120 includes a fourth connection portion 121 as a third connection structure and, for example, a semiconductor layer 122 connected to the fourth connection portion 121 , and a memory cell array structure, for example, is formed on the surface of the semiconductor layer 122 away from the fourth connection portion 121 . Or CMOS circuit structure.

In step S30, the first wafer is bonded with the second wafer. An end of the first connection structure 111 in the first wafer away from the substrate is electrically connected to the fourth connection portion 121 as the third connection structure in the second wafer 120 , so as to bond the first wafer to the second wafer.

It should be noted that, when the embodiment of the first wafer also forms a second connection structure connected to the end of the first connection structure 111 away from the substrate on the surface of the first array structure 110 away from the substrate as in the preferred embodiment, As shown in FIG. 8 , the second connection structure is bonded and connected to the second wafer 120 . Further, a bonding process is used to connect the surface exposed to the outside of the second connection structure formed on the surface of the first array structure 110 away from the substrate and the surface exposed to the outside of the third connection structure of the second wafer 120 . . The third connection portion 117 of the second connection structure in the first wafer is electrically connected to the fourth connection portion 121 of the third connection structure in the second wafer 120, so that the electrical connection between the first wafer and the second wafer is electrically connected. connect.

In step S40, the conductive structures of the first wafer are exposed to the outside to form conductive channels. Specifically, as shown in FIG. 9 , the bonded semiconductor structure is turned over, and the first substrate 101 is thinned along the second surface of the first substrate 101 so as to stop when the bottom of the conductive structure 102 is exposed to the outside. Conductive vias 103 are formed. One end of the conductive channel 103 is in contact with and electrically connected to the first connection structure 111 , and the other end of the conductive channel 103 is higher than the second surface of the first substrate 101 to be exposed to the outside for external electrical connection.

According to the 3D memory device obtained by the 3D memory device manufacturing method provided in the present application, the three-dimensional bonding process is used to realize electrical connection between the wafers. Before performing the bonding process between the wafers, by providing grooves along the first surface of the first substrate corresponding to the positions of the first connection structures formed on the first substrate, and after performing the bonding process, thinning The second surface of the first substrate exposes the groove and forms a conductive channel in the groove for electrical connection with the external circuit. The alignment of the conductive channel connected with the external circuit and the connection structure in the semiconductor structure is not affected by the bonding process, the process difficulty is simplified without increasing the cost, and the conductive channel for connecting with the external is optimized. The alignment between the connection structures improves the yield of the semiconductor device.

In the above description, technical details such as patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as those described above. Additionally, although the various embodiments have been described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

Embodiments of the present invention have been described above. However, these examples are for illustrative purposes only, and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present invention.

Claims (13)

1. A method for manufacturing a 3D memory device, comprising: A first wafer is formed, including a first substrate, a first connection structure on a first surface of the first substrate, and extending down and through the first substrate along the first surface of the first substrate at least one conductive structure of the partial area; and forming a second wafer, including a second substrate and a third connection structure on the surface of the second substrate; the first wafer is bonded to the second wafer; the first connection structure is electrically connected to the third connection structure; Wherein, the conductive structure corresponds to the position of the first connection structure. 2. The method for manufacturing a 3D memory device according to claim 2, wherein the step of forming the first connection structure comprises: The first connection structure in contact with the conductive structure is formed above the conductive structure. 3. The method for manufacturing a 3D memory device according to claim 1, wherein after the first wafer and the second wafer are bonded, further comprising: Exposing the conductive structure to form a conductive channel through the first substrate, one end of the conductive channel is exposed outside the second surface of the first substrate, and the other end of the conductive channel is connected to the first substrate The connection structures are in contact for electrical connection. 4. The method for manufacturing a 3D memory device according to claim 1, further comprising: forming a second connection structure electrically connected to the first connection structure in the first wafer, one end of the second connection structure is connected with the first connection structure, and the other end of the second connection structure is connected with the third connection structure. 5. The method of manufacturing a 3D memory device according to claim 3, wherein the step of forming the conductive structure comprises: extending downward along the first surface of the first substrate to form at least one trench through the partial region of the first substrate; A glue layer and/or a barrier layer and a metal layer are deposited in the groove to form the conductive structure. 6. The method of manufacturing a 3D memory device according to claim 5, wherein the step of forming the conductive channel comprises: After the bonded semiconductor structure is turned over, the first substrate is thinned along the second surface of the first substrate, so that the conductive structure penetrates the thinned first substrate. 7. The method of manufacturing a 3D memory device according to claim 5, wherein the step of forming the groove comprises: forming a sacrificial layer on the first surface of the first substrate; patterning on the sacrificial layer; and etching to form at least one of the grooves in the first substrate. 8. The method for manufacturing a 3D memory device according to claim 1, wherein the first wafer is a CMOS circuit or a memory cell array, and the second wafer is a CMOS circuit or a memory cell array. 9. A 3D memory device, comprising: A first wafer including a first substrate, a first connection structure on a first surface of the first substrate, and a portion extending down the first surface of the first substrate and through the first substrate at least one conductive structure of the region; and a second wafer bonded to the first wafer, comprising a second substrate and a third connection structure on the surface of the second substrate; the first connection structure is electrically connected to the third connection structure; Wherein, the conductive structure corresponds to the position of the first connection structure. 10. The 3D memory device of claim 9, wherein the first connection structure is located above and in contact with the conductive structure. 11. The 3D memory device of claim 9, wherein the conductive structure is exposed as a conductive via passing through the first substrate, and one end of the conductive via is exposed at the second surface of the first substrate outside, the other end of the conductive channel is in contact with the first connection structure to realize electrical connection. 12. The 3D memory device of claim 9, further comprising: A second connection structure is located in the first wafer and is electrically connected to the first connection structure, one end of the second connection structure is connected to the first connection structure, and the other end of the second connection structure is connected to the first connection structure. The third connection structure is connected. 13. The 3D memory device of claim 9, wherein the first wafer is a CMOS circuit or a memory cell array, and the second wafer is a CMOS circuit or a memory cell array.

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