CN111508545B - Control circuit for repairing flash memory and method for repairing flash memory - Google Patents
Control circuit for repairing flash memory and method for repairing flash memory Download PDFInfo
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- CN111508545B CN111508545B CN202010300343.5A CN202010300343A CN111508545B CN 111508545 B CN111508545 B CN 111508545B CN 202010300343 A CN202010300343 A CN 202010300343A CN 111508545 B CN111508545 B CN 111508545B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
- G11C29/765—Masking faults in memories by using spares or by reconfiguring using address translation or modifications in solid state disks
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/835—Masking faults in memories by using spares or by reconfiguring using programmable devices with roll call arrangements for redundant substitutions
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/838—Masking faults in memories by using spares or by reconfiguring using programmable devices with substitution of defective spares
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention provides a control circuit for repairing a flash memory and a method for repairing the flash memory. The control circuit of the repair flash memory comprises a first logic module and a second logic module which are respectively used for receiving and processing selection signals of even-numbered row redundancy sub-blocks, selection signals of odd-numbered row redundancy sub-blocks and row direction secondary low-order address signals of damaged storage sub-blocks and then respectively outputting first logic signals and second logic signals, and a third logic module receives and processes the first logic signals and the second logic signals and then outputs inner and outer side exchange control signals, wherein the inner and outer side exchange control signals and high-voltage control signals scheduled to be applied to the damaged storage sub-blocks are subjected to exclusive OR operation to obtain bit line high-voltage control signals applied to the replacement redundancy sub-blocks. The control circuit for repairing the flash memory can enable the odd-line redundant subblocks and the even-line redundant subblocks to replace damaged storage subblocks, and improves the utilization rate of the redundant subblocks. The invention also provides a method for repairing the flash memory.
Description
Technical Field
The present invention relates to the field of circuit technologies, and in particular, to a control circuit for repairing a flash memory and a method for repairing a flash memory.
Background
Flash Memory (Flash Memory) is a Non-Volatile Memory that can still hold stored data information in the event of a power failure. Flash memory does not need special high voltage during electric erasing and repeated programming, and has the characteristics of low manufacturing cost, high storage density and the like, so that the flash memory becomes the mainstream of nonvolatile semiconductor storage technology. Among them, the dual split gate flash memory (NORD Cell) is one of the main nonvolatile memories on the market because of high transmission efficiency and high cost effectiveness at a small capacity of 1-4 MB.
FIG. 1 is a schematic plan view of a memory array of a dual split gate flash memory. As shown in the dashed boxes in fig. 1, a7=0 is an even memory sub-block (sector) including four memory bits A, B, C, D, a7=1 is an odd memory sub-block including four memory bits a ', B', C ', D', and memory bits A, B, C, D, A ', B', C ', D' are a repeating unit of the memory array, which is correspondingly connected to three bit lines BL0<0>, BL1<0>, BL2<0>, and two control gate lines CG0 and CG1, wherein memory bits a and B 'are connected to bit line BL0<0>, memory bits B, D, A' and C 'are connected to bit line BL1<0>, and memory bits C and D' are connected to bit line BL2<0>. It can be seen that the bit line selections corresponding to the storage bits connected to the two control gate lines (CG 0 and CG 1) in the even storage sub-block and the odd storage sub-block corresponding to the same repeating unit are different, so that the levels required to be applied to each bit line by the even storage sub-block and the odd storage sub-block are different when the storage control is performed, and the distinction processing is required.
Taking the memory bits A, B, A ' and B ' of a memory array as an example, if the memory bits A and B ' are to be stored, a lower voltage (e.g., 0V) is applied to BL0<0>, a higher voltage (e.g., 0.8V) is applied to BL1<0>, and a higher voltage (e.g., 0.8V) is applied to BL2<0 >; in order to perform the memory operation on the memory bits B and A', a higher voltage (e.g., 0.8V) is applied to BL0<0>, a lower voltage (e.g., 0V) is applied to BL1<0>, and a lower voltage (e.g., 0V) is applied to BL2<0>. It can be seen that the levels applied to the three bit lines when the even memory sub-blocks (a and B) corresponding to a7=0 are operated and the levels applied to the three bit lines when the odd memory sub-blocks (a 'and B') corresponding to a7=1 are operated are reversed.
In conventional circuit operation, when a memory sub-block is defective, it is necessary to replace it with a redundant sub-block disposed in another area on the memory array. The arrangement of the redundant subblocks is substantially identical to that of the even storage subblocks and the odd storage subblocks. According to the above analysis, with the memory array of the above structure, when even memory subblocks are damaged, only even row redundancy subblocks (RDN is 0,2, 4) can be used for replacement repair, and when odd memory subblocks are damaged, only odd row redundancy subblocks (RDN is 1,3, 5) can be used for replacement repair, i.e. when damaged memory subblocks of the flash memory are repaired, the use of the redundancy subblocks is limited by the selection of corresponding bit lines, which affects the utilization rate of the redundancy subblocks.
Disclosure of Invention
The invention provides a control circuit for repairing a flash memory, which aims to solve the problem that when a damaged storage subblock of the flash memory is replaced by a redundant subblock, the use of the redundant subblock is limited, and the utilization rate of the redundant subblock is affected. The invention also provides a method for repairing the flash memory.
In order to solve the above-mentioned problems, an aspect of the present invention provides a control circuit for repairing a flash memory, for providing a bit line high voltage control signal to a redundancy sub-block to be replaced when a memory sub-block is damaged, the memory sub-block including an odd line memory sub-block and an even line memory sub-block, an inner memory bit of a group of adjacent odd line memory sub-block and even line memory sub-block being connected to a same bit line and an outer memory bit being connected to two bit lines in two columns, each of the bit lines being controlled by the bit line high voltage control signal, the redundancy sub-block including an odd line redundancy sub-block and an even line redundancy sub-block, the control circuit comprising:
the input end of the first logic module is connected with selection signals of a plurality of even-numbered row redundancy sub-blocks and row direction secondary low-order address signals of the damaged storage sub-blocks, and a first logic signal is output through logic operation;
the input end of the second logic module is connected with selection signals of a plurality of odd-numbered row redundancy sub-blocks and row direction secondary low-order address signals of the damaged storage sub-blocks, and a second logic signal is output through logic operation;
and the two input ends of the third logic module are respectively connected with the output end of the first logic module and the output end of the second logic module, the third logic module is used for carrying out logic operation on the first logic signal and the second logic signal and outputting an inside-outside exchange control signal, and the inside-outside exchange control signal is used for carrying out exclusive OR operation on the inside-outside exchange control signal and a high-voltage control signal scheduled to be applied to a damaged storage subblock so as to obtain a bit line high-voltage control signal applied to a selected redundancy subblock, so that the odd-line redundancy subblock and the even-line redundancy subblock can both replace the damaged storage subblock.
Optionally, if the damaged storage sub-block is an odd-line storage sub-block, the row direction sub-low address signal is at a high level, when the odd-line redundancy sub-block is selected for replacement, the selection signal of the even-line redundancy sub-block is at a low level, the selection signal of the odd-line redundancy sub-block is at a high level, the first logic signal is at a low level, the second logic signal is at a low level, the inner and outer side exchange control signals are at a low level, and the level of the bit line high voltage control signal applied to the selected odd-line redundancy sub-block is the same as the level of the high voltage control signal scheduled to be applied to the damaged storage sub-block.
Optionally, if the damaged memory sub-block is an odd-numbered row memory sub-block, the row direction sub-low address signal is at a high level, when an even-numbered row redundancy sub-block is selected for replacement, the selection signal of the even-numbered row redundancy sub-block is at a high level, the selection signal of the odd-numbered row redundancy sub-block is at a low level, the first logic signal is at a high level, the second logic signal is at a low level, the inner and outer side exchange control signals are at a high level, and the level of the bit line high voltage control signal applied to the selected even-numbered row redundancy sub-block is opposite to the level of the high voltage control signal scheduled to be applied to the damaged memory sub-block.
Optionally, if the damaged memory sub-block is an even-numbered row memory sub-block, the row direction sub-low address signal is at a low level, when the odd-numbered row redundancy sub-block is selected for replacement, the selection signal of the even-numbered row redundancy sub-block is at a low level, the selection signal of the odd-numbered row redundancy sub-block is at a high level, the first logic signal is at a low level, the second logic signal is at a high level, the inner and outer side exchange control signals are at a high level, and the level of the bit line high voltage control signal applied to the selected odd-numbered row redundancy sub-block is opposite to the level of the high voltage control signal scheduled to be applied to the damaged memory sub-block.
Optionally, if the damaged memory sub-block is an even-numbered row memory sub-block, the row direction sub-low address signal is a low level, when the even-numbered row redundancy sub-block is selected for replacement, the selection signal of the even-numbered row redundancy sub-block is a high level, the selection signal of the odd-numbered row redundancy sub-block is a low level, the first logic signal is a low level, the second logic signal is a low level, the inner and outer side exchange control signals are a low level, and the level of the bit line high voltage control signal applied to the selected even-numbered row redundancy sub-block is the same as the level of the high voltage control signal planned to be applied to the damaged memory sub-block.
Optionally, the first logic module includes a first nor gate, a second nor gate, and a first nor gate, where a selection signal of the even-numbered row redundancy sub-block is input from an input port of the first nor gate, an output port of the first nor gate is connected to an input port of the second nor gate, a row-direction next-lower address signal of the damaged memory sub-block is input from an input port of the first nor gate, an output port of the first nor gate is connected to another input port of the second nor gate, an output port of the second nor gate is connected to an input port of the third logic module, and an output port of the second nor gate is output from an output port of the third logic module.
Optionally, the second logic module includes a third nor gate and a fourth nor gate, the selection signal of the redundant sub-block of the odd-numbered row is input from an input port of the third nor gate, an output port of the third nor gate is connected with an input port of the fourth nor gate, the row direction next lower address signal of the damaged memory sub-block is input from another input port of the fourth nor gate, an output port of the fourth nor gate is connected with another input port of the third logic module, and an output port of the fourth nor gate connected with the third logic module outputs the second logic signal.
Optionally, the third logic module includes a fifth nor gate and a second nor gate, where two input ports of the fifth nor gate are respectively connected to output ports of the first logic module and the second logic module, and are used to receive the first logic signal and the second logic signal, and an output port of the fifth nor gate is connected to an input port of the second nor gate, and an output port of the second nor gate outputs an internal-external exchange control signal.
Another aspect of the present invention provides a method of repairing a flash memory for providing a bit line high voltage control signal to a replacement redundancy subblock when a storage subblock is damaged, the storage subblock including an odd row storage subblock and an even row storage subblock, an inner storage bit of a group of adjacent odd row storage subblocks and even row storage subblocks being connected to a same bit line and an outer storage bit being connected to two bit lines in two columns, each of the bit lines being controlled by the bit line high voltage control signal, the redundancy subblock including an odd row redundancy subblock and an even row redundancy subblock, the method comprising:
acquiring a row direction next lower address signal of a damaged storage sub-block and a bit line high voltage control signal planned to be applied to the damaged storage sub-block;
selecting a redundant subblock as a replacement for the damaged storage subblock, the redundant subblock being an odd-line redundant subblock or an even-line redundant subblock;
performing logic operation on the selection signals of the even-numbered row redundancy sub-blocks and the row-direction sub-low address signals of the damaged storage sub-blocks to obtain first logic signals, and performing logic operation on the selection signals of the odd-numbered row redundancy sub-blocks and the row-direction sub-low address signals of the damaged storage sub-blocks to obtain second logic signals, wherein the selection signals of the redundancy sub-blocks used for replacing are included in the selection signals of the even-numbered row redundancy sub-blocks or the odd-numbered row redundancy sub-blocks;
performing logic operation on the first logic signal and the second logic signal and outputting an inside-outside exchange control signal; and
and performing exclusive OR operation on the inner and outer side exchange control signals and the high voltage control signals scheduled to be applied to the damaged storage subblocks to obtain bit line high voltage control signals applied to the redundancy subblocks for replacement, so that the redundancy subblocks for replacement operate according to the control mode of the damaged storage subblocks.
Alternatively, if the damaged memory subblock is an odd-line memory subblock, when the odd-line redundancy subblock is selected for replacement, the level of the bit line high-voltage control signal applied to the selected odd-line redundancy subblock is the same as the level of the high-voltage control signal scheduled to be applied to the damaged memory subblock, or when the even-line redundancy subblock is selected for replacement, the level of the bit line high-voltage control signal applied to the selected even-line redundancy subblock is opposite to the level of the high-voltage control signal scheduled to be applied to the damaged memory subblock; if the damaged memory subblock is an even-line memory subblock, when an odd-line redundancy subblock is selected for replacement, the level of the bit line high-voltage control signal applied to the selected odd-line redundancy subblock is opposite to the level of the high-voltage control signal intended for the damaged memory subblock, or when an even-line redundancy subblock is selected for replacement, the level of the bit line high-voltage control signal applied to the selected even-line redundancy subblock is the same as the level of the high-voltage control signal intended for the damaged memory subblock.
The control circuit for repairing the flash memory outputs an inner side exchange control signal and an outer side exchange control signal through carrying out logic operation on a selection signal of an even-numbered row redundancy sub-block, a selection signal of an odd-numbered row redundancy sub-block and a row direction secondary low-order address signal of a damaged storage sub-block, and then carries out exclusive OR operation on the inner side exchange control signal and the outer side exchange control signal and a high-voltage control signal scheduled to be applied to the damaged storage sub-block to obtain a bit line high-voltage control signal applied to the selected redundancy sub-block, so that the odd-numbered row redundancy sub-block and the even-numbered row redundancy sub-block can replace the damaged storage sub-block. The control circuit for repairing the flash memory can enable the flash memory to be replaced and repaired by using even-row redundant sub-blocks and odd-row redundant sub-blocks when the storage sub-blocks are damaged, the use of the redundant sub-blocks is not limited, the utilization rate of the redundant sub-blocks is improved, and the storage performance of the flash memory is improved.
The method for repairing the flash memory is applied to the control circuit for repairing the flash memory, so that when the storage sub-blocks of the flash memory are damaged, the flash memory can be replaced and repaired by using even-numbered row redundancy sub-blocks and also can be replaced and repaired by using odd-numbered row redundancy sub-blocks, the use of the redundancy sub-blocks is not limited, the utilization rate of the redundancy sub-blocks is improved, and the storage performance of the flash memory is improved.
Drawings
FIG. 1 is a schematic plan view of a memory array of a dual split gate flash memory.
FIG. 2 is a control circuit diagram of repairing a flash memory according to an embodiment of the invention.
Reference numerals illustrate:
10-a first logic module; 20-a second logic module; 30-a third logic module; 110-a memory cell; i01-a first NOR gate; i02-a second NOR gate; i03-a third NOR gate; i04-a fourth NOR gate; i05-a fifth NOR gate; i11-a first NOT gate; i12-second NOT gate.
Detailed Description
The control circuit for repairing the flash memory and the method for repairing the flash memory provided by the invention are further described in detail below with reference to the accompanying drawings and the specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
In order to solve the problem that when a damaged storage sub-block of a flash memory is replaced by a redundant sub-block, the use of the redundant sub-block is limited, and the utilization rate of the redundant sub-block is affected, in one embodiment of the invention, a control circuit for repairing the flash memory is related to the control circuit for providing a bit line high voltage control signal for the replaced redundant sub-block when the storage sub-block is damaged, wherein the storage sub-block comprises an odd line storage sub-block and an even line storage sub-block, the inner side storage bits of a group of adjacent odd line storage sub-block and even line storage sub-block are connected with the same bit line, the outer side storage bits are connected with two bit lines in two columns, each bit line is controlled by the bit line high voltage control signal, the redundant sub-block comprises an odd line redundant sub-block and an even line redundant sub-block, the control circuit comprises a first logic module, a second logic module and a third logic module, the input end of the first logic module is connected with a plurality of selection signals of the even-numbered row redundancy sub-blocks and row direction secondary low-order address signals of the damaged storage sub-blocks, a first logic signal is output through logic operation, the input end of the second logic module is connected with a plurality of selection signals of the odd-numbered row redundancy sub-blocks and row direction secondary low-order address signals of the damaged storage sub-blocks, a second logic signal is output through logic operation, two input ends of the third logic module are respectively connected with the output end of the first logic module and the output end of the second logic module, the third logic module is used for carrying out logic operation on the first logic signal and the second logic signal and outputting an inner-outer side exchange control signal (Innercell-Change), the inner and outer side exchange control signals are used for performing exclusive OR operation with the high voltage control signals scheduled to be applied to the damaged storage subblocks to obtain bit line high voltage control signals applied to the selected redundancy subblocks, so that the odd-line redundancy subblocks and the even-line redundancy subblocks can replace the damaged storage subblocks.
In this embodiment, the storage sub-block is located in a storage array. As shown in fig. 1, the memory array includes a plurality of memory cells 110 (shown by dashed oval), which may be dual split gate flash memory (NORD Cell) and each of which includes two memory bits, the memory sub-blocks include odd-line memory sub-blocks (e.g., odd memory sub-blocks of a7=1) and even-line memory sub-blocks (e.g., even memory sub-blocks of a7=0), wherein the odd-line and even-line refer to parity in the row direction of the memory sub-blocks in the memory array, and the parity is opposite, and the memory array includes a plurality of sets of adjacent odd-line memory sub-blocks and even-line memory sub-blocks, and, as an example, A7 is an address of CG (CG 0 and CG 1), and A6 is an address of WL. As shown in fig. 1, the odd memory subblocks of a7=1 and the even memory subblocks of a7=0 are a group of adjacent odd and even memory subblocks, and the memory bits A, B, C, D, A ', B', C ', D' are a repeating unit of the memory array, the repeating unit includes four memory cells, adjacent Inner memory bits B, D, A 'and C' (Inner-cell) are connected to the same bit line BL1<0>, the Outer memory bits A, C, B 'and D' (Outer-cell) are connected to the bit lines BL0<0> and BL2<0> in two columns, respectively, and voltages applied to the bit lines BL0<0>, BL1<0> and BL2<0> are controlled by the bit line high voltage control signal. As an example, when the memory bit a is subjected to a memory operation, the voltage applied to BL0<0> is 0V, and the voltages applied to BL1<0> and BL2<0> are 0.8V by the control of the bit line high voltage control signal; similarly, when the memory bit B is subjected to a memory operation, the voltages applied to BL0<0> are 0.8V, and the voltages applied to BL1<0> and BL2<0> are 0V; when the memory bit C is subjected to a memory operation, voltages applied to BL0<0> and BL1<0> are 0.8V, and a voltage applied to BL2<0> is 0; when the memory bit D is subjected to a memory operation, voltages on BL0<0> and BL1<0> are 0, and a voltage on BL2<0> is 0.8V.
In this embodiment, a redundant array may be disposed on the same substrate on which the memory array is disposed. The redundant array can be formed in the same arrangement mode with the memory array, and the redundant array does not perform signal writing and reading when the memory array is not damaged. When a memory sub-block in the memory array is damaged during operation, the circuit can select a memory Cell (NORD Cell) with an equivalent memory function from the redundant array to replace, and the number of the memory cells in the redundant array can be set according to requirements. Specifically, the redundant array may also include an odd-row redundancy sub-block and an even-row redundancy sub-block, and, similar to the memory array, the bit line arrangements corresponding to the memory bits in the odd-row redundancy sub-block and the even-row redundancy sub-block are different, and the bit line arrangements of the odd-row redundancy sub-blocks in the same column are the same, and the arrangement of the even-row redundancy sub-blocks is the same. The bit line high voltage control signal outputted from the control circuit of the repair flash memory in this embodiment, which is applied to the selected redundancy subblock, is transmitted to the bit line corresponding to the redundancy subblock and controls the voltage applied to the bit line when the redundancy subblock is selected to replace the damaged memory subblock.
FIG. 2 is a control circuit diagram of repairing a flash memory according to an embodiment of the invention. As shown in fig. 2, the first logic block 10 may include a first nor gate I01, a second nor gate I02, and a first nor gate I11, the selection signals (RDNSEL <0>, RDNSEL <2>, RDNSEL <4>, etc.) of the even-numbered row redundancy sub-blocks may be input from an input port of the first nor gate I01, an output port of the first nor gate I01 may be connected to an input port of the second nor gate I02, the row-wise next-lower address signal (e.g., a <7 >) of the defective memory sub-block may be input from an input port of the first nor gate I11, an output port of the first nor gate I11 may be connected to another input port of the second nor gate I02, an output port of the second nor gate I02 may be connected to an input port of the third logic block, and the output port of the second nor gate I02 may be connected to the third logic block.
The second logic module 20 may include a third nor gate I03 and a fourth nor gate I04, the selection signal (RDNSEL <1>, RDNSEL <3>, RDNSEL <5>, etc.) of the odd-numbered row redundancy sub-block may be input from an input port of the third nor gate I03, an output port of the third nor gate I03 is connected to an input port of the fourth nor gate I04, a row-wise next-lower address signal (e.g., a <7 >) of the defective memory sub-block may be input from another input port of the fourth nor gate I04, an output port of the fourth nor gate I04 is connected to another input port of the third logic module, and an output port of the fourth nor gate I04 connected to the third logic module outputs a second logic signal.
The third logic module 30 may include a fifth nor gate I05 and a second nor gate I2, where two input ports of the fifth nor gate I05 are connected to output ports of the first logic module and the second logic module, that is, two input ports of the fifth nor gate I05 are connected to output ports of the second nor gate I02 and the fourth nor gate I04, respectively, the fifth nor gate I05 is configured to receive the first logic signal output by the first logic module 10 and the second logic signal output by the second logic module 20, and an output port of the fifth nor gate I05 is connected to an input port of the second nor gate I12, and an output port of the second nor gate I12 outputs an inside-outside switching control signal (lnnercell-change).
In this embodiment, when a redundancy sub-block is selected to replace a damaged memory sub-block, only the selection signal applied to the selected redundancy sub-block is at a high level, and the selection signals applied to the other non-selected redundancy sub-blocks are all at a low level. For example, when an even row redundancy sub-block is selected, only one of the selection signals RDNSEL <0>, RDNSEL <2>, RDNSEL <4>, etc. of the even row redundancy sub-block is high, such as RDNSEL <0>, RDNSEL <2>, RDNSEL <4>, etc. is low, and the selection signals RDNSEL <1>, RDNSEL <3>, RDNSEL <5>, etc. of the odd row redundancy sub-block are low.
When repairing the damaged storage sub-block, the use of the redundant sub-block for replacing the damaged storage sub-block is not limited by utilizing the control circuit for repairing the flash memory of the embodiment, namely, the damaged storage sub-block can be replaced by the redundant sub-block of even number row or the redundant sub-block of odd number row, so that the utilization rate of the redundant sub-block can be improved, and the storage performance of the flash memory is improved.
Specifically, if the damaged memory subblock is an odd-numbered line memory subblock, the line direction sub-low address signal is at a high level, an odd-numbered line redundancy subblock or an even-numbered line redundancy subblock is selected for replacement, wherein when the odd-numbered line redundancy subblock is selected for replacement, a selection signal of the even-numbered line redundancy subblock is at a low level, a selection signal of the odd-numbered line redundancy subblock is at a high level (one of RDNSEL <1>, RDNSEL <3>, RDNSEL <5>, etc.), the first logic signal is at a low level, the second logic signal is at a low level, the internal and external side switching control signals are at a low level, and a level of a bit line high voltage control signal applied to the selected odd-numbered line redundancy subblock is the same as a level of a high voltage control signal intended to be applied to the damaged memory subblock; when an even row redundancy sub-block is selected for replacement, the selection signal of the even row redundancy sub-block is high (one of RDNSEL <0>, RDNSEL <2>, RDNSEL <4>, etc. is high), the selection signal of the odd row redundancy sub-block is low, the first logic signal is high, the second logic signal is low, the inside-outside switching control signal is high, and the level of the bit line high voltage control signal applied to the selected even row redundancy sub-block is opposite to the level of the high voltage control signal intended to be applied to the damaged memory sub-block.
Selecting an odd-numbered row redundancy sub-block or an even-numbered row redundancy sub-block for replacement if the damaged memory sub-block is an even-numbered row memory sub-block, wherein when the odd-numbered row redundancy sub-block is selected for replacement, the selection signal of the even-numbered row redundancy sub-block is low, one of the selection signals of the odd-numbered row redundancy sub-block is high (RDNSEL <1>, RDNSEL <3>, RDNSEL <5>, etc., the first logic signal is low, the second logic signal is high, the inner and outer side switching control signals are high, and the level of the bit line high voltage control signal applied to the selected odd-numbered row redundancy sub-block is opposite to the level of the high voltage control signal planned to be applied to the damaged memory sub-block; when an even row redundancy sub-block is selected for replacement, the selection signal of the even row redundancy sub-block is high (one of RDNSEL <0>, RDNSEL <2>, RDNSEL <4>, etc. is high), the selection signal of the odd row redundancy sub-block is low, the first logic signal is low, the second logic signal is low, the inside-outside switching control signal is low, and the level of the bit line high voltage control signal applied to the selected even row redundancy sub-block is the same as the level of the high voltage control signal intended to be applied to the damaged memory sub-block.
The following describes in detail the control circuit for repairing the flash memory according to the present embodiment with reference to fig. 1 and 2, in which an even-numbered row redundancy sub-block is selected for replacement repair when an odd-numbered row storage sub-block is damaged. For example, when the storage bit a' in the odd-numbered storage sub-block with a7=1 is damaged, the row direction sub-low address signal a <7> of the damaged storage sub-block is at a high level, and at this time, for the first logic module 10, the row direction sub-low address signal a <7> of the damaged storage sub-block is input to the first not gate I11, the output end of the first not gate I11 outputs a low level signal to an input end of the second not gate I02, because the even-numbered redundancy sub-block is selected for replacement repair, the selection signal of the even-numbered redundancy sub-block, for example, RDNSEL <0>, is at a high level, the high level signal is input to the first not gate I01, the output end of the first not gate I01 outputs a low level signal to the other input end of the second not gate I02, both input ends of the second not gate I02 receive a low level signal, the first logic signal output by the output end of the second not gate I02 is at a high level, and the first logic signal is transmitted to an input end of the fifth not gate I05; for the second logic module 20, the odd-numbered row redundancy sub-block selection signals such as RDNSEL <1>, RDNSEL <3>, RDNSEL <5>, etc. are all low, the low-level odd-numbered row redundancy sub-block selection signal is input to the third or gate I03, the output terminal of the third or gate I03 outputs a high-level signal to one input terminal of the fourth nor gate I04, meanwhile, the row-direction next-lower address signal a <7> of the damaged memory sub-block of the high level is input to the other input terminal of the fourth nor gate I04, both input terminals of the fourth nor gate I04 receive two high-level signals, the output terminal of the fourth nor gate I04 outputs a low-level second logic signal, and the second logic signal is transmitted to the other input terminal of the fifth nor gate I05; for the third logic module 30, the fifth nor gate I05 receives the first logic signal with a high level and the second logic signal with a low level, the output end of the fifth nor gate I05 outputs the low level signal, and the internal and external side switching control signal output by the output end of the second nor gate I12 is at a high level after the inversion of the second nor gate I12. When the memory bit a ' is to be stored, for example, the high voltage control signal scheduled to be applied to the damaged memory sub-block may control the application of a higher voltage (e.g., 0.8V) to the bit line BL0<0>, the application of a lower voltage (e.g., 0V) to the bit line BL1<0>, the odd-numbered row memory sub-block of a7=1 is not used after the memory bit a ' is damaged, at this time, the even-numbered row redundancy sub-block is selected for replacement, and the high-level inside and outside switching control signal outputted by the third logic module 30 is xored with the high-voltage control signal scheduled to be applied to the damaged memory sub-block to obtain the bit line high-voltage control signal applied to the selected even-numbered row redundancy sub-block, and the level of the obtained bit line high-voltage control signal applied to the selected even-numbered row redundancy sub-block is opposite to the level of the high-voltage control signal scheduled to be applied to the damaged memory sub-block, and the bit line high-voltage control signal applied to the selected even-numbered row redundancy sub-block is not applied to the bit line (e.g., 0V) corresponding to the bit line 0' is not shown in the memory sub-block BL1 (e.g., 0V) and the bit line BL1' is not shown in the memory sub-0 ') shown in the memory sub-block.
The control circuit for repairing the flash memory of the embodiment outputs an inner-outer exchange control signal through carrying out logic operation on the selection signal of the even-numbered row redundancy sub-block, the selection signal of the odd-numbered row redundancy sub-block and the row direction secondary low-order address signal of the damaged storage sub-block, and then carries out exclusive OR operation on the inner-outer exchange control signal and the high-voltage control signal which is scheduled to be applied to the damaged storage sub-block to obtain the bit line high-voltage control signal which is applied to the selected redundancy sub-block, so that the odd-numbered row redundancy sub-block and the even-numbered row redundancy sub-block can replace the damaged storage sub-block. More specifically, when the odd-numbered line storage sub-block is damaged, the odd-numbered line redundancy sub-block is selected for replacement, or when the even-numbered line storage sub-block is damaged, the internal and external exchange control signals and the high-voltage control signals scheduled to be applied to the damaged storage sub-block are subjected to exclusive OR operation, so that bit line high-voltage control signals with the same level as that of the high-voltage control signals scheduled to be applied to the damaged storage sub-block are obtained, and the bit line high-voltage control signals are applied to the selected redundancy sub-block, so that the selected redundancy sub-block can replace the damaged storage sub-block; and selecting an even-numbered row redundancy sub-block for replacement when the odd-numbered row storage sub-block is damaged or selecting an odd-numbered row redundancy sub-block for replacement when the even-numbered row storage sub-block is damaged, performing exclusive OR operation on the inner and outer side exchange control signals and the high-voltage control signals scheduled to be applied to the damaged storage sub-block to obtain bit line high-voltage control signals which are opposite in level to the high-voltage control signals scheduled to be applied to the damaged storage sub-block and are applied to the selected redundancy sub-block, wherein the bit line high-voltage control signals applied to the selected redundancy sub-block enable the selected redundancy sub-block to replace the damaged storage sub-block. Therefore, the control circuit for repairing the flash memory of the embodiment can enable the flash memory to be replaced and repaired by using the redundant subblocks of even lines when the storage subblocks are damaged, and also can be replaced and repaired by using the redundant subblocks of odd lines, so that the use of the redundant subblocks is not limited, the utilization rate of the redundant subblocks is improved, and the storage performance of the flash memory is improved.
The embodiment also relates to a method for repairing a flash memory, the method for repairing a flash memory being used for providing a bit line high voltage control signal to a replaced redundancy subblock when a storage subblock is damaged, the storage subblock comprises an odd-line storage subblock and an even-line storage subblock, the inner storage bits of a group of adjacent odd-line storage subblocks and even-line storage subblocks are connected with a same bit line, the outer storage bits are connected with two bit lines in two columns, each bit line is controlled by the bit line high voltage control signal, the redundancy subblock comprises an odd-line redundancy subblock and an even-line redundancy subblock, the method comprises the steps of obtaining a row direction secondary low bit address signal of the damaged storage subblock and a bit line high voltage control signal planned to be applied to the damaged storage subblock, selecting a redundancy subblock as the replacement of the damaged storage subblock, the redundancy subblock is an odd-line redundancy subblock or an even-line redundancy subblock, then, carrying out logic operation on the selection signals of a plurality of even-numbered row redundancy sub-blocks and the row direction sub-low address signals of the damaged storage sub-blocks to obtain first logic signals, carrying out logic operation on the selection signals of a plurality of odd-numbered row redundancy sub-blocks and the row direction sub-low address signals of the damaged storage sub-blocks to obtain second logic signals, wherein the selection signals of the redundancy sub-blocks used for replacing are included in the selection signals of the even-numbered row redundancy sub-blocks or the odd-numbered row redundancy sub-blocks, carrying out logic operation on the first logic signals and the second logic signals and outputting inner and outer side exchange control signals, carrying out exclusive OR operation on the inner and outer side exchange control signals and the high voltage control signals scheduled to be applied to the damaged storage sub-blocks to obtain bit line high voltage control signals applied to the redundancy sub-blocks used for replacing, so that the redundancy subblocks for replacement operate in a controlled manner as the defective storage subblocks.
In this embodiment, if the damaged memory subblock is an odd-line memory subblock, when the odd-line redundancy subblock is selected for replacement, the level of the bit line high-voltage control signal applied to the selected odd-line redundancy subblock is the same as the level of the high-voltage control signal scheduled to be applied to the damaged memory subblock, or when the even-line redundancy subblock is selected for replacement, the level of the bit line high-voltage control signal applied to the selected even-line redundancy subblock is opposite to the level of the high-voltage control signal scheduled to be applied to the damaged memory subblock; if the damaged memory subblock is an even-line memory subblock, when an odd-line redundancy subblock is selected for replacement, the level of the bit line high-voltage control signal applied to the selected odd-line redundancy subblock is opposite to the level of the high-voltage control signal intended for the damaged memory subblock, or when an even-line redundancy subblock is selected for replacement, the level of the bit line high-voltage control signal applied to the selected even-line redundancy subblock is the same as the level of the high-voltage control signal intended for the damaged memory subblock.
The method for repairing the flash memory is applied to the control circuit for repairing the flash memory, so that when the storage sub-blocks of the flash memory are damaged, the flash memory can be replaced and repaired by using even-numbered row redundancy sub-blocks and also can be replaced and repaired by using odd-numbered row redundancy sub-blocks, the use of the redundancy sub-blocks is not limited, the utilization rate of the redundancy sub-blocks is improved, and the storage performance of the flash memory is improved.
The foregoing description is only illustrative of the preferred embodiments of the present invention, and is not intended to limit the scope of the claims, and any person skilled in the art may make any possible variations and modifications to the technical solution of the present invention using the method and technical content disclosed above without departing from the spirit and scope of the invention, so any simple modification, equivalent variation and modification made to the above embodiments according to the technical matter of the present invention fall within the scope of the technical solution of the present invention.
Claims (9)
1. A control circuit for repairing a flash memory for providing a bit line high voltage control signal to a replaced redundancy subblock when a memory subblock is damaged, wherein the memory subblock comprises an odd row memory subblock and an even row memory subblock, wherein inner memory bits of a group of adjacent odd row memory subblocks and even row memory subblocks are connected to a same bit line and outer memory bits are connected to two bit lines in two columns, each bit line is controlled by the bit line high voltage control signal, the redundancy subblock comprises an odd row redundancy subblock and an even row redundancy subblock, the control circuit comprising:
the input end of the first logic module is connected with selection signals of a plurality of even-numbered row redundancy sub-blocks and row direction secondary low-order address signals of the damaged storage sub-blocks, and a first logic signal is output through logic operation; the first logic module comprises a first NOR gate, a second NOR gate and a first NOR gate, wherein a selection signal of the even-numbered row redundancy sub-block is input from an input port of the first NOR gate, an output port of the first NOR gate is connected with an input port of the second NOR gate, a row-direction next-lower address signal of the damaged storage sub-block is input from the input port of the first NOR gate, an output port of the first NOR gate is connected with another input port of the second NOR gate, an output port of the second NOR gate is connected with an input port of a third logic module, and an output port of the second NOR gate is connected with an output port of the third logic module to output the first logic signal;
the input end of the second logic module is connected with selection signals of a plurality of odd-numbered row redundancy sub-blocks and row direction secondary low-order address signals of the damaged storage sub-blocks, and a second logic signal is output through logic operation;
and the two input ends of the third logic module are respectively connected with the output end of the first logic module and the output end of the second logic module, the third logic module is used for carrying out logic operation on the first logic signal and the second logic signal and outputting an inside-outside exchange control signal, and the inside-outside exchange control signal is used for carrying out exclusive OR operation on the inside-outside exchange control signal and a high-voltage control signal scheduled to be applied to a damaged storage subblock so as to obtain a bit line high-voltage control signal applied to a selected redundancy subblock, so that the odd-line redundancy subblock and the even-line redundancy subblock can both replace the damaged storage subblock.
2. The control circuit for repairing a flash memory according to claim 1, wherein if the damaged memory subblock is an odd-numbered row memory subblock, the row direction sub-lower address signal is high, when the odd-numbered row redundancy subblock is selected for replacement, the selection signal of the even-numbered row redundancy subblock is low, the selection signal of the odd-numbered row redundancy subblock is high, the first logic signal is low, the second logic signal is low, the inside-outside switching control signal is low, and the level of the bit line high-voltage control signal applied to the selected odd-numbered row redundancy subblock is the same as the level of the high-voltage control signal intended to be applied to the damaged memory subblock.
3. The control circuit for repairing a flash memory according to claim 1, wherein if the damaged memory subblock is an odd-numbered row memory subblock, the row direction sub-lower address signal is high, when an even-numbered row redundancy subblock is selected for replacement, the selection signal of the even-numbered row redundancy subblock is high, the selection signal of the odd-numbered row redundancy subblock is low, the first logic signal is high, the second logic signal is low, the inside-outside switching control signal is high, and the level of the bit line high-voltage control signal applied to the selected even-numbered row redundancy subblock is opposite to the level of the high-voltage control signal intended to be applied to the damaged memory subblock.
4. The control circuit for repairing a flash memory according to claim 1, wherein if the defective memory subblock is an even-numbered row memory subblock, the row-direction sub-lower address signal is low, when an odd-numbered row redundancy subblock is selected for replacement, the selection signal of the even-numbered row redundancy subblock is low, the selection signal of the odd-numbered row redundancy subblock is high, the first logic signal is low, the second logic signal is high, the inside-outside switching control signal is high, and the level of the bit line high-voltage control signal applied to the selected odd-numbered row redundancy subblock is opposite to the level of the high-voltage control signal intended to be applied to the defective memory subblock.
5. The control circuit for repairing a flash memory according to claim 1, wherein if the damaged memory subblock is an even-numbered row memory subblock, the row-direction sub-lower address signal is low, when the even-numbered row redundancy subblock is selected for replacement, the selection signal of the even-numbered row redundancy subblock is high, the selection signal of the odd-numbered row redundancy subblock is low, the first logic signal is low, the second logic signal is low, the inside-outside switching control signal is low, and the level of the bit line high-voltage control signal applied to the selected even-numbered row redundancy subblock is the same as the level of the high-voltage control signal intended to be applied to the damaged memory subblock.
6. The control circuit for repairing flash memory according to any one of claims 1 to 5, wherein the second logic module comprises a third nor gate and a fourth nor gate, the selection signal of the odd-numbered row redundancy sub-block is input from an input port of the third nor gate, an output port of the third nor gate is connected to an input port of the fourth nor gate, the row-direction next lower address signal of the damaged memory sub-block is input from another input port of the fourth nor gate, an output port of the fourth nor gate is connected to another input port of the third logic module, and an output port of the fourth nor gate connected to the third logic module outputs the second logic signal.
7. The control circuit for repairing flash memory according to any one of claims 1 to 5, wherein the third logic module comprises a fifth nor gate and a second nor gate, two input ports of the fifth nor gate are respectively connected with output ports of the first logic module and the second logic module and used for receiving the first logic signal and the second logic signal, and an output port of the fifth nor gate is connected to an input port of the second nor gate, and an output port of the second nor gate outputs an internal-external exchange control signal.
8. A method of repairing a flash memory, characterized in that it is applied to a control circuit of repairing a flash memory according to any one of claims 1 to 7, for providing a bit line high voltage control signal to a replaced redundancy subblock when a storage subblock is damaged, the storage subblock including an odd row storage subblock and an even row storage subblock, an inner storage bit of a group of adjacent odd row storage subblocks and even row storage subblocks being connected to a same bit line and an outer storage bit being connected to two bit lines in two columns, each of the bit lines being controlled by the bit line high voltage control signal, the redundancy subblock including an odd row redundancy subblock and an even row redundancy subblock, the method comprising:
acquiring a row direction next lower address signal of a damaged storage sub-block and a bit line high voltage control signal planned to be applied to the damaged storage sub-block;
selecting a redundant subblock as a replacement for the damaged storage subblock, the redundant subblock being an odd-line redundant subblock or an even-line redundant subblock;
performing logic operation on the selection signals of the even-numbered row redundancy sub-blocks and the row-direction sub-low address signals of the damaged storage sub-blocks to obtain first logic signals, and performing logic operation on the selection signals of the odd-numbered row redundancy sub-blocks and the row-direction sub-low address signals of the damaged storage sub-blocks to obtain second logic signals, wherein the selection signals of the redundancy sub-blocks used for replacing are included in the selection signals of the even-numbered row redundancy sub-blocks or the odd-numbered row redundancy sub-blocks;
performing logic operation on the first logic signal and the second logic signal and outputting an inside-outside exchange control signal; and
exclusive-or-operating the inner and outer side switching control signals with the high voltage control signals scheduled to be applied to the damaged memory subblocks to obtain bit line high voltage control signals applied to the redundancy subblocks for replacement ， So that the redundancy subblocks for replacement operate in a controlled manner as the defective storage subblocks.
9. The method of repairing a flash memory according to claim 8, wherein if the damaged memory subblock is an odd-line memory subblock, when the odd-line redundancy subblock is selected for replacement, a level of a bit line high voltage control signal applied to the selected odd-line redundancy subblock is the same as a level of a high voltage control signal intended to be applied to the damaged memory subblock, or when the even-line redundancy subblock is selected for replacement, a level of a bit line high voltage control signal applied to the selected even-line redundancy subblock is opposite to a level of a high voltage control signal intended to be applied to the damaged memory subblock; if the damaged memory subblock is an even-line memory subblock, when an odd-line redundancy subblock is selected for replacement, the level of the bit line high-voltage control signal applied to the selected odd-line redundancy subblock is opposite to the level of the high-voltage control signal intended for the damaged memory subblock, or when an even-line redundancy subblock is selected for replacement, the level of the bit line high-voltage control signal applied to the selected even-line redundancy subblock is the same as the level of the high-voltage control signal intended for the damaged memory subblock.
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| US6191986B1 (en) * | 1999-08-11 | 2001-02-20 | Mosel Vitelic Inc. | Memory device with redundancy arrays |
| CN101377959A (en) * | 2007-08-30 | 2009-03-04 | 晶豪科技股份有限公司 | Selection method and device for redundant bit line repair |
| CN108091368A (en) * | 2018-01-12 | 2018-05-29 | 上海华虹宏力半导体制造有限公司 | A kind of control circuit and its redundant repair method for redundancy reparation |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6191986B1 (en) * | 1999-08-11 | 2001-02-20 | Mosel Vitelic Inc. | Memory device with redundancy arrays |
| CN101377959A (en) * | 2007-08-30 | 2009-03-04 | 晶豪科技股份有限公司 | Selection method and device for redundant bit line repair |
| CN108091368A (en) * | 2018-01-12 | 2018-05-29 | 上海华虹宏力半导体制造有限公司 | A kind of control circuit and its redundant repair method for redundancy reparation |
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