CN111505993A - Sequential control circuit - Google Patents

Abstract

The present invention provides a sequence control circuit, which includes: a power-on delay module, a reference voltage generation module and a control sequence generation module; an input end of the power-on delay module is used for connecting with a power input end, and the power-on delay module The output end of the delay module is connected with the control sequence generation module to output the first voltage to the control sequence generation module; the input end of the reference voltage generation module is used for connecting with the power input end, the reference The output end of the voltage generation module is connected to the control sequence generation module to output a second voltage to the control sequence generation module; the control sequence generation module outputs under the driving of the first voltage and the second voltage a timing control signal; wherein, the timing control circuit is configured to, after the power input terminal is powered on, the reference voltage generation module outputs the second voltage before the power-on delay module outputs the first voltage a voltage.

Description

timing control circuit

technical field

The invention relates to the technical field of medical equipment, in particular to a timing control circuit.

Background technique

MRI (Magnetic Resonance Imaging) systems include various complex electronic components or single boards, and circuits in such electronic components or single boards are usually powered by multiple channels of different power supply voltages. In addition, the component or single board needs to control the power-on and power-on sequence of the multi-channel power supply voltage, so as to work normally or more stably and reliably after power-on. For example, some high-end processing chips powered by multiple power supply voltages have strict power-on and power-on sequence requirements. If the power-on and power-on sequence of each power supply voltage does not meet the requirements, the chip may not work normally or be permanently damaged.

In the prior art, there are many solutions for controlling the power-on or power-off sequence of the multi-channel power supply voltage of components or single boards, mainly including the following:

A. Use a dedicated power sequence control chip to achieve this. This type of chip is usually a dedicated chip for each chip manufacturer, with high cost, poor scalability, and poor substitutability of the solution. If the chip is out of production, the design must be changed to replace it;

B. The power sequence control is realized through programmable logic devices. Such methods are expensive. In many components or boards without programmable logic devices, if this solution is used, the cost is too high;

C. Control the enable signal of the power supply after powering on the Pgood (power output normal signal) of the power supply first. This method cannot realize the power-off control, and at the same time, this scheme cannot be used for many power supply chips without Pgood signal;

D. By connecting switches, such as field effect transistors, in series on the voltage output links of various power modules, the power-on and power-on sequence of the power supply is controlled by controlling the order in which the switches are turned on. Since the switches themselves have internal resistance, when a large current is passed , it will bring turn-on loss, which will not only cause additional voltage drop, but also bring additional heat to the board.

E. There are also some implementation schemes. It is necessary to provide a backup power supply (different from the main input power supply) to realize the priority power supply of the power supply sequence control circuit, which increases the number of input power supplies of components or single boards.

However, the above-mentioned solutions have more or less problems such as complicated design, high cost, limitation, high loss or low reliability.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a timing control circuit to solve one or more problems in the prior art.

In order to solve the above technical problems, the present invention provides a timing control circuit, which includes: a power-on delay module, a reference voltage generating module and a control timing generating module;

The input end of the power-on delay module is connected to the power input end, and the output end of the power-on delay module is connected to the control sequence generation module, so as to output the first voltage to the control sequence generation module;

The input end of the reference voltage generation module is used for connecting with the power input end, and the output end of the reference voltage generation module is connected with the control sequence generation module, so as to output the second voltage to the control sequence generation module;

The control timing generation module outputs timing control signals driven by the first voltage and the second voltage;

The timing control circuit is configured such that after the power input terminal is powered on, the reference voltage generating module outputs the second voltage before the power-on delay module outputs the first voltage.

Optionally, the sequence control circuit further includes a power-off hold module, the power-off hold module is configured to be connected to the power input terminal and configured to provide the power-on hold module within a predetermined time after the power input terminal is powered off. The electrical delay module and the reference voltage generating module supply power.

Optionally, the control timing generation module includes at least two timing generation units, the first input terminal of each timing generation unit is connected to the output terminal of the reference voltage generation module, and the output terminal of each timing generation unit is The second input terminal is connected to the output terminal of the power-on delay module, and the output terminal of each timing generation unit is used for outputting a timing control signal.

Optionally, the timing generation unit includes: a first comparator, a first resistor, a second resistor and a first capacitor;

The first input end of the first comparator is connected to the output end of the power-on delay module through the first resistor, and the first input end of the first comparator is also grounded through the second resistor, the first capacitor is connected in parallel with both ends of the second resistor;

The output end of the reference voltage generating module supplies power to the first comparator;

The first comparator is configured such that when the voltage of the first input terminal of the first comparator reaches a first threshold value, the output terminal of the first comparator outputs a first predetermined signal.

Optionally, the control sequence generation module further includes a compensation unit, and the compensation unit includes: a second comparator, a third resistor, a fourth resistor, and an AND gate;

The first input terminal of the second comparator is connected to the power input terminal through the third resistor, and the first input terminal of the second comparator is also grounded through the fourth resistor;

The output end of the reference voltage generating module supplies power to the second comparator;

The second comparator is configured such that when the voltage of the first input terminal of the second comparator reaches a second threshold value, the output terminal of the second comparator outputs a second predetermined signal;

Input terminals of the AND gate are respectively connected to the output terminal of the first comparator and the output terminal of the second comparator, and the output terminal of the AND gate is configured to output the timing control signal.

Optionally, the timing generation unit further includes: a fifth resistor and a sixth resistor, the second input end of the first comparator is connected to the output end of the reference voltage generating module through the fifth resistor, so The second input terminal of the first comparator is also grounded through the sixth resistor, and the first threshold is determined by the resistance ratio of the fifth resistor and the sixth resistor; and/or, the compensation unit It also includes: a seventh resistor and an eighth resistor, the second input end of the second comparator is connected to the output end of the reference voltage generating module through the seventh resistor, and the second input end of the second comparator The terminal is also grounded through the eighth resistor, and the second threshold is determined by the resistance ratio of the seventh resistor and the eighth resistor.

Optionally, the timing generation unit further includes: a ninth resistor and a tenth resistor, the output end of the first comparator is grounded through the ninth resistor and the tenth resistor arranged in sequence, and the first The voltage of the predetermined signal is determined by the resistance ratio of the ninth resistor and the tenth resistor; and/or the compensation unit further includes: an eleventh resistor and a twelfth resistor, and the second comparator The output terminal is grounded through the eleventh resistor and the twelfth resistor arranged in sequence, and the second predetermined signal is connected to the connection point of the eleventh resistor and the twelfth resistor.

Optionally, the reference voltage generating module includes a low dropout linear regulator.

Optionally, the power-on delay module includes: a thirteenth resistor, a fourteenth resistor, a second capacitor and a transistor;

The control terminal of the transistor is connected to the power input terminal through the thirteenth resistor, the control terminal of the transistor is also grounded through the fourteenth resistor, and the second capacitor is connected in parallel with the thirteenth resistor Both ends of the transistor; the input end of the transistor is connected to the power supply input end, and the output end of the transistor is configured as the output end of the power-on delay module; the transistor is configured as the control end of the control end Turning on when the voltage or control current reaches a third threshold, wherein the third threshold is determined by the resistance ratio of the thirteenth resistor and the fourteenth resistor.

Optionally, the transistor includes a MOS transistor, and the power-on delay module further includes a diode, and the diode is connected in parallel to both ends of the second capacitor.

In the sequence control circuit provided by the present invention, the sequence control circuit includes a power-on delay module, a reference voltage generation module and a control sequence generation module; the input end of the power-on delay module is used for connecting with the power input end, The output end of the power-on delay module is connected to the control sequence generation module to output a first voltage to the control sequence generation module; the input end of the reference voltage generation module is used to connect to the power input end , the output end of the reference voltage generation module is connected to the control sequence generation module to output a second voltage to the control sequence generation module; the control sequence generation module is at the first voltage and the second voltage The timing control circuit is configured to output the timing control signal under the driving of the power source; wherein the timing control circuit is configured such that after the power input terminal is powered on, the reference voltage generation module outputs the second voltage before the power-on delay module The first voltage is output. With this configuration, the control sequence generation module can output sequence control signals driven by the first voltage and the second voltage, and only depends on a single input power supply, that is, no backup power supply is required, and the number of power supplies for components or boards is not increased. Because the second voltage is output before the first voltage, the control sequence generation module can work reliably and output the sequence control signal, and the solution has high reliability, simple circuit and low cost.

Description of drawings

Those of ordinary skill in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention. in:

1 is a schematic block diagram of a timing control circuit provided by a preferred embodiment of the present invention;

2 is a schematic diagram of a power-on delay module and a power-off hold module provided by a preferred embodiment of the present invention;

3 is a schematic diagram of a reference voltage generating module provided by a preferred embodiment of the present invention;

4 is a schematic diagram of a control sequence generation module provided by a preferred embodiment of the present invention;

5 is a timing diagram of a timing control circuit provided by a preferred embodiment of the present invention;

6 is a timing relationship diagram of a timing control circuit provided by a preferred embodiment of the present invention, wherein PCTL1 fails to output successfully when powered off;

7 is a schematic diagram of a control sequence generation module provided by a preferred embodiment of the present invention, which includes a compensation unit;

FIG. 8 is a timing relationship diagram of a timing control circuit provided by a preferred embodiment of the present invention, wherein the PCTL1 can be successfully output when powered off by the action of the compensation unit.

In the attached picture:

10-power input terminal; 11-power-off hold module; 12-power-on delay module; 13-reference voltage generation module; 14-control sequence generation module; 15-power conversion module.

Detailed ways

In order to make the objects, advantages and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clearly assist the purpose of explaining the embodiments of the present invention. Furthermore, the structures shown in the drawings are often part of the actual structure. In particular, each drawing needs to show different emphases, and sometimes different scales are used.

As used in this specification, the singular forms "a," "an," and "the" include plural referents unless the content clearly dictates otherwise. As used in this specification, the term "or" is generally employed in its sense including "and/or" unless the content clearly dictates otherwise.

The present invention provides a timing control circuit to solve one or more of the problems in the prior art, such as complicated design, high cost, limitation, high loss or low reliability of the timing control circuit.

The following description is made with reference to the accompanying drawings.

Please refer to FIG. 1 to FIG. 8, wherein, FIG. 1 is a schematic block diagram of a timing control circuit provided by a preferred embodiment of the present invention, and FIG. 2 is a power-on delay module and a power-off hold module provided by a preferred embodiment of the present invention. Schematic diagram, FIG. 3 is a schematic diagram of a reference voltage generation module provided by a preferred embodiment of the present invention, FIG. 4 is a schematic diagram of a control sequence generation module provided by a preferred embodiment of the present invention, and FIG. 5 is a timing sequence provided by a preferred embodiment of the present invention. The timing relationship diagram of the control circuit, FIG. 6 is the timing relationship diagram of the timing control circuit provided by a preferred embodiment of the present invention, wherein PCTL1 fails to output when powered off, and FIG. 7 is the control sequence generation provided by a preferred embodiment of the present invention. A schematic diagram of a module including a compensation unit. FIG. 8 is a timing diagram of a timing control circuit provided by a preferred embodiment of the present invention, wherein the function of the compensation unit enables PCTL1 to output successfully when powered off.

As shown in FIG. 1, a preferred embodiment of the present invention provides a timing control circuit, which includes: a power-on delay module 12, a reference voltage generation module 13, and a control timing generation module 14; The input terminal is used to connect with the power input terminal 10, the output terminal of the power-on delay module 12 is connected to the control sequence generation module 14, and the output terminal of the power-on delay module 12 is used to send the control sequence The generation module 14 outputs the first voltage; the input terminal of the reference voltage generation module 13 is used to connect with the power input terminal 10 , and the output terminal of the reference voltage generation module 13 is connected to the control sequence generation module 14 . The output end of the reference voltage generation module 13 is used to output the second voltage to the control sequence generation module 14; the control sequence generation module 14 outputs a timing control signal driven by the first voltage and the second voltage ; wherein, the timing control circuit is configured such that after the power input terminal 10 is powered on, the reference voltage generation module 13 outputs the second voltage before the power-on delay module 12 outputs the first voltage . Optionally, the output end of the control sequence generation module 14 is used to connect with a power conversion module 15, and the sequence control signal output by the control sequence generation module 14 is used to control the power conversion module 15. The power conversion module 15 may be a low dropout voltage. Linear regulated power supply LDO or DC switching power supply DC-DC.

In this configuration, the control sequence generation module 14 can output the sequence control signal driven by the first voltage and the second voltage, and only depends on a single input power supply (ie, the power input terminal 10 ), without providing a backup power supply, without adding components or single The number of power supplies for the board. Since the second voltage is output before the first voltage, the control sequence generation module 14 can work reliably and output the sequence control signal, and the solution has high reliability, simple circuit and low cost.

Preferably, the sequence control circuit further includes a power-off hold module 11, the power-off hold module 11 is used for connecting with the power input terminal 10 (VIN_EXT) and used for a predetermined time after the power input terminal 10 is powered off Inside, the power-on delay module 12 and the reference voltage generating module 13 are powered. The main function of the power-off hold module 11 is to extend the power-off time of the external main input power supply 10 to ensure that the power conversion module 15 requiring sequence control is powered off before the external main input power supply 10 is completely powered off. Optionally, the power-off hold module 11 includes at least one capacitor, and the capacitance of the capacitor is generally larger. Referring to FIG. 2 , in an exemplary embodiment, the power-off hold module 11 includes a capacitor C1 , a capacitor C2 and a capacitor C3 , the three capacitors are connected in parallel, one end is connected to the power input terminal 10 (VIN_EXT), and the other end is grounded. In practice, the power-off delay time can be adjusted by adjusting the total capacitance value. In theory, the power-off delay time Δt1=k*(C1+C2+C3)/P; where k is a constant, and P is the component or board load during power-off required power. It can be understood that those skilled in the art can adjust the number and value of the capacitors according to the actual situation, so as to obtain a suitable power-off delay time.

Please continue to refer to FIG. 2 , the power-on delay module 12 includes: a thirteenth resistor R1 , a fourteenth resistor R2 , a second capacitor C4 and a transistor Q1 . The control terminal of the transistor Q1 is connected to the power input terminal VIN_EXT through the thirteenth resistor R1, the control terminal of the transistor Q1 is also grounded through the fourteenth resistor R2, and the second capacitor C4 is connected in parallel with the power supply input terminal VIN_EXT. Both ends of the thirteenth resistor R1; the input end of the transistor Q1 is connected to the power input end VIN_EXT, and the output end of the transistor Q1 is configured as the output end of the power-on delay module 12 (which Mainly used to output the first voltage VIN); the transistor Q1 is configured to be turned on when the control voltage or control current of the control terminal reaches a third threshold, wherein the third threshold is determined by the thirteenth resistor R1 and The resistance ratio of the fourteenth resistor R2 is determined. The main function of the power-on delay module 12 is to make the power input terminal VIN_EXT supply power to other components or boards after a delay. With this configuration, the reference voltage generation module 13 can preferentially generate the second voltage VREF required by the control timing generation module 14 . The delay time of the first voltage VIN relative to the power-on of the power input terminal VIN_EXT can be adjusted through R2 and C4. Specifically, the delay time of VIN relative to VIN_EXT Δt2=k*C4*R2, where k is a constant. The delay time Δt2 only needs to ensure that the second voltage VREF is ready before the control sequence generation module 14 works normally. The ratio of R1 to R2 determines the third threshold at which Q1 turns on. In a preferred embodiment, the transistor Q1 includes a MOS transistor, the power-on delay module further includes a diode D1, and the diode D1 is connected in parallel to both ends of the second capacitor C4. The conduction of the MOS tube is mainly controlled by the gate voltage. At this time, the third threshold is the turn-on voltage of the MOS tube. The diode D1 can be a voltage regulator tube or a TVS tube to protect the gate and source of the MOS tube. Of course, in other embodiments, the transistor Q1 may also include a triode, which is mainly turned on by current control. At this time, the third threshold is the on-current of the triode. Those skilled in the art can make appropriate modifications according to the actual situation. Invention is not limited to this.

Please refer to FIG. 3 , optionally, the reference voltage generating module 13 includes a low dropout linear regulator LDO, the input end of the low dropout linear regulator LDO is connected to the power input end 10 (VIN_EXT), and the other end is configured It is the output terminal of the reference voltage generating module 13 for outputting the second voltage VREF. Of course, in practice, the reference voltage generating module 13 may also include other commonly used DC-DC circuits, and is not limited to the low dropout linear regulator LDO. It can be understood that the second voltage VREF is lower than the first voltage VIN.

Preferably, the control timing generation module 14 includes at least two timing generation units, the first input terminal of each timing generation unit is connected to the output terminal of the reference voltage generation module 13, and each timing generation unit The second input terminal of 1 is connected to the output terminal of the power-on delay module 12 , and the output terminal of each timing generation unit is used to output a timing control signal.

Referring to FIG. 4 , in an exemplary embodiment, the control timing generation module 14 includes two timing generation units 20 and 21 , and the first timing generation unit 20 is used as an example for description below. The timing generation unit 20 includes a first comparator U1, a first resistor R3, a second resistor R4 and a first capacitor C5. The first input end U1A of the first comparator U1 is connected to the upper The output end of the electrical delay module 12 is connected, the first input end U1A of the first comparator U1 is also grounded through the second resistor R4, and the first capacitor C5 is connected in parallel with both ends of the second resistor R4 ; The output end of the reference voltage generation module 13 supplies power to the first comparator U1; the first comparator U1 is configured such that the voltage of the first input end U1A of the first comparator U1 reaches the first When the threshold value is reached, the output terminal of the first comparator U1 outputs a first predetermined signal, and the first predetermined signal is configured as a timing control signal PCTL1. For example, the first threshold can be a reference voltage. Further, the reference voltage can be obtained by dividing the second voltage VREF. Optionally, the timing generation unit further includes: a fifth resistor R5 and a sixth resistor R6, the first The second input terminal U1B of a comparator U1 is connected to the output terminal of the reference voltage generating module 13 through the fifth resistor R5, and the second input terminal U1B of the first comparator U1 is also connected through the sixth resistor R6 is grounded, and the first threshold is determined by the resistance ratio of the fifth resistor R5 and the sixth resistor R6. Since the first voltage VIN output by the output terminal of the power-on delay module 12 is greater than the second voltage VREF output by the output terminal of the reference voltage generating module 13, the first input terminal U1A of the first comparator U1 is set as The positive terminal of the first comparator U1 and the second input terminal U1B are set as the negative terminal of the first comparator U1. The first input terminal U1A is used to connect the voltage signal of the first voltage VIN divided by R3 and R4. After the first voltage VIN is divided by R3 and R4, the output delay of PCTL1 can be adjusted through R3 and C5. Specifically, The output delay time of PCTL1 is proportional to the resistance-capacitance product value of R3 and C5. Optionally, the output terminal of the reference voltage generation module 13 supplies power to the first comparator U1, and a decoupling capacitor C6 can also be set here. One end of the decoupling capacitor C6 is connected to the output terminal of the reference voltage generation module 13, and the other end is grounded. . Those skilled in the art can select an appropriate decoupling capacitor C6 according to the specifications of the first comparator U1.

Optionally, the timing generation unit 20 further includes: a ninth resistor R7 and a tenth resistor R8, and the output end of the first comparator U1 is arranged through the ninth resistor R7 and the tenth resistor R8 in sequence. Grounding, the voltage of the first predetermined signal is connected to the connection point of the ninth resistor R7 and the tenth resistor R8. It can be understood that the voltage of the first predetermined signal is determined by the ratio of the ninth resistor R7 and the tenth resistor R8 to generate an enable control signal that meets the level required by the power conversion module 15 .

Preferably, the circuit structure of the second timing generation unit 21 is similar to that of the first timing generation unit 20. After the first voltage VIN is divided by R9 and R10, the output delay of PCTL2 can be adjusted through R9 and C7. Specifically, the output delay time of PCTL2 is proportional to the value of the resistance-capacitance product of R9 and C7. The arrangement of the two timing generating units 20 and 21 can output at least two timing control signals. It can be understood that those skilled in the art can set a larger number of timing generation units according to actual needs. When there are N (N is a natural number) timing generation units, they can output N channels of timing control signals PCTL1, PCTL2... PCTLN.

The following describes the timing relationship of the timing control circuit provided by this embodiment with reference to FIG. 5 .

In the power-on stage: the external power input terminal VIN_EXT is powered on for the first time, and the second voltage VREF is powered on for the second time (the second voltage VREF rises with the rise of VIN_EXT in the initial stage, and when VIN_EXT reaches the predetermined voltage VT, the first The output of the two voltages VREF is normal and maintains a stable voltage), after a delay of Δt2, the first voltage VIN is powered on at the third time, and the timing control signals PCTL1, PCTL2, ... PCTLN are set after the fourth time according to the timing generation units. The delays of , are set in sequence, so as to drive the various power sources of the power conversion module 15 to be powered on in sequence.

In the power-off stage: the external power input terminal VIN_EXT is powered off at the fifth time, the first voltage VIN can be approximately considered to be powered off at the same time as VIN_EXT, and the timing control signals PCTLN...PCTL2, PCTL1 are set to zero in turn to drive the power conversion module 15 Power off the circuits one by one. Wherein, after the external power input terminal VIN_EXT is powered off, the power-off holding module 11 can continue to supply power to the power-on delay module 12 and the reference voltage generating module 13, and the voltage of VIN_EXT gradually decreases at this time. When the voltage to VIN_EXT drops below the predetermined voltage VT, the second voltage VREF starts to power down. Before the second voltage VREF is powered off, all the power sources of the power conversion module 15 that need to be powered off sequence control have been powered off, that is, all the sequence generation units have completed the output of power off and reset to zero. The sequence control signals PCTL1 and PCTL2 ... PCTLN are all set to zero.

Referring to FIG. 6 , in some other embodiments, if the delay between the timing control signals is relatively large, it may cause that when the second voltage VREF starts to be powered down, some timing generation units have not completed the power down setting. If the output is zero, at this time, the power of the last channel or channels of the power conversion module 15 cannot be powered off in sequence according to the set sequence, which will cause problems. To this end, this embodiment also provides a control sequence generation module provided with a compensation unit to solve the above problem.

Please refer to FIG. 7 , in conjunction with FIG. 6 , in an exemplary embodiment, the first timing generation unit 20 is used as an example for description. In the timing relationship diagram shown in FIG. 6 , VN in FIG. 6 is the power-off threshold voltage of each compensation circuit, N is a natural number, and satisfies VN>...>V2>V1>VT. When the second voltage VREF starts to be powered off, the PCTL1 of the timing generation unit 20 fails to output successfully (the dotted line in the figure). Therefore, the control timing generation module 14 further includes a compensation unit 30, and the compensation unit 30 includes: a first Two comparators U3, a third resistor R21, a fourth resistor R22 and an AND gate U4; the first input end U3A of the second comparator U3 is connected to the power supply input end 10 through the third resistor R21, and the The first input end U3A of the second comparator U3 is also grounded through the fourth resistor R22; the output end of the reference voltage generating module 13 supplies power to the second comparator U3; the second comparator U3 is configured Therefore, when the voltage of the first input terminal U3A of the second comparator U3 reaches the second threshold, the output terminal of the second comparator U3 outputs the second predetermined signal PCTL1B; the input terminals of the AND gate U4 are respectively connected with The output terminal of the first comparator U1 is connected to the output terminal of the second comparator U3, and the output terminal of the AND gate U4 is configured to output the timing control signal PCTL1. Further, the compensation unit 30 further includes: a seventh resistor R23 and an eighth resistor R24, the second input end U3B of the second comparator U3 communicates with the reference voltage generating module 13 via the seventh resistor R23 The output terminal is connected, the second input terminal U3B of the second comparator U3 is also grounded through the eighth resistor R24, and the second threshold value is determined by the resistance ratio of the seventh resistor R23 and the eighth resistor R24 Sure. Further, the compensation unit 30 further includes: an eleventh resistor R25 and a twelfth resistor R26, and the output end of the second comparator U3 is arranged through the eleventh resistor R25 and the tenth resistor R25 in sequence. The second resistor R26 is grounded, and the second predetermined signal PCTL1B is connected to the connection point of the eleventh resistor R25 and the twelfth resistor R26. The specific circuit structure and principle of the comparator part of the compensation unit 30 are similar to those of the sequence generation unit 20. Please refer to the above description for the sequence generation unit 20, except that the first input end U3A is directly connected to the power supply through the voltage division of R21 and R22. Input 10 is connected. Since the AND gate U4 of the compensation unit 30 is connected to the output end of the timing generation unit 20 , the output end of the timing generation unit 20 does not directly output the timing control signal to the power conversion module 15 . Therefore, when the control sequence of the compensation unit 30 is provided In the generating module 14, the signal output by the output terminal of the timing generating unit 20 is defined as the first predetermined signal PCTL1A. It should be understood that the second threshold value of the compensation unit 30 is determined by R23 and R24, and it is not limited that it must be satisfied at the same time as the first threshold value of the timing generation unit 20 is determined by R3 and R4, or the second threshold value is determined by R23 and R24, but The first threshold is determined by other reference voltages; in the same way, the second predetermined signal is connected by the connection point of R25 and R26, which is not limited to be satisfied at the same time as the first predetermined signal is connected by the connection point of R7 and R8, it can also be the first predetermined signal. The two predetermined signals are directly connected to the output terminal of the second comparator U3, or connected in other ways, while the first predetermined signal is connected to the connection point of R7 and R8; the present invention is not limited to this.

Due to the setting of the AND gate U4, PCTL1=PCTL1A·PCTL1B, during the power-on process, PCTL1B is set before PCTL1A, then PCTL1=PCTL1A, the generation of the timing control signal PCTL1 depends on the timing generation unit 20, that is, it is not affected by the compensation circuit 30 In the power-off process, if PCTL1A is set to zero after PCTL1B or PCTL1 fails to be set to zero normally as shown in Figure 6, then PCTL1=PCTL1B, when the voltage VIN_EXT of the external power input terminal is powered off to the threshold V1, PCTL1 Then the output will be set to zero, and the compensation circuit 30 will play a role at this time, as shown in FIG. 8 . Wherein, when the voltage VIN_EXT of the external power supply input terminal drops to the threshold value V1, each power supply of the power conversion module 15 that needs to be powered off still works normally, that is, the output voltage is normal. Preferably, the setting of each element of the compensation unit 30 satisfies: VREF*R24/(R23+R24)=V1*R22/(R21+R22). This configuration ensures that the second predetermined signal PCTL1B output by the output terminal of the second comparator U3 of the compensation circuit 30 can be set to zero when the voltage VIN_EXT of the external power input terminal is powered down to the fourth threshold V1.

The function of the compensation circuit 30 is described above by taking the first timing generation unit 20 as an example. Those skilled in the art can understand that, in practice, each timing generation unit or a part of the timing generation units may be used in cooperation with a corresponding compensation circuit. In this way, it can be ensured that the control sequence generation module 14 can reliably output the sequence control signal when the voltage VIN_EXT of the external power input terminal is powered off.

To sum up, the sequence control circuit provided by the present invention mainly adopts discrete passive devices, operational amplifiers and other devices to realize a low-cost power supply voltage sequence control scheme with low cost, simple structure and low power consumption. Further, the control sequence generation module may include multiple sequence generation units, which can be extended to realize the power sequence control of power-on and power-off of multiple power sources of the power conversion module according to actual needs, and the scheme is highly scalable. At the same time, the delay time between the timing generation units of each channel can be adjusted by changing the hardware circuit parameters according to the actual application, which is convenient to adjust and has high circuit reliability.

The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosure all belong to the protection scope of the claims.

Claims (10)

1. a sequence control circuit, is characterized in that, comprises: power-on delay module, reference voltage generation module and control sequence generation module; The input end of the power-on delay module is connected to the power input end, and the output end of the power-on delay module is connected to the control sequence generation module, so as to output the first voltage to the control sequence generation module; The input end of the reference voltage generation module is used for connecting with the power input end, and the output end of the reference voltage generation module is connected with the control sequence generation module, so as to output the second voltage to the control sequence generation module; The control timing generation module outputs timing control signals driven by the first voltage and the second voltage; The timing control circuit is configured such that after the power input terminal is powered on, the reference voltage generating module outputs the second voltage before the power-on delay module outputs the first voltage. 2 . The sequence control circuit according to claim 1 , wherein the sequence control circuit further comprises a power-off hold module, the power-off hold module is used to connect to a power input terminal and to connect to the power input terminal. 3 . The power-on delay module and the reference voltage generating module are powered within a predetermined time after the terminal is powered off. 3 . The timing control circuit according to claim 1 , wherein the control timing generating module comprises at least two timing generating units, and the first input terminal of each timing generating unit is connected to the reference voltage generating module. 4 . The output terminal of each timing generation unit is connected to the output terminal of the power-on delay module, and the output terminal of each timing generation unit is used for outputting a timing control signal. 4. The timing control circuit according to claim 3, wherein the timing generating unit comprises: a first comparator, a first resistor, a second resistor and a first capacitor; The first input end of the first comparator is connected to the output end of the power-on delay module through the first resistor, and the first input end of the first comparator is also grounded through the second resistor, the first capacitor is connected in parallel with both ends of the second resistor; The output end of the reference voltage generating module supplies power to the first comparator; The first comparator is configured such that when the voltage of the first input terminal of the first comparator reaches a first threshold value, the output terminal of the first comparator outputs a first predetermined signal. 5. The sequence control circuit according to claim 4, wherein the control sequence generation module further comprises a compensation unit, the compensation unit comprising: a second comparator, a third resistor, a fourth resistor and an AND gate; The first input terminal of the second comparator is connected to the power input terminal through the third resistor, and the first input terminal of the second comparator is also grounded through the fourth resistor; The output end of the reference voltage generating module supplies power to the second comparator; The second comparator is configured such that when the voltage of the first input terminal of the second comparator reaches a second threshold value, the output terminal of the second comparator outputs a second predetermined signal; Input terminals of the AND gate are respectively connected to the output terminal of the first comparator and the output terminal of the second comparator, and the output terminal of the AND gate is configured to output the timing control signal. 6 . The timing control circuit according to claim 5 , wherein the timing generating unit further comprises: a fifth resistor and a sixth resistor, and the second input terminal of the first comparator is connected through the fifth resistor. 7 . Connected to the output end of the reference voltage generating module, the second input end of the first comparator is also grounded through the sixth resistor, and the first threshold is determined by the difference between the fifth resistor and the sixth resistor. and/or, the compensation unit further includes: a seventh resistor and an eighth resistor, the second input end of the second comparator is connected to the output of the reference voltage generating module via the seventh resistor The second input terminal of the second comparator is also grounded through the eighth resistor, and the second threshold is determined by the resistance ratio of the seventh resistor and the eighth resistor. 7 . The timing control circuit according to claim 5 , wherein the timing generating unit further comprises: a ninth resistor and a tenth resistor, and the output terminals of the first comparator are arranged in sequence through the ninth resistors. 8 . The resistor and the tenth resistor are grounded, and the voltage of the first predetermined signal is determined by the resistance ratio of the ninth resistor and the tenth resistor; and/or, the compensation unit further includes: an eleventh resistor and the twelfth resistor, the output terminal of the second comparator is grounded through the eleventh resistor and the twelfth resistor arranged in sequence, and the second predetermined signal is connected by the eleventh resistor and the twelfth resistor. The connection point of the twelfth resistor is connected out. 8 . The timing control circuit according to claim 1 , wherein the reference voltage generating module comprises a low dropout linear regulator. 9 . 9. The timing control circuit according to claim 1, wherein the power-on delay module comprises: a thirteenth resistor, a fourteenth resistor, a second capacitor and a transistor; The control terminal of the transistor is connected to the power input terminal through the thirteenth resistor, the control terminal of the transistor is also grounded through the fourteenth resistor, and the second capacitor is connected in parallel with the thirteenth resistor Both ends of the transistor; the input end of the transistor is connected to the power supply input end, and the output end of the transistor is configured as the output end of the power-on delay module; the transistor is configured as the control end of the control end Turning on when the voltage or control current reaches a third threshold, wherein the third threshold is determined by a resistance ratio of the thirteenth resistor and the fourteenth resistor. 10 . The timing control circuit according to claim 9 , wherein the transistor comprises a MOS transistor, the power-on delay module further comprises a diode, and the diode is connected in parallel to both ends of the second capacitor. 11 .

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