CN111489963B - Preparation method of SiC-MOSFET gate with thick gate oxide layer at corner of trench - Google Patents

Abstract

A method for preparing a SiC-MOSFET gate with a thick gate oxide layer at the corner of the trench. The steps are: 1. Etching the upper surface of the epitaxial layer to form a trench; 2. Growing polysilicon or amorphous silicon on the upper surface of the epitaxial layer and the inner wall of the trench. Silicon; 3 Deposit the SiO ₂ layer that completely covers the upper surface of the epitaxial layer and fills the groove; 4 Planarize the upper surface of the epitaxial layer so that the upper surface of the SiO ₂ layer is flush with the upper surface of the epitaxial layer; 5 Etch the SiO ₂ layer , keep the oxide layer at the bottom of the trench; 6 etch the polysilicon or amorphous silicon above the upper surface level of the SiO ₂ layer; 7 etch the entire SiO ₂ layer at the bottom of the trench; 8 high-temperature oxidation of the exposed silicon carbide and Polysilicon or amorphous silicon, so that it forms an oxide layer. Adopt the preparation method of the present invention, utilize _SiO2 instead of photoresist as mask layer, oxidize polysilicon or amorphous silicon at the bottom of the trench, play the effect of thickening the oxide layer at the corner of the trench, which increases the thickness of the oxide layer at the corner of the trench. Reverse electric field strength withstand capacity.

Description

A preparation method of SiC-MOSFET gate with thick gate oxide layer at trench corner

technical field

The invention relates to the technical field of semiconductors, in particular to a method for preparing a SiC-MOSFET gate with a thick gate oxide layer at the corner of a trench.

Background technique

Modern electronic technology puts forward new requirements for semiconductor materials such as high voltage, high frequency, high power, high temperature and radiation resistance, and the third-generation semiconductor material SiC with wide bandgap has wide bandgap, high critical breakdown electric field, high saturation electron mobility, With the advantages of high melting point and high thermal conductivity, it is an ideal material for the preparation of power electronic devices. Among SiC switching devices, SiC-MOSFET has the advantages of fast switching speed, high voltage resistance and low power consumption. SiC-MOSFET is mainly divided into planar type and trench type. Due to the vertical channel used in trench type devices, electron migration The efficiency is higher and there is no JFET effect. Compared with the planar SiC-MOSFET, the trench SiC-MOSFET can achieve lower on-resistance, so the trench SiC-MOSFET has a broader development prospect.

Trench-type SiC-MOSFET adopts a vertical structure in which the source and drain are above and below the wafer, respectively. However, due to the high critical breakdown electric field strength of silicon carbide, the electric field strength of the gate oxide layer at the corner of the trench SiC-MOSFET trench is often very high. When it exceeds the range that the oxide layer can withstand, it is easy to cause device damage. fail.

In the trench type SiC-MOSFET, since the semiconductor silicon carbide wafer used is usually (0001) crystal orientation, the oxidation rate of the (0001) crystal plane at the bottom of the device trench is significantly lower than the oxidation rate of the sidewall of the trench, while The thickness of the oxide layer on the side wall of the trench is affected by the threshold voltage and cannot be thickened. This results in that when the side wall and bottom of the trench are oxidized at the same time, the thickness of the oxide layer at the bottom of the trench including its corners is thinner, which further exposes the trench. The above-mentioned situation is further exacerbated by defects of high electric field strength in the gate oxide layer at the trench corner of the trench SiC-MOSFET.

In the face of the above defects, the solutions of the prior art are mainly as follows: 1. The designer of the product makes some kind of compromise and sacrifice in terms of device performance; 2. Adopts a special crystal structure; 3. By changing the doping concentration at the bottom of the trench 4. Increase the oxidation rate of the silicon carbide material at the bottom of the trench by means of ion implantation. These improvement methods will significantly increase the complexity and cost of the process, and bring great restrictions to the design.

Contents of the invention

The purpose of the invention is to provide a method for preparing a SiC-MOSFET gate with a thick gate oxide layer at the corner of the trench.

In order to achieve the above object, the technical scheme that the present invention takes is as follows:

A method for preparing a SiC-MOSFET gate with a thick gate oxide layer at the corner of the trench, comprising the following steps:

Step S1: patterning the SiC epitaxial layer so that grooves are etched on the upper surface of the SiC epitaxial layer, and the groove depth ranges from 0.3-100um, and the opening width ranges from 0.3-5um;

Step S2: Isotropically growing a layer of polysilicon or amorphous silicon on the upper surface of the SiC epitaxial layer and the inner wall of the trench formed by patterning, the thickness of which is 2-800nm;

Step S3: Depositing a SiO ₂ layer so that it completely covers the upper surface of the SiC epitaxial layer and fills the grooves formed by patterning;

Step S4: Planarize the upper surface of the SiC epitaxial layer by semiconductor processing techniques such as CMP or dry etching, and retain the amorphous silicon polysilicon or amorphous silicon and _SiO2 layer in the trench, so that the remaining _SiO2 layer The surface is flush with the upper surface of the SiC epitaxial layer;

Step S5: performing SiO ₂ etching using a high SiO ₂ /Si selective ratio dry etching process, etching part of the SiO ₂ layer retained in step S4, and retaining the SiO ₂ layer below a certain depth in the covering trench;

Step S6: Etching all the polysilicon or amorphous silicon on the upper surface of the SiC epitaxial layer and the polysilicon or amorphous silicon not covered by the remaining silicon dioxide layer on the side wall of the trench, after the etching is completed, the bottom of the trench and the side of the trench The polysilicon or amorphous silicon retained by the wall constitutes a "concave" structure;

Step S7: using high selectivity SiO ₂ /Si dry etching or wet etching all the SiO ₂ layer at the bottom of the trench retained in step S5, retaining the bottom of the trench and the side walls of the trench in step S6 Polysilicon or amorphous silicon with a "concave"structure;

Step S8: Simultaneously high-temperature oxidation of the exposed SiC on the sidewall of the trench and the polysilicon or amorphous silicon retained in step S7, after the oxidation is completed, the thickness of the _SiO2 layer formed by the oxidation of polysilicon or amorphous silicon is greater than that formed by the oxidation of SiC on the sidewall of the trench The thickness of the SiO ₂ layer, and the thickness of the SiO ₂ layer formed by SiC oxidation on the sidewall of the trench is 30-100nm.

In the preparation method of the present invention, firstly, _SiO is used instead of the photoresist as a mask layer, which compensates for the floating glue phenomenon produced by the photoresist during corrosion, and also avoids the damage of the device in the subsequent etching process; then Remove excess polysilicon and amorphous silicon; finally oxidize the remaining polysilicon or amorphous silicon and silicon carbide together. The remaining oxidation products of polysilicon and amorphous silicon play the role of thickening the oxide layer at the corner of the trench, not as the gate oxide itself, which increases the strength of the reverse electric field at the corner of the trench and solves the problem of the existing technology. The problem that the gate oxide at the intersection of the side wall of the gate trench of the middle trench type SiC-MOSFET and the bottom of the trench is too strong against the reverse electric field.

Description of drawings

FIG. 1 is a schematic structural diagram after step S3 is completed.

FIG. 2 is a schematic structural diagram after step S4 is completed.

FIG. 3 is a schematic structural diagram after step S5 is completed.

Fig. 4 is a schematic structural diagram of the preparation process in step S6.

FIG. 5 is a schematic structural diagram after step S7 is completed.

FIG. 6 is a schematic structural diagram after step S8 is completed.

FIG. 7 is a schematic structural diagram of a trench SiC-MOSFET gate in step S5.

FIG. 8 is a schematic structural diagram of a trench SiC-MOSFET gate in step S8.

1. SiC epitaxial layer; 2. Polysilicon or amorphous silicon; 3. Deposited _SiO2 layer; 4. _SiO2 layer formed by oxidation of polysilicon or amorphous silicon; 5. _SiO2 layer formed by oxidation of SiC; 6. Source region .

Detailed ways

The following describes in detail the preparation method of a trench silicon carbide MOSFET gate according to the present invention to improve the reverse electric field strength of the gate oxide layer at the corner of the trench with reference to the accompanying drawings and specific embodiments.

A method for preparing a SiC-MOSFET gate with a thick gate oxide layer at a trench corner, comprising the steps of:

Step S1: patterning the SiC epitaxial layer 1 so that grooves are etched on the upper surface of the SiC epitaxial layer 1, and the groove depth ranges from 0.3-100um, and the opening width ranges from 0.3-5um;

Among them, the preferred range of groove depth is 0.5-90um; the better range is 5-70um; the best range is 10-40um;

Among them, the preferred range of opening width is 0.5-4um; the better range is 1-3um; the best range is 1.5-2um;

Both the depth of the groove and the width of the opening have an impact on the electrical properties of the device, such as on-resistance, leakage current, threshold voltage and breakdown voltage, and ultimately affect the quality of the device. Three ranges are provided for the depth and the opening width respectively. According to the preferred range, the better range and the best range, the performance of the device is improved sequentially, and the performance of the device reaches the best within the best range.

Step S2: growing a layer of polysilicon or amorphous silicon 2 on the upper surface of the SiC epitaxial layer 1 and the inner wall of the trench formed by patterning, the thickness of which is 2-800nm;

Step S3: Depositing a SiO ₂ layer 3 so that it completely covers the upper surface of the SiC epitaxial layer 1 and fills the grooves formed by patterning, as shown in FIG. 1 ;

Step S4: planarizing the upper surface of the SiC epitaxial layer 1, retaining the polysilicon or amorphous silicon 2 and the _SiO2 layer 3 in the trench, so that the remaining upper surface of the _SiO2 layer 3 is flush with the upper surface of the SiC epitaxial layer 1 , specifically as shown in Figure 2;

Step S5: Etching _SiO 2 by using a high SiO ₂ /Si selective ratio dry etching process, etching part of the SiO ₂ layer 3 retained in step S4, and retaining the SiO ₂ layer 3 below a certain depth in the covering trench, specifically As shown in Figure 3;

Step S6: Etching all the polysilicon or amorphous silicon 2 on the upper surface of the SiC epitaxial layer 1 and the polysilicon or amorphous silicon 2 whose side walls of the trench are not covered by the remaining silicon dioxide layer, after the etching is completed, the bottom of the trench and the The polysilicon or amorphous silicon 2 retained on the side wall of the trench has a "concave" structure, as shown in Figure 4;

Step S7: using high selectivity SiO ₂ /Si dry etching or wet etching all the SiO ₂ layer 3 at the bottom of the trench retained in step S5, retaining the composition of the trench bottom and trench sidewalls in step S6 Polysilicon or amorphous silicon 2 with a "concave" structure, as shown in Figure 5;

Step S8: Simultaneously high-temperature oxidation of the SiC exposed on the sidewall of the trench and the polysilicon or amorphous silicon 2 retained in step S7, after the oxidation is completed, the thickness of the SiO ₂ layer 4 formed by the oxidation of the polysilicon or amorphous silicon 2 is greater than that of the SiC on the sidewall of the trench The thickness of the _SiO2 layer 5 formed by oxidation, and the thickness of the _SiO2 layer 5 formed by oxidation of SiC on the trench sidewall is 30-100nm, preferably in the range of 35-90nm; better in the range of 40-75nm; best in the range of 45-60nm , specifically as shown in Figure 6.

Further, in step S1, the groove is formed by etching using a photolithography process, and the groove is formed by plasma dry etching, and the groove angle is 70-90 ^° .

Further, in step S2, polysilicon or amorphous silicon 2 is grown on the inner wall of the trench by isotropic growth by chemical vapor deposition.

Further, in step S4, the method used for planarizing the upper surface of the SiC epitaxial layer 1 is CMP process or anisotropic dry etching and etching back; Use endpoint detection.

Further, in step S8, the SiO layer 3 formed by oxidation of polysilicon or amorphous silicon ₂ has a thickness of 30-1500nm, preferably in the range of 75-1000nm; more preferably in the range of 150-800nm; most preferably in the range of 200-500nm, In the preparation method of the present invention, the final step is to oxidize the remaining polysilicon or amorphous silicon and silicon carbide together, and the oxidation products of the remaining polysilicon and amorphous silicon play the role of thickening the oxide layer at the corner of the trench , increase the reverse electric field strength bearing capacity at the corner of the trench to obtain higher performance devices, the present invention provides the bottom SiO ₂ layer 3 thicknesses in the above three ranges, according to the preferred range, better range and best range, device performance Increase in turn, and the device performance reaches the best within the best range.

Further, in step S8, the temperature for high-temperature oxidation is 600-2000°C, and the oxidizing gas used to oxidize polysilicon or amorphous silicon 2 into SiO ₂ layer 3 is dry oxygen, wet oxygen, NO, N ₂ O or NO One or more of ₂ .

Further, after step S8 is completed, all residual polysilicon or amorphous silicon 2 is oxidized, and after a thick oxide film is formed at the corner of the bottom of the trench, a wet etching process can also be used to etch away the SiO formed by oxidation of SiC on the side wall of the trench. ₂ layers 5, the thickness of the oxide film at the corner of the bottom is correspondingly thinned, but it still remains. Then perform the SiC gate oxidation process again to grow the gate oxide film thickness required for the MOSFET channel.

Further, as shown in FIG. 7 for a structure of a trench type SiC-MOSFET gate, in step S5, in the above structure, the doping type of the source region 6 is opposite to that of the SiC epitaxial layer 1, and a certain depth refers to the SiC epitaxial layer 1 The vertical depth H between the upper surface of layer 1 and the lower surface of source region 6, that is, the upper surface of _SiO2 layer 3 remaining after etching is below the lower surface of source region 6.

Further, as shown in FIG. 8, a structure of a trench type SiC-MOSFET gate, in step S8, in the above structure, after the oxidation is completed, the SiO ₂ layer 4 formed by oxidation of polysilicon or amorphous silicon 2 is formed in a certain Below the depth H, that is, in the vertical direction, the upper surface of the SiO ₂ layer 4 formed by oxidation of polysilicon or amorphous silicon 2 is below the lower surface of the source region 6 .

In the preparation method of the present invention, firstly, _SiO is used instead of the photoresist as a mask layer, which compensates for the floating glue phenomenon produced by the photoresist during corrosion, and also avoids the damage of the device in the subsequent etching process; then Remove excess polysilicon and amorphous silicon; finally oxidize the remaining polysilicon or amorphous silicon and silicon carbide together. The remaining oxidation products of polysilicon and amorphous silicon play the role of thickening the oxide layer at the corner of the trench, not as the gate oxide itself, which increases the strength of the reverse electric field at the corner of the trench and solves the problem of the existing technology. The problem that the gate oxide at the intersection of the side wall of the gate trench of the middle trench type SiC-MOSFET and the bottom of the trench is too strong against the reverse electric field.

The specific implementation manners described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific implementation methods of the present invention and are not intended to limit the present invention. Inventions, any modifications, equivalent replacements and improvements made within the gist of the present invention shall be included within the protection scope of the present invention.

Claims (6)

1. A method for preparing a SiC-MOSFET gate with a thick gate oxide layer at the corner of the trench, comprising the steps of: Step S1: patterning the SiC epitaxial layer (1), so that grooves are etched on the upper surface of the SiC epitaxial layer (1), and the groove depth ranges from 0.3-100um, and the opening width ranges from 0.3-5um; Step S2: growing a layer of polysilicon or amorphous silicon (2) on the upper surface of the SiC epitaxial layer (1) and the inner wall of the trench formed by patterning, with a thickness of 2-800 nm; Step S3: Depositing a SiO ₂ layer (3) so that it completely covers the upper surface of the SiC epitaxial layer (1) and fills the grooves formed by patterning; Step S4: planarizing the upper surface of the SiC epitaxial layer (1), retaining the polysilicon or amorphous silicon (2) and the _SiO2 layer (3) in the trench, so that the remaining _SiO2 layer (3) upper surface and The upper surface of the SiC epitaxial layer (1) is flush; Step S5: Etching SiO 2 by using a high SiO ₂ /Si selective ratio dry etching process, etching part of the SiO ₂ layer (3) retained in step S4, and retaining _the SiO ₂ layer below a certain depth in the covering trench ( 3); step S6: etching all the polysilicon or amorphous silicon (2) on the upper surface of the SiC epitaxial layer (1) and the polysilicon or amorphous silicon (2) whose sidewalls of the trench are not covered by the remaining silicon dioxide, After the etching is completed, the polycrystalline silicon or amorphous silicon (2) remaining at the bottom of the trench and on the sidewall of the trench forms a "concave"structure; Step S7: using high selectivity SiO ₂ /Si dry etching or wet etching the entire SiO ₂ layer (3) at the bottom of the trench retained in step S5, and retaining the bottom and sides of the trench in step S6 Polysilicon or amorphous silicon with "concave" structure formed by walls (2); Step S8: Simultaneously high temperature oxidize the exposed SiC on the sidewall of the trench and the polysilicon or amorphous silicon (2) retained in step S7, after the oxidation is completed, the thickness of the _SiO2 layer (4) formed by oxidation of the polysilicon or amorphous silicon (2) greater than the thickness of the _SiO2 layer (5) formed by SiC oxidation on the sidewall of the trench, and the thickness of the _SiO2 layer (5) formed by SiC oxidation on the sidewall of the trench is 30-100nm. 2. The method for preparing a SiC-MOSFET gate with a thick gate oxide layer at the corner of the trench according to claim 1, characterized in that: in step S1, the method of etching and forming the trench adopts a photolithography process, which etches Plasma dry etching is used to form trenches, and the trench angle is ^70-90o . 3. The method for preparing a SiC-MOSFET gate with a thick gate oxide layer at the corner of the trench according to claim 1, characterized in that: in step S2, polysilicon or amorphous silicon (2) is grown on the inner wall of the trench Isotropically grown by chemical vapor deposition. 4. The method for preparing a SiC-MOSFET gate with a thick gate oxide layer at the corner of the trench according to claim 1, characterized in that: in step S4, the upper surface of the SiC epitaxial layer (1) is planarized using The best method is CMP process or anisotropic dry etching etch back. 5. The method for preparing the SiC-MOSFET gate with a thick gate oxide layer at the corner of the trench according to claim 1, characterized in that: in step S8, the _SiO2 layer (3 ) thickness of 30-1500nm. 6. The method for preparing a SiC-MOSFET gate with a thick gate oxide layer at the corner of the trench according to claim 1, characterized in that: in step S8, the temperature for high temperature oxidation is 600-2000°C, polysilicon or All the amorphous silicon (2) is oxidized to SiO ₂ , and the oxidizing gas of the layer (3) is one or more of dry oxygen, wet oxygen, NO, N ₂ O or NO ₂ .

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