CN111489676B - Array substrate, driving method and display device - Google Patents
Array substrate, driving method and display device Download PDFInfo
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- CN111489676B CN111489676B CN202010340149.XA CN202010340149A CN111489676B CN 111489676 B CN111489676 B CN 111489676B CN 202010340149 A CN202010340149 A CN 202010340149A CN 111489676 B CN111489676 B CN 111489676B
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- 239000000758 substrate Substances 0.000 title claims abstract description 45
- 238000000034 method Methods 0.000 title claims abstract description 16
- 125000004122 cyclic group Chemical group 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 8
- 239000008186 active pharmaceutical agent Substances 0.000 description 6
- 239000010409 thin film Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000003139 buffering effect Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses an array substrate, a driving method and a display device, wherein the array substrate comprises a driving circuit, the driving circuit comprises a control circuit and a plurality of cascaded shift registers, and an output signal end of a shift register of the last stage is electrically connected with an input signal end of a shift register of the first stage through the control circuit. When the driving circuit starts to work, only one frame trigger signal is needed to be loaded on the driving circuit through the frame trigger signal end, when the driving circuit outputs a signal from the last stage of shift register, the signal output from the last stage of shift register can be provided for the input signal end of the first stage of shift register, so that the driving circuit can work circularly, and the requirement that the driving circuit works at a high refresh rate can be met without loading the frame trigger signal on the driving circuit at a high frequency.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to an array substrate, a driving method and a display device.
Background
With the rapid development of display technology, display panels are increasingly developed toward high integration and low cost. Among them, the array substrate row driving (Gate Driver on Array, GOA) technology integrates a thin film transistor (Thin Film Transistor, TFT) gate switching circuit on an array substrate of a display panel to form a scan driving of the display panel. Usually, when the gate switch circuit works, the driving chip is required to provide a trigger signal, but the refresh rate of the trigger signal provided by the existing driving chip has an upper limit, and the requirement of the array substrate with high refresh rate cannot be met.
Disclosure of Invention
The embodiment of the invention provides an array substrate, a driving method and a display device, which can realize high refresh rate scanning driving.
Therefore, the embodiment of the invention provides an array substrate, which comprises a driving circuit; the driving circuit comprises a control circuit and a plurality of shift registers in cascade connection;
the input signal end of the first-stage shift register is electrically connected with the frame trigger signal end, and in each two adjacent stages of shift registers, the input signal end of the next-stage shift register is electrically connected with the output signal end of the previous-stage shift register, and the output signal end of the next-stage shift register is electrically connected with the reset signal end of the previous-stage shift register;
the output signal end of the last stage shift register is electrically connected with the input signal end of the first stage shift register through the control circuit; the control circuit is used for transmitting signals of the output signal end of the last stage of shift register to the input signal end of the first stage of shift register.
Optionally, the control circuit includes a switching transistor, an output signal terminal of the last stage shift register is electrically connected to a first pole and a control pole of the switching transistor, and an input signal terminal of the first stage shift register is electrically connected to a second pole of the switching transistor.
Optionally, the control circuit includes a plurality of cascaded first virtual shift registers;
in each two adjacent stages of first virtual shift registers, the input signal end of the next stage of first virtual shift register is electrically connected with the output signal end of the previous stage of first virtual shift register, and the output signal end of the next stage of first virtual shift register is electrically connected with the reset signal end of the previous stage of first virtual shift register;
the output signal end of the last stage shift register is electrically connected with the input signal end of the first virtual shift register of the first stage, and the reset signal end of the last stage shift register is electrically connected with the output signal end of the first virtual shift register of the first stage; the input signal end of the first stage shift register is electrically connected with the output signal end of the first virtual shift register of any stage.
Optionally, the driving circuit further includes a plurality of second dummy shift registers connected in cascade between an input signal terminal of the first stage shift register and the frame trigger signal terminal;
the input signal end of the first stage second virtual shift register is electrically connected with the frame trigger signal end;
in each two adjacent stages of second virtual shift registers, the input signal end of the next stage of second virtual shift register is electrically connected with the output signal end of the previous stage of second virtual shift register, and the output signal end of the next stage of second virtual shift register is electrically connected with the reset signal end of the previous stage of second virtual shift register;
the output signal end of the second virtual shift register at the last stage is electrically connected with the input signal end of the first stage shift register, and the reset signal end of the second virtual shift register at the last stage is electrically connected with the output signal end of the first stage shift register.
Optionally, the cyclic reset signal ends of all shift registers are electrically connected with the reset signal end; the shift registers are configured to be reset according to the signals of the reset signal terminals.
Optionally, the circuit structure of all shift registers is the same.
Optionally, the array substrate further includes a plurality of gate lines; the driving circuit is electrically connected with the plurality of gate lines; and each shift register is electrically connected with one grid line correspondingly.
Based on the same inventive concept, the embodiment of the invention also provides a display device, which comprises any one of the array substrates.
Based on the same inventive concept, the embodiment of the invention also provides a driving method of any one of the array substrates, which comprises a plurality of driving periods; each of the drive periods comprises a plurality of successive scan phases;
in the first scanning stage, loading a frame trigger signal to a frame trigger signal end electrically connected with a first stage shift register in a driving circuit;
in each of the scan stages, the driving circuit sequentially inputs a scan signal to the plurality of gate lines electrically connected line by line.
Optionally, between every two adjacent driving periods, a reset phase is further included;
in the reset stage, a reset signal is loaded to the circulating reset signal ends of all the shift registers in the driving circuit through the reset signal ends so that all the shift registers are reset.
The invention has the following beneficial effects:
the embodiment of the invention provides an array substrate, a driving method and a display device, which comprise a driving circuit, wherein the driving circuit comprises a control circuit and a plurality of cascaded shift registers, and an output signal end of a shift register of the last stage is electrically connected with an input signal end of a shift register of the first stage through the control circuit. When the driving circuit starts to work, only one frame trigger signal is needed to be loaded on the driving circuit through the frame trigger signal end, when the driving circuit outputs a signal from the last stage of shift register, the signal output from the last stage of shift register can be provided for the input signal end of the first stage of shift register, so that the driving circuit can work circularly, and the requirement that the driving circuit works at a high refresh rate can be met without loading the frame trigger signal on the driving circuit at a high frequency.
Drawings
Fig. 1 is a schematic diagram of a driving circuit in an array substrate according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an array substrate according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a driving circuit in an array substrate according to another embodiment of the present invention;
FIG. 4 is a schematic diagram of a driving circuit in an array substrate according to another embodiment of the present invention;
FIG. 5 is a schematic diagram of a driving circuit in an array substrate according to another embodiment of the present invention;
FIG. 6 is a schematic diagram of a driving circuit in an array substrate according to another embodiment of the present invention;
fig. 7 is a signal timing diagram of an array substrate according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. It will be apparent that the described embodiments are some, but not all, embodiments of the invention. And embodiments of the invention and features of the embodiments may be combined with each other without conflict. All other embodiments, which can be made by a person skilled in the art without creative efforts, based on the described embodiments of the present invention fall within the protection scope of the present invention.
Unless defined otherwise, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The terms "first," "second," and the like, as used herein, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "electrically connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
It should be noted that the dimensions and shapes of the figures in the drawings do not reflect true proportions, and are intended to illustrate the present invention only. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.
An array substrate provided in an embodiment of the present invention, as shown in fig. 1, includes: a driving circuit; the driving circuit includes a control circuit 10, a plurality of shift registers in cascade: SR (1), SR (2) … … SR (N-1), SR (N) (total N shift registers, 1 < N);
the input signal end IN of the first stage shift register SR (1) is electrically connected with the frame trigger signal end STV, and IN each adjacent two stages of shift registers, the input signal end IN of the next stage shift register is electrically connected with the output signal end Out of the previous stage shift register, and the output signal end Out of the next stage shift register is electrically connected with the reset signal end Rst of the previous stage shift register;
the output signal end Out of the last stage shift register SR (N) is electrically connected with the input signal end IN of the first stage shift register through the control circuit 10; the control circuit 10 is configured to transmit a signal of the output signal terminal Out of the last stage shift register SR (N) to the input signal terminal IN of the first stage shift register SR (1).
IN the array substrate provided by the embodiment of the invention, the control circuit 10 is arranged IN the driving circuit, and the output signal end Out of the last stage shift register SR (N) is electrically connected with the input signal end IN of the first stage shift register SR (1) through the control circuit 10. When the driving circuit starts to work, only one frame trigger signal is needed to be loaded on the driving circuit through the frame trigger signal end STV, when the last stage of shift register SR (N) of the driving circuit outputs a signal, the signal output by the last stage of shift register SR (N) can be provided for the input signal end IN of the first stage of shift register SR (1), so that the driving circuit can work circularly, and the requirement that the driving circuit works at a high refresh rate can be met without loading the frame trigger signal on the driving circuit at a high frequency.
In implementation, as shown in fig. 2, the array substrate may include: a substrate, and a plurality of pixel units on the substrate. In general, a pixel unit includes a plurality of sub-pixels P, each of which includes a pixel circuit and an organic light emitting diode electrically connected to the pixel circuit. The pixel circuits in one row of the sub-pixels P are electrically connected with a grid line G, the pixel circuits in one column of the sub-pixels P are electrically connected with a data line D, and the pixel circuits in the sub-pixels enable the organic light emitting diode to emit light under the control of the scanning signals of the electrically connected grid line G and the signals of the electrically connected data line D. The driving circuit 100 in the array substrate provided by the embodiment of the invention can be used as a gate driving circuit for providing a scanning signal for the gate line G. Also, the driving circuit may be integrated on the substrate using an array substrate row driving (Gate Driver on Array, GOA) technique to form a scan driving for the gate lines.
In a specific implementation, in an embodiment of the present invention, as shown in fig. 1, an array substrate may include a plurality of gate lines: g (1), G (2) … … G (N-1), G (N); the driving circuit is electrically connected with the grid lines; in the cascade connection of a plurality of shift registers, each shift register is electrically connected with one grid line correspondingly.
In particular embodiments, the driving circuit is configured to sequentially supply scan signals to the plurality of gate lines electrically connected. Specifically, in the cascaded shift registers, the output signal terminal Out of each shift register is electrically connected to one gate line correspondingly: the output signal end Out of the first stage shift register SR (1) is electrically connected with the grid line G (1), the output signal end Out of the second stage shift register SR (2) is electrically connected with the grid line G (2), and the output signal end Out of the last stage shift register SR (N) is electrically connected with the grid line G (N). From the first stage shift register SR (1) to the last stage shift register SR (N), scanning signals are sequentially output to the corresponding grid lines through the output signal end Out, namely the driving circuit completes the signal output of one frame and can drive the display picture of one frame.
IN particular, IN the embodiment of the present invention, as shown IN fig. 3, the control circuit 10 may include a switching transistor T, where the output signal terminal Out of the last stage shift register SR (N) is electrically connected to the first pole and the control pole of the switching transistor T, and the input signal terminal IN of the first stage shift register SR (1) is electrically connected to the second pole of the switching transistor T.
IN a specific implementation, when the switching transistor T is turned on, the signal output by the shift register SR (N) of the last stage is directly supplied to the input signal terminal IN of the shift register SR (1) of the first stage through the switching transistor T, so that the shift register SR (1) of the first stage continues to output the signal. That is, when signals are sequentially output from the first stage shift register SR (1) to the last stage shift register SR (N) in the driving circuit, that is, after the driving circuit finishes the scanning signal output of one frame, the scanning signal output of the next frame can be immediately performed, and no buffer time is required between the two frame signal outputs, so that seamless connection of two adjacent frames of display pictures can be realized.
In practice, the first pole of the switching transistor T is electrically connected to the control pole, forming a diode structure, enabling the signal to be transmitted only from the first pole to the second pole of the switching transistor T. When the frame trigger signal is loaded through the frame trigger signal terminal STV, the frame trigger signal is not transmitted to the output signal terminal Out of the last stage shift register through the switching transistor T.
Specifically, in the array substrate provided in the embodiment of the present invention, the switching transistor may be a thin film transistor (TFT, thin Film Transistor) or a metal oxide semiconductor field effect transistor (MOS, metal Oxide Scmiconductor), which is not limited herein. The control electrode of the switching transistor may be used as a gate electrode, and the first electrode of the switching transistor may be used as a source electrode, the second electrode may be used as a drain electrode, or the first electrode of the switching transistor may be used as a drain electrode, and the second electrode may be used as a source electrode, depending on the types of the switching transistors and the signals of the control electrodes of the switching transistors.
In implementation, in the embodiment of the present invention, as shown in fig. 4, the control circuit 10 may also include a plurality of cascaded first virtual shift registers: DS (1), DS (2) … …;
IN each two adjacent stages of first virtual shift registers, an input signal end IN of a next stage of first virtual shift register is electrically connected with an output signal end Out of an upper stage of first virtual shift register, and the output signal end Out of the next stage of first virtual shift register is electrically connected with a reset signal end Rst of the upper stage of first virtual shift register;
the output signal end Out of the last stage shift register SR (N) is electrically connected with the input signal end IN of the first stage first virtual shift register DS (1), and the reset signal end Rst of the last stage shift register SR (N) is electrically connected with the output signal end Out of the first stage first virtual shift register DS (1); the input signal terminal IN of the first stage shift register SR (1) is electrically connected to the output signal terminal Out of the first dummy shift register of any stage.
IN the driving circuit shown IN fig. 4, the input signal terminal IN of the first stage shift register SR (1) is electrically connected to the output signal terminal Out of the first stage first dummy shift register DS (1), but is not limited thereto. In practical applications, the number of the first virtual shift registers may be determined according to the design of the practical needs, which is not limited herein. The input signal terminal IN of the first stage shift register SR (1) and the output signal terminal Out of which stage of the first virtual shift register are electrically connected may be designed and determined according to actual needs, and are not limited herein.
IN a specific implementation, after the output signal of the output signal terminal Out of the last stage shift register SR (N) is provided to the input signal terminal IN of the first stage first virtual shift register DS (1), the first stage first virtual shift register is triggered to operate, so that the output signal terminal Out of the first stage first virtual shift register outputs the signal. And, the signal output by the output signal end Out of the first stage first virtual shift register is provided to the input signal end of the first stage shift register to trigger the first stage shift register to work, so that the scanning signal output of the next frame can be automatically started. Thus, the buffer time can be set between the two frames of scanning signal output, and the display effect of the display pictures of two adjacent frames can be improved.
IN a specific implementation, the control circuit 10 includes a plurality of cascaded first virtual shift registers, and when the input signal terminal IN of the first stage shift register SR (1) is electrically connected to the second stage first virtual shift register or the first virtual shift register after the second stage first virtual shift register, the output signal terminal Out of the last stage shift register SR (N) outputs a signal, and when the output signal of the first virtual shift register is also cascaded, the input signal terminal of the first stage shift register will input a signal. Therefore, after the output signal terminal Out of the last stage shift register SR (N) outputs a signal, the input signal terminal IN of the first stage shift register SR (1) will not input a signal until a buffering time is needed, and the buffering time can be adjusted by adjusting the number of first virtual shift registers electrically connected between the output signal terminal Out of the last stage shift register SR (N) and the input signal terminal IN of the first stage shift register SR (1).
IN a specific implementation, the output signal Out of the first virtual shift register is not electrically connected to the gate line, and when the frame trigger signal is loaded through the frame trigger signal terminal STV, the frame trigger signal is transmitted to the output signal Out of the first virtual shift register electrically connected to the input signal terminal IN of the first stage shift register SR (1), but the display is not affected.
IN a specific implementation, IN an embodiment of the present invention, the driving circuit may further include a plurality of second virtual shift registers connected IN cascade between the input signal terminal IN of the first stage shift register and the frame trigger signal terminal STV;
the input signal end IN of the first stage second virtual shift register is electrically connected with the frame trigger signal end STV;
IN each two adjacent stages of second virtual shift registers, an input signal end IN of a next stage of second virtual shift register is electrically connected with an output signal end Out of a previous stage of second virtual shift register, and an output signal end Out of the next stage of second virtual shift register is electrically connected with a reset signal end Rst of the previous stage of second virtual shift register;
the output signal end Out of the second virtual shift register of the last stage is electrically connected with the input signal end IN of the first stage shift register, and the reset signal end Rst of the second virtual shift register of the last stage is electrically connected with the output signal end Out of the first stage shift register.
IN an implementation, as shown IN fig. 5, the second dummy shift register D connected between the input signal terminal IN of the first stage shift register and the frame trigger signal terminal STV may include only one. Of course, in practical applications, the number of the second virtual shift registers may be determined according to the design of the practical needs, which is not limited herein.
IN a specific implementation, when the control circuit 10 transmits the signal of the output signal terminal Out of the last stage shift register to the input signal terminal IN of the first stage shift register, the signal transmission to the frame trigger signal terminal STV can be avoided by setting the second virtual shift register.
In a specific implementation, in the embodiment of the present invention, as shown in fig. 3 and fig. 6, all shift registers, including the above cascaded shift registers, the first virtual shift register, and the second virtual shift register, have a cyclic reset signal terminal CR; these cyclic reset signal terminals CR may be electrically connected to the reset signal terminal TR; all shift registers are configured to be reset according to the signal of the reset signal terminal TR.
In a specific implementation, when the driving circuit works, the reset signal ends TR load the reset signals to all the cyclic reset signal ends Rst, so that all the shift registers can be reset, and all the shift registers can stop working.
In a specific implementation, in an embodiment of the present invention, all shift registers, including the cascaded shift registers, the first virtual shift register, and the second virtual shift register may have the same circuit structure. Specifically, the circuit structure of all shift registers may be substantially the same as that in the prior art, and will not be described herein. Other essential components of these shift registers are those of ordinary skill in the art and will not be described in detail herein, nor should they be considered as limiting the invention.
Based on the same inventive concept, the embodiment of the invention also provides a driving method of any one of the array substrates provided by the embodiment of the invention, which comprises a plurality of driving periods; each drive cycle comprises a plurality of successive scan phases;
in the first scanning stage, loading a frame trigger signal to a frame trigger signal end electrically connected with a first stage shift register in a driving circuit;
in each scanning stage, the driving circuit sequentially inputs scanning signals to a plurality of gate lines electrically connected line by line.
In particular embodiments, in embodiments of the present invention, a reset phase is included between each adjacent two drive cycles;
in the reset stage, the reset signal ends load reset signals to the circulating reset signal ends of all the shift registers in the driving circuit through the reset signal ends so as to reset all the shift registers.
The present invention will be described in detail with reference to specific examples. The present embodiment is for better explaining the present invention, but not limiting the present invention.
The following describes the operation of the array substrate according to the embodiment of the present invention with reference to the signal timing diagram shown in fig. 7 by taking the structure of the array substrate shown in fig. 3 as an example. Specifically, the driving period T1, the reset phase R, and the driving period T2 in fig. 7 are selected. The driving period T1 includes a first scanning period T1 and a second scanning period T2.
IN the first scan stage t1, the input signal terminal IN of the first stage shift register SR (1) is loaded with a frame trigger signal through the frame trigger signal terminal STV. After receiving the frame trigger signal, the first stage shift register SR (1) shifts and outputs a scan signal, and supplies the scan signal to the gate line G (1) and the second stage shift register SR (2). After receiving the scan signal supplied from the first stage shift register SR (1), the second stage shift register SR (2) shifts and outputs the scan signal, and supplies the scan signal to the gate line G (2) and the third stage shift register SR (3). IN the adjacent two stages of shift registers, the upper stage of shift register provides the scanning signal to the corresponding grid line and the input signal end IN of the lower stage of shift register, and the lower stage of shift register outputs the scanning signal after receiving the scanning signal. After receiving the scan signal, the last stage shift register SR (N) shifts and outputs the scan signal to the gate line G (N) and the first pole of the switching transistor T, and the switching transistor T provides the scan signal to the input signal terminal IN of the first stage shift register SR (1).
In the second scan stage t2, the first shift register SR (1) receives the scan signal output from the last shift register SR (N) and then shifts the output scan signal. The subsequent operation may be substantially the same as the first scanning stage t1, and will not be described here.
In the reset phase R, all shift registers can be reset by loading the reset signal to all the cyclic reset signal terminals Rst through the reset signal terminal TR, and all the shift registers stop outputting signals.
In the driving period T2, including the first scanning stage T1 and at least one second scanning stage T2, the working process may be substantially the same as that of the first scanning stage T1 and the second scanning stage T2 in the driving period T1, which is not described herein.
Based on the same inventive concept, the embodiment of the invention also provides a display device, which comprises the array substrate provided by the invention. The specific implementation of the method can be seen in the implementation process of the array substrate, and the details of the method are not repeated. The display device may be: any product or component with display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device will be understood by those skilled in the art, and are not described herein in detail, nor should they be considered as limiting the invention.
The array substrate, the driving method and the display device provided by the embodiment of the invention comprise a driving circuit, wherein the driving circuit comprises a control circuit and a plurality of cascaded shift registers, and an output signal end of a shift register of the last stage is electrically connected with an input signal end of a shift register of the first stage through the control circuit. When the driving circuit starts to work, only one frame trigger signal is needed to be loaded on the driving circuit through the frame trigger signal end, when the driving circuit outputs a signal from the last stage of shift register, the signal output from the last stage of shift register can be provided for the input signal end of the first stage of shift register, so that the driving circuit can work circularly, and the requirement that the driving circuit works at a high refresh rate can be met without loading the frame trigger signal on the driving circuit at a high frequency.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (8)
1. An array substrate is characterized by comprising a driving circuit; the driving circuit comprises a control circuit and a plurality of shift registers in cascade connection;
the input signal end of the first-stage shift register is electrically connected with the frame trigger signal end, and in each two adjacent stages of shift registers, the input signal end of the next-stage shift register is electrically connected with the output signal end of the previous-stage shift register, and the output signal end of the next-stage shift register is electrically connected with the reset signal end of the previous-stage shift register;
the output signal end of the last stage of shift register is electrically connected with the input signal end of the first stage of shift register through the control circuit; the control circuit is used for transmitting signals of the output signal end of the last stage of shift register to the input signal end of the first stage of shift register;
the control circuit comprises a plurality of cascaded first virtual shift registers;
in each two adjacent stages of first virtual shift registers, the input signal end of the next stage of first virtual shift register is electrically connected with the output signal end of the previous stage of first virtual shift register, and the output signal end of the next stage of first virtual shift register is electrically connected with the reset signal end of the previous stage of first virtual shift register;
the output signal end of the last stage shift register is electrically connected with the input signal end of the first virtual shift register of the first stage, and the reset signal end of the last stage shift register is electrically connected with the output signal end of the first virtual shift register of the first stage; the input signal end of the first stage shift register is electrically connected with the output signal end of the first virtual shift register of any stage.
2. The array substrate of claim 1, wherein the driving circuit further comprises a plurality of second dummy shift registers connected in cascade between an input signal terminal of the first stage shift register and the frame trigger signal terminal;
the input signal end of the first stage second virtual shift register is electrically connected with the frame trigger signal end;
in each two adjacent stages of second virtual shift registers, the input signal end of the next stage of second virtual shift register is electrically connected with the output signal end of the previous stage of second virtual shift register, and the output signal end of the next stage of second virtual shift register is electrically connected with the reset signal end of the previous stage of second virtual shift register;
the output signal end of the second virtual shift register at the last stage is electrically connected with the input signal end of the first stage shift register, and the reset signal end of the second virtual shift register at the last stage is electrically connected with the output signal end of the first stage shift register.
3. The array substrate of claim 1 or 2, wherein the cyclic reset signal terminals of all shift registers are electrically connected to the reset signal terminal; the shift registers are configured to be reset according to the signals of the reset signal terminals.
4. The array substrate of claim 1 or 2, wherein the circuit structures of all shift registers are the same.
5. The array substrate of claim 1 or 2, wherein the array substrate further comprises a plurality of gate lines; the driving circuit is electrically connected with the plurality of gate lines; and each shift register is electrically connected with one grid line correspondingly.
6. A display device comprising the array substrate according to any one of claims 1 to 5.
7. The driving method of an array substrate according to any one of claims 1 to 5, comprising a plurality of driving cycles; each of the drive periods comprises a plurality of successive scan phases;
in the first scanning stage, loading a frame trigger signal to a frame trigger signal end electrically connected with a first stage shift register in a driving circuit;
in each of the scan stages, the driving circuit sequentially inputs a scan signal to the plurality of gate lines electrically connected line by line.
8. The driving method as claimed in claim 7, further comprising a reset phase between each adjacent two of the driving periods;
in the reset stage, a reset signal is loaded to the circulating reset signal ends of all the shift registers in the driving circuit through the reset signal ends so that all the shift registers are reset.
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