CN111478840A - Double-rate arbitration relay device for bus system - Google Patents

Abstract

The invention discloses double-rate arbitration relay equipment for a bus system, which comprises a main interface, an interface control module, a cache and control module, a bus control module, a sub-bus and a plurality of secondary interfaces, wherein the main interface is used for being connected with a main central bus, and the secondary interfaces are used for being connected with a sensor; if the first multilevel symbol string successfully sent by the fast arbitration bus in one time slice is consistent with the partial multilevel symbol string sent by the slow arbitration bus, the data to be sent of all the relay devices successfully sending the multilevel symbol strings in the time slice on the fast arbitration bus are sequentially sent to a group of data buses at the beginning of the next time slice. The double-rate arbitration relay equipment for the bus system can dynamically adjust the arbitration rate and the data transmission rate, and improve the arbitration rate and the data transmission rate of the bus while ensuring the correctness of data transmission.

Description

Double-rate arbitration relay device for bus system

Technical Field

The invention relates to the technical field of data transmission, in particular to double-rate arbitration relay equipment for a bus system.

Background

As an important vehicle, the automobile has no need of repeated description on the importance of human daily life. From the birth of the first automobile in the 19 th century to the vigorous development of the automotive industry to date, the timely adjustment of this industry to the era has not been left. In modern society, the automobile industry has also changed correspondingly under the theme of electronic information technology.

From the publication by Bosch in 1986, the CAN bus is widely used in various fields and is also the main choice for on-board buses used in the automotive industry. The CAN bus also has some disadvantages, because the round trip delay of data transmission, the transmission rate of the CAN bus is related to the length of the bus, and as the length of the bus increases, the transmission rate needs to be reduced in order to ensure the correctness of data transmission.

Secondly, each device on the CAN bus shares one communication line, so that the problem of data transmission collision exists, the use right of the communication line is generally distributed by carrying out priority arbitration through a transmission arbitration signal, and the communication line is not efficient due to the fact that only one communication line has high collision probability. Meanwhile, due to the round-trip delay existing in the transmission of the arbitration signal, the transmission rate of the arbitration signal cannot be too high, and the data transmission and the arbitration signal are transmitted on the same communication line, so that the data transmission rate of the communication line is very low. And the arbitration signal is transmitted by binary symbols, namely symbols "0" and "1", and priority arbitration is performed by using the binary symbols, which has too low arbitration efficiency and long queuing time of the device.

Disclosure of Invention

The invention aims to provide a double-rate arbitration relay device for a bus system, which can dynamically adjust the arbitration rate and the data transmission rate, and improve the arbitration rate and the data transmission rate of a bus while ensuring the correctness of data transmission.

The invention discloses a technical scheme adopted by double-rate arbitration relay equipment for a bus system, which comprises the following steps:

a dual rate arbitration relay device for use in a bus system, characterized by: the sensor comprises a central bus, a main interface, an interface control module, a cache and control module, a bus control module, a sub-bus and a plurality of secondary interfaces, wherein the main interface is used for being connected with the central bus, and the secondary interfaces are used for being connected with a sensor;

the interface control module comprises a first arbitration control module and a first data transmission module, and the first arbitration control module and the first data transmission module are respectively connected with the central bus and the cache and control module; the bus control module comprises a second arbitration control module and a second data transmission module, and the second arbitration control module and the second data transmission module are respectively connected with the sub-bus and the cache and control module;

the central bus and the sub-buses have the same functional structure and respectively comprise: a slow arbitration bus, a fast arbitration bus and a data bus;

the data bus at least comprises 2 pairs of copper twisted pairs, and data to be transmitted are transmitted in a time slice through a data frame, wherein the time slice is the duration time required by the data bus for transmitting one data frame;

the fast arbitration bus transmits a multilevel symbol string in a fast arbitration time slot in the time slice through an arbitration frame, the fast arbitration time slot is the duration time required by the fast arbitration bus to transmit an arbitration frame, and the number of the fast arbitration time slots contained in one time slice is not less than the number of twisted wire pairs in the data bus; the multilevel symbol is represented by a multilevel comprising different states of voltage amplitude separated by a plurality of thresholds, the higher the voltage amplitude the higher the priority;

the slow arbitration bus transmits a multi-system symbol string in a slow arbitration time slot in a long time slice through an arbitration frame, the slow arbitration time slot is the duration time required by the slow arbitration bus to transmit one arbitration frame, the slow arbitration time slot is longer than 2 times of the fast arbitration time slot, the long time slice is the duration time of a plurality of slow arbitration time slots, the number of the slow arbitration time slots is not less than the number of twisted wire pairs in the data bus, and the duration time of the long time slice is usually longer than 2 times of the duration time of the time slice;

the second data transmission module in a receiving state receives data sent to a sub data bus and stores the data in a cache and control module, the second arbitration control module obtains a new multi-system symbol string through weighted calculation according to the received multi-system symbol string corresponding to the received data and the number of data to be sent cached in the cache module, and the priority of the new multi-system symbol string is higher than or equal to that of the originally received multi-system symbol string;

when data in the cache and control module needs to be uploaded through a central hub bus, the interface control module repeatedly sends a new multi-system symbol string to a fast arbitration bus in each fast arbitration time slot in a time slice, and simultaneously repeatedly sends a new multi-system symbol string to a slow arbitration bus in each slow arbitration time slot in a long time slice, a first arbitration control module in the interface control module compares the new multi-system symbol string with the voltage on the arbitration bus in the central hub bus bit by bit, if the priority of the new multi-system symbol is higher than the voltage priority on the arbitration bus in the central hub bus, the new multi-system symbol is output to the arbitration bus in the central hub bus, and simultaneously detects and compares the first arbitration frame respectively received on the fast arbitration bus and the slow arbitration bus in a time slice, and if the priority of the new multi-system symbol is lower than the voltage priority on the arbitration bus in the central hub bus, retransmitting the new multilevel symbol string at the next arbitration slot;

if the transmitted multi-system symbol strings in the first arbitration frame respectively received by the fast arbitration bus and the slow arbitration bus in one time slice are completely the same, the slow arbitration bus stops sending the arbitration frame and the fast arbitration bus simultaneously enters the arbitration of the next time slice; the interface control module successfully sends the complete multilevel symbol string through the fast arbitration bus at the first fast arbitration time slot, selects a group of data buses for data transmission through the data transmission module for the data to be uploaded in the cache and control module at the beginning of the next time slice, and successfully sends the complete new multilevel symbol string through the fast arbitration bus at the second fast arbitration time slot, selects another group of data buses for data transmission through the data transmission module for the data to be uploaded in the beginning cache and control module of the next time slice until all the data buses are completely distributed, and then enters the arbitration of the next time slice;

if the new multi-system symbol strings which are transmitted in the first arbitration frame detected from the fast arbitration bus and the slow arbitration bus are not identical, the fast arbitration bus stops the transmission of the arbitration frame until the slow arbitration bus finishes the transmission of the arbitration frame of a long time slice, and enters the arbitration of the next time slice together with the slow arbitration bus; the interface control module successfully sends a complete new multi-system symbol string through a slow arbitration bus in a first slow arbitration time slot, selects a group of data buses for data transmission through a data transmission module for data to be uploaded in a cache and control module at the beginning of the next slow time slice, and successfully sends the complete new multi-system symbol string through the slow arbitration bus in a second slow arbitration time slot, and selects another group of data buses for data transmission through the data transmission module for data transmission at the beginning of the next slow time slice until all the data buses are completely distributed, and then enters the arbitration of the next time slice;

when a sensor needs to send data to the double-rate arbitration relay equipment or a cache and a control module of the double-rate arbitration relay equipment needs to send data to the sensor, an interface control module and a bus control module of the sensor repeatedly send a multilevel symbol string to a sub-fast arbitration bus in each fast arbitration time slot in a time slice, and simultaneously repeatedly send the multilevel symbol string to a sub-slow arbitration bus in each slow arbitration time slot in a slow time slice, a second arbitration control module in the interface control module and a bus control module of the sensor compares the multilevel symbol string with the voltage on the sub-arbitration bus in the sub-bus bit by bit, and if the priority of the multilevel symbol string is higher than the voltage priority on the sub-arbitration bus in the sub-bus, the multilevel symbol is output to the sub-arbitration bus in the sub-bus, simultaneously detecting and comparing first arbitration frames respectively received on a sub fast arbitration bus and a sub slow arbitration bus in a time slice, and if the priority of a multilevel symbol string is lower than the voltage priority on the arbitration bus in the sub bus, retransmitting the multilevel symbol string in the next arbitration time slot;

if the multi-system symbol strings which are transmitted in the first arbitration frame and are respectively received by the sub-fast arbitration bus and the sub-slow arbitration bus in one time slice are completely the same, the sub-slow arbitration bus stops sending the arbitration frame and simultaneously enters the arbitration of the next time slice together with the sub-fast arbitration bus; the interface control module and the bus control module of the sensor of the complete multilevel symbol string are successfully sent through the sub-fast arbitration bus in the first sub-fast arbitration time slot, data transmission is carried out on data to be sent through one group of sub-data buses at the beginning of the next time slice, the interface control module and the bus control module of the sensor of the complete multilevel symbol string are successfully sent through the fast arbitration bus in the second fast arbitration time slot, the data to be sent are transmitted through the other group of sub-data buses at the beginning of the next time slice until all the sub-data buses are distributed, and then arbitration of the next time slice is carried out;

if the multi-system symbol strings which are transmitted in the first arbitration frame respectively received by the sub fast arbitration bus and the sub slow arbitration bus in one time slice are not identical, the sub fast arbitration bus stops the transmission of the arbitration frame until the sub slow arbitration bus finishes the transmission of the arbitration frame in one long time slice, and the multi-system symbol strings and the sub slow arbitration bus enter the arbitration of the next time slice together; and the interface control module and the bus control module of the sensor successfully transmit the complete new multilevel symbol string through the sub-slow arbitration bus at the first sub-slow arbitration time slot, the data to be transmitted is transmitted through a group of sub-data buses at the beginning of the next long time slice, the interface control module and the bus control module of the sensor successfully transmit the complete multilevel symbol string through the sub-slow arbitration bus at the second sub-slow arbitration time slot, the data to be transmitted is transmitted through another group of sub-data buses at the beginning of the next long time slice until all the sub-data buses are distributed, and then the arbitration of the next time slice is started. As a preferred scheme, if the number of times that the control module continuously and successfully sends the data to be sent reaches a set value, the control module reduces the number of times that the multilevel symbol string is output.

As a preferred scheme, the double-rate arbitration relay device is characterized in that the first data transmission module in the interface control module includes an identity recognition module, when the identity recognition module detects identity information of the double-rate arbitration relay device in data received from a central bus, the identity recognition module stores arriving data in a local cache and control module, and forwards the arriving data to a sub-data bus inside a neuron through a bus control module, and when identity information matched with the neuron is not detected, the data received from the central bus is directly discarded.

Preferably, the second data transmission module in the bus control module includes an identity recognition module, when the identity recognition module detects identity information matching with the dual-rate arbitration relay device from data received from a sub-data bus inside the dual-rate arbitration relay device, the identity recognition module stores arriving data in the local cache and control module, and forwards the arriving data to the hub bus through the interface control module, and when identity information matching with the neuron is not detected, the identity recognition module directly discards the data received from the sub-data bus.

Preferably, the control module includes an arbitration circuit, the arbitration circuit including a logical wired-or circuit, the logic wired-OR circuit comprises a field effect tube and a first comparator, the drain electrode of the field effect tube is used as the input end of the logic wired-OR circuit, the grid electrode of the field effect tube is connected with the output end of the first comparator, the source electrode of the field effect tube is used as the output end of a logic line or a circuit, the reverse phase input end of the first comparator is connected with the source electrode of the field effect tube, the non-phase input end of the first comparator is connected with the drain electrode of the field effect tube, if the voltage of the drain electrode of the field effect tube is higher than the voltage of the source electrode of the field effect tube, the first comparator outputs high level to drive the field effect transistor to be conducted, the field effect transistor outputs the input multilevel symbol, otherwise, the first comparator outputs low level, and the field effect transistor is cut off.

Preferably, the logic line or circuit further includes a clearing circuit, the clearing circuit includes a pull-down resistor and a switch tube, one end of the pull-down resistor is connected to the logic line or output end, the other end of the pull-down resistor is connected to the input end of the switch tube, the output end of the switch tube is grounded, the control end of the switch tube is connected to the device of the logic line or input end, and the device controls the switch tube to be turned on when the time slot is over.

Preferably, the arbitration circuit further includes an error elimination circuit, an input terminal of the error elimination circuit is connected to the logic line or circuit output terminal, an output terminal of the error elimination circuit is connected to a device at the logic line or circuit input terminal, and the error elimination circuit includes:

a threshold circuit for providing a plurality of threshold voltages corresponding to the multilevel symbols, the threshold voltages being used to distinguish the different voltage amplitude states;

the regenerative circuit comprises a plurality of second comparators corresponding to the threshold voltage and a plurality of divider resistors, wherein the in-phase input end of each second comparator is connected with the logic line or the output end of the logic line, the reverse phase input end of each second comparator is used for inputting different threshold voltages, the output end of each second comparator is connected with one divider resistor in series, the divider resistors are connected in parallel, the second comparators compare the multilevel symbols with the threshold voltage to generate logic levels, and all the logic levels are divided by the divider resistors to generate standard voltages corresponding to the multilevel symbols;

the equipment compares the standard voltage output by the error elimination circuit with the multilevel symbol output by the error elimination circuit, and if the standard voltage and the multilevel symbol are consistent, the equipment successfully sends the multilevel symbol.

The embodiment disclosed by the invention has the beneficial effects that: the arbitration signal is transmitted by the arbitration bus, and the data to be transmitted is transmitted by the data bus. Therefore, the arbitration bus and the data bus can adopt different rates to transmit data, so that the arbitration bus and the data bus can respectively reach the maximum transmission rate, and the overall data transmission rate is improved. The sensors compete for the first time in the relay equipment, the sensors which compete successfully compete for the second time on the system bus through the relay equipment, the relay equipment divides the arbitration signal into two times for competition, the number of the devices which participate in competition for the single time is reduced, the collision probability of the devices is reduced, and meanwhile, part of wiring is reduced. Meanwhile, considering that overflow risk exists in data to be sent in the cache and the control module, the relay equipment can form a new multi-system symbol string according to the cache data volume, and the priority of the new multi-system symbol string is not lower than that of the original sensor. The arbitration bus is divided into a fast arbitration bus and a slow arbitration bus, because the time slot of the fast arbitration bus is smaller than the time slot of the slow arbitration bus, when the transmission of the multi-system symbol strings of all fast arbitration time slots is completed on the fast arbitration bus in a time slice, the transmission of the multi-system symbol strings of partial slow arbitration time slots is only completed on the slow arbitration bus, at the moment, the first multi-system symbol string is successfully sent in the fast arbitration bus in a time slice and the relay equipment consistent with the partial multi-system symbol strings sent by the slow arbitration bus is successfully sent in the fast arbitration bus, and the to-be-sent data of the relay equipment which successfully transmits the multi-system symbol strings in all arbitration time slots in a time slice of the fast arbitration bus is sequentially sent to one group of data buses at the beginning of the next time slice. And if the transmitted multi-system symbol strings are inconsistent, performing data transmission according to the multi-system symbol strings on the slow arbitration bus. The accuracy of arbitration frame transmission in one time slice of the fast arbitration bus is judged by comparing the accuracy of the first multi-system symbol string, and the multi-system symbol string of the arbitration bus is dynamically selected as a data transmission basis, so that the accuracy and the efficiency of sensor data transmission with different lengths from the bus are ensured. And the arbitration signal is transmitted by using the multi-system symbol string, more information can be transmitted in the same time, and the arbitration bus automatically selects the multi-system symbol with higher voltage amplitude for output, so that the arbitration efficiency is improved.

Drawings

FIG. 1 is a schematic diagram of a dual-rate arbitration relay device for a bus system according to the present invention, wherein an arbitration bus comprises a fast arbitration bus and a slow arbitration bus.

FIG. 2 is a schematic circuit diagram of the logic lines or circuits of the dual rate arbitration relay device of the present invention for use in a bus system.

FIG. 3 is a circuit schematic of the arbitration circuitry of the dual rate arbitration relay device for use in a bus system of the present invention.

Fig. 4 is a schematic structural diagram of a dual-rate arbitration relay device for a bus system according to the present invention, wherein an arbitration bus comprises a fast arbitration bus, a slow arbitration bus and a medium-rate arbitration bus.

Detailed Description

The invention will be further elucidated and described with reference to the embodiments and drawings of the specification:

referring to fig. 1 and 4, the relay device includes a main interface, an interface control module, a cache and control module, a bus control module, a sub-bus, and a plurality of secondary interfaces, wherein the main interface is used for connecting with the main bus, and the secondary interfaces are used for connecting with the sensor connection data bus. The data bus is 3 twisted-pair lines, the fast arbitration bus is divided into 3 fast arbitration time slots in one time slice, the slow arbitration bus is divided into 3 slow arbitration time slots in one long time slice, and the time length of one long time slice is 5 times that of the time slice. The sub data bus and the data bus are identical.

It is emphasized here that the strings of multilevel symbols sent to the sub-fast arbitration bus are sent in the fast arbitration slots at the faster data rate; the multilevel symbol string sent to the slow arbitration bus is sent in the slow arbitration slot at the slower data rate.

The second data transmission module in a receiving state receives data sent to a sub data bus and stores the data in a cache and control module, the second arbitration control module obtains a new multi-system symbol string through weighted calculation according to the received multi-system symbol string corresponding to the received data and the number of data to be sent cached in the cache module, and the priority of the new multi-system symbol string is higher than or equal to that of the originally received multi-system symbol string;

when data in the cache and control module needs to be uploaded through the central hub bus, the interface control module repeatedly sends a new multi-system symbol string to the fast arbitration bus in each fast arbitration time slot in a time slice, and simultaneously repeatedly sends a new multi-system symbol string to the slow arbitration bus in each slow arbitration time slot in a slow time slice.

A first arbitration control module in the interface control module compares the new multi-system symbol string with the voltage on an arbitration bus in a central hub one by one, if the priority of the new multi-system symbol is higher than the voltage priority on an arbitration bus in the central hub, the new multi-system symbol is output to the arbitration bus in the central hub, and simultaneously, first arbitration frames respectively received on a fast arbitration bus and a slow arbitration bus in a time slice are detected and compared.

In this embodiment, the transmission completion rate of one arbitration frame of the slow arbitration bus in one time slice is about 60%, and the transmission completion rate of the multilevel symbol string is slightly higher than 60% and lower than 100%, and if the multilevel symbol strings are completely consistent, all the multilevel symbol strings transmitted by the fast arbitration bus in the 3 fast arbitration time slots in the time slice are considered to be correct. At the beginning of the next time slice, selecting a group of twisted-pair lines for transmitting data to be transmitted of the repeater corresponding to the multi-system symbol strings which are transmitted in the first fast arbitration time slot, selecting a second group of twisted-pair lines for transmitting data to be transmitted of the repeater corresponding to the multi-system symbol strings which are transmitted in the second fast arbitration time slot, and selecting a third group of twisted-pair lines for transmitting data to be transmitted of the repeater corresponding to the multi-system symbol strings which are transmitted in the third arbitration time slot; and if the priority of the multilevel symbol string is lower than the voltage priority on the arbitration bus in the central bus, retransmitting the multilevel symbol string in the next arbitration time slot.

If the partial multi-system symbol strings are not completely consistent, the multi-system symbol strings transmitted by the fast arbitration bus in the 3 fast arbitration time slots in the time slice are considered to be incorrect, and data transmission is carried out according to the multi-system symbol strings transmitted by the slow arbitration bus in the 3 slow arbitration time slots in the slow time slice. At the beginning of the next long time slice, selecting a group of twisted-pair lines for transmitting data to be transmitted of the repeater corresponding to the multilevel symbol string which is transmitted in the first slow arbitration time slot, selecting a second group of twisted-pair lines for transmitting data to be transmitted of the repeater corresponding to the multilevel symbol string which is transmitted in the second slow arbitration time slot, and selecting a third group of twisted-pair lines for transmitting data to be transmitted of the repeater corresponding to the multilevel symbol string which is transmitted in the third slow arbitration time slot; and if the priority of the multilevel symbol string is lower than the voltage priority of the arbitration bus in the central bus, retransmitting the multilevel symbol string in the next arbitration time slot.

The following description will be made with specific numerical values. Taking 10 symbols with the length of the multi-system symbol string; the fast arbitration bus rate is 2.5M symbols per second, and the time slot length of the fast arbitration bus is 5 microseconds; the slow arbitration bus rate is 0.5M symbol per second, and the time slot length is 25 microseconds; three data buses, a time slice of 18 microseconds duration, include 3 fast arbitration slots, and a long time slice of 90 microseconds duration, include 3 slow arbitration slots.

At the beginning of an arbitration time slot, an interface control circuit of a first arbitration control module compares a corresponding multi-system symbol string with the voltage of an arbitration bus bit by bit, if the priority of the multi-system symbol is higher than the priority of the arbitration bus voltage, the multi-system symbol is output to the arbitration bus, if the priority of the multi-system symbol is lower than the priority of the arbitration bus voltage, the transmission of the rest symbols is stopped, and the corresponding first arbitration control module waits for the data line competition of the next arbitration time slot.

And comparing the transmitted multi-system symbol strings of the first arbitration frame on the fast arbitration bus and the slow arbitration bus in a time slice. When in a time slice, 3 arbitration frames on the fast arbitration bus are transmitted within 15 microseconds, while the slow arbitration bus transmits 7.5 symbols within 15 microseconds, that is, the multilevel symbol string of the first slow arbitration frame has a completion rate of only 75%. Thus, during the period of time between the 15 th microsecond and the 18 th microsecond, the interface control circuitry may compare the strings of multilevel symbols that have completed transmission in the first arbitration frame sent on the two different rate arbitration buses.

If the two are completely the same, the multilevel symbol strings successfully transmitted in all the fast arbitration time slots on the fast arbitration bus in the time slice are all considered to be correct. Starting after the next time slice, namely 18 microseconds, the multilevel symbol string corresponds to the data to be sent of the double-rate arbitration sensor, sequentially selecting a group of data buses for transmission until all the data buses are completely distributed, and entering the bus competition of the next time slice after the time slice, namely 18 microseconds, is finished if the double-rate arbitration sensor which is not distributed with the data buses does not exist.

If the two are not identical, the multi-system symbol string transmitted by the slow arbitration bus is used as the basis of data transmission, and starts after the next long time slice, namely 90 microseconds, the multi-system symbol string corresponds to the data to be sent of the double-rate arbitration sensor, one group of data buses are sequentially selected for transmission until all the data buses are completely distributed, and the double-rate arbitration sensor which distributes the data buses does not exist, and then enters the bus competition of the next time slice after the current long time slice, namely 90 microseconds finishes.

In view of the possibility of bus contention failure of the interface control module and the possibility of overflow of the cache data in the cache and the control module, the interface control module generates a new multi-system symbol string according to the amount of the cache data and the re-weighting of the multi-system symbol string, and the priority of the new multi-system symbol string is not lower than that of the original multi-system symbol string.

When a sensor needs to send data to the double-rate arbitration relay device or data needs to be sent to the sensor in the cache and control module of the double-rate arbitration relay device, the data transmission process from the interface control module and the bus control module of the sensor to the sub-bus is consistent with the data transmission principle of the central bus, and details are not repeated here.

Due to the reason of wire length delay, the multilevel symbol strings transmitted on the fast arbitration bus may have a part of the multilevel symbol strings of the devices closer to each other and a part of the multilevel symbol strings of the devices farther from each other, and at this time, the multilevel symbol strings output on the fast arbitration bus are inconsistent with the part of the multilevel symbol strings on the slow arbitration bus, which is equal to the case that no device successfully transmits the multilevel symbol strings on the fast arbitration bus, so the multilevel symbol strings output on the fast arbitration bus are not used as the arbitration result.

The slow arbitration bus can always output correct multi-system symbol strings due to low transmission rate, so that the multi-system symbol strings output on the slow arbitration bus are used as arbitration results. When the multi-system symbol string output by the fast arbitration bus is consistent with the partial multi-system symbol string output by the slow arbitration bus, the multi-system symbol string output by the fast arbitration bus is still used as the arbitration result. The transmission rate of the slow arbitration bus meets the maximum line length delay, the basic transmission rate of the arbitration signal is ensured, and when no device far away from the fast arbitration bus participates in arbitration, the transmission rate of the arbitration signal of the device near the fast arbitration bus can be increased.

Furthermore, if the number of times of the control module continuously and successfully sending the data to be sent reaches a set value, the bus is always occupied, and at this time, the device which does not successfully send the data to be sent is always queued. In order to ensure that the queued devices have an opportunity to send data to be sent, the control module delays for a set time and then sends the multilevel symbol string. Alternatively, the control module may reduce the frequency or probability of transmitting the multilevel symbol string, such as by reducing the transmission probability by ten percent, or by stopping transmission once every several successful transmissions. In short, the number of times of sending the multilevel symbol string by the control module can be reduced. Therefore, the device with lower priority can be effectively prevented from queuing or being incapable of sending data for a long time, each device is ensured to have the opportunity to send data, and the fairness of arbitration is improved.

Furthermore, the first data transmission module in the interface control module includes an identity recognition module, when the identity recognition module detects identity information of the relay device belonging to the dual-rate arbitration in data received from the hub bus, the data is stored in the local cache and control module, and is forwarded to the sub-data bus inside the neuron through the bus control module, and when identity information matched with the neuron is not detected, the data received from the hub bus is directly discarded, that is, the cache and control module of the relay device is ensured to only receive data to be sent, the destination address of which belongs to the range of the relay device.

Furthermore, the second data transmission module in the bus control module comprises an identity recognition module, when the identity recognition module detects identity information matched with the dual-rate arbitration relay device in data received from a sub-data bus in the dual-rate arbitration relay device, the identity recognition module stores the arriving data in a local cache and a control module, and forwards the arriving data to the central bus through an interface control module, and when the identity information matched with the neuron is not detected, the data received from the sub-data bus is directly discarded, so that the data needing to be transmitted to the central bus is cached in a repeater, and the data not needing to be transmitted to the central bus is directly transmitted to a sensor connected to the sub-data bus.

Further, referring to fig. 2, the control module includes an arbitration circuit, the arbitration circuit includes a logic line or circuit, the logic line or circuit includes a field effect transistor and a first comparator, a drain of the field effect transistor is used as an input end of the logic line or circuit, a gate of the field effect transistor is connected to an output end of the first comparator, a source of the field effect transistor is used as an output end of the logic line or circuit, an inverting input end of the first comparator is connected to a source of the field effect transistor, and a non-inverting input end of the first comparator is connected to a drain of the field effect transistor.

If the voltage of the input end of the logic wired-OR circuit is higher than the voltage of the output end of the logic wired-OR circuit, namely the voltage of the in-phase input end of the first comparator is higher than the voltage of the reverse phase input end of the first comparator, the first comparator outputs high level to drive the field effect tube to be conducted, the field effect tube is used as a switch, the conducting voltage of the field effect tube is reduced, the voltage of the output end of the field effect tube is clamped to be slightly smaller than the voltage of the input end of the field effect tube, the field effect tube is equivalent to the field effect tube, the input multi-system symbols are output.

The logic wired-OR circuit further comprises an input buffer, and the output end of the input buffer is connected with the input end of the field effect tube.

The logic line or circuit further comprises a clearing circuit, the clearing circuit comprises a pull-down resistor and a switch tube, one end of the pull-down resistor is connected with the logic line or the output end, the other end of the pull-down resistor is connected with the input end of the switch tube, the output end of the switch tube is grounded, the control end of the switch tube is connected with the logic line or circuit input end, and the switch tube is controlled to be conducted when the time slot is finished by the equipment. The parasitic capacitance exists in the lead in a high-frequency state, which can affect the multilevel symbol output by the logic wire or the circuit subsequently, and the parasitic capacitance is introduced into the conducting switch tube to be eliminated when the time slot is ended, so that the influence of the parasitic capacitance can be avoided when the next time slot is started, namely the next multilevel symbol is output. Normally, a field effect transistor is selected as the switching transistor.

Further, the arbitration circuit further comprises an error elimination circuit, an input end of the error elimination circuit is connected with the logic line or the circuit output end, an output end of the error elimination circuit is connected with the logic line or the circuit input end, and the error elimination circuit comprises:

a threshold circuit for providing a plurality of threshold voltages corresponding to the multilevel symbols, the threshold voltages being used to distinguish states of the different voltage amplitudes;

the regenerative circuit comprises a plurality of second comparators and a plurality of divider resistors, the second comparators are connected with an arbitration bus in a non-inverting input end, the inverting input end of each second comparator is used for inputting different threshold voltages, the output end of each second comparator is connected with one divider resistor in series, the divider resistors are connected in parallel, the second comparators compare the multilevel symbols with the threshold voltages to generate logic levels, all the logic levels are divided by the divider resistors to generate standard voltages corresponding to the multilevel symbols, the standard voltages output by the error elimination circuit are compared with the output multilevel symbols of the logic lines or the equipment at the circuit input end, and if the two are consistent, the equipment successfully sends the multilevel symbols;

and the zero-gain operational amplifier is used for buffering the standard voltage and outputting the standard voltage.

The data bus or the arbitration bus has different data symbol modulation modes and modulation rates. The data bus has a higher symbol modulation rate in view of the data bus being required to achieve a higher data transfer rate, while the arbitration bus has a lower symbol modulation rate in view of the arbitration accuracy and round-trip delay. The data on the data bus may be modulated using any manner of modulation, while the data on the arbitration bus is level modulated. The data buses may adopt any form of data lines for data transmission, such as twisted pair and optical fiber, and each set of data buses are independent of each other and support full-duplex communication.

In the invention, the multi-system symbol string is adopted to transmit the arbitration signal, compared with the binary symbol to transmit the arbitration signal, more information can be transmitted in the same time, and the arbitration efficiency is greatly improved. The specific implementation process is as follows:

referring to fig. 3, it is assumed that three relay devices participate in the priority arbitration.

There are correspondingly three logic wired-or circuits 100 and three error cancellation circuits 200. The output of the logical wired-or circuit 100 is connected to the input of the error cancellation circuit 200, and the output of the error cancellation circuit 200 is connected to the device at the input of the logical wired-or circuit 100.

Since the three error elimination circuits have the same structure, only three logic wired-OR circuits and one error elimination circuit are included in FIG. 3 for convenience of explanation.

The circuit is explained by a 5V logic system, and the multilevel symbol comprises five states, wherein the level 0 is defined to be lower than 1V, and the standard voltage is 0.5V; the level 1 is between 1.1V and 1.9V, and the standard voltage is 1.5V; the level 2 is between 2.1V and 2.9V, and the standard voltage is 2.5V; the level 3 is between 3.1V and 3.9V, and the standard voltage is 3.5V; the voltage of 4.1V or more is level 4, and the standard voltage thereof is 4.5V. Other voltage values are level transition voltages, requiring rounding of the nearest level. When all input ports are not switched in and assume a high impedance state, a level 0 is output by default.

The circuit of this embodiment can be used for arbitration signaling of the penta symbol. Level 0 represents the symbol "0", level 1 represents the symbol "1", and so on.

As can be seen from the above, the multilevel symbol includes four threshold voltages, which are 1V, 2V, 3V and 4V respectively. Correspondingly, the threshold circuit comprises 5 resistors connected in series, each resistor is divided into 1V voltage, and the corresponding threshold voltages are respectively 4V, 3V, 2V and 1V and respectively correspond to nodes 10-13 in FIG. 3.

Correspondingly, the regeneration circuit comprises 4 second comparators and 4 divider resistors, the non-inverting input end of each second comparator is connected with the same multi-system symbol input, the inverting input end of each second comparator is connected with different threshold voltages, the output end of each second comparator is connected with one divider resistor in series, and the divider resistors are connected in parallel. When the voltage of the non-inverting input terminal of the second comparator is larger than that of the inverting input terminal, the second comparator outputs a logic high level, otherwise, the second comparator outputs a logic low level. And the logic high level or the logic low level output by all the second comparators generates standard voltage corresponding to the multilevel symbol after being subjected to voltage division by the voltage division resistors.

It can be known from the circuit of the embodiment that, if deriving the arbitration signal transmission circuit with other multilevel symbols, only the number of the threshold voltages needs to be changed, and the corresponding number change is performed on the comparators and the divider resistors.

In the embodiment, for convenience of understanding, the high level and the low level output by the comparator are 4.5V and 0.5V, and the resistance values of the voltage dividing resistors connected in series with the output end of the comparator are all equal to each other, so that the resistance value is R. It should be noted that, in practice, the high level amplitude, the low level amplitude and the resistance of the divider resistor output by the comparator can be calculated according to the required result.

Assume that node 1 inputs level 3, the reference voltage is 3.5V, node 2 inputs level 2, the reference voltage is 2.5V, and node 3 inputs level 1, and the reference voltage is 1.5V.

From the above analysis, the node 4 is a high level output, and the output voltage of the node 5 is slightly less than 3.5V. I.e. output level 3.

Since 3.5V is only less than the threshold voltage of 4V, node 6 outputs 0.5V low and nodes 7, 8 and 9 all output 4.5V high. The voltage of the output out at this time is:

exactly the standard voltage for level 3. The node controller compares the standard voltage output by the error elimination circuit with the input level, and finally judges that the standard voltage is consistent with the input level of the node 1, and the equipment connected with the node 1 obtains arbitration priority.

Assuming that the first bit level is inputted, the node 1 is inputted with the level 2, the standard voltage is 2.5V, the node 2 is inputted with the level 2, the standard voltage is 2.5V, the node 3 is inputted with the level 1, and the standard voltage is 1.5V. Assume that the level is disturbed during transmission and becomes 2.7V input at node 1, 2.2V input at node 2 and 1.3V input at node 3.

From the above analysis, the node 4 is a high level output, and the output voltage of the node 5 is slightly less than 2.7V. Since 2.7V is greater than 2V and less than 3V, nodes 9 and 8 output 4.5V high and nodes 6 and 7 both output 0.5V low. The voltage of the output out at this time is:

exactly the standard voltage for level 2.

When the second bit level is input, the node 1 inputs the level 4, the standard voltage is 4.5V, the node 2 inputs the level 2, the standard voltage is 2.5V, the node 3 inputs the level 3, and the standard voltage is 3.5V. From the above analysis, it can be seen that the node 4 is a high level output, and the output voltage of the node 5 is slightly less than 4.5V. Assuming that interference is experienced during transmission, 4.5V becomes 4.8V.

Since 4.8V is greater than all threshold voltages, nodes 9, 8, 7 and 6 all output a high level of 4.5V. The voltage of the output out at this time is 4.5V, which is exactly the standard voltage corresponding to level 4. The node controller compares the standard voltage output by the error elimination circuit with the input level, when the first level comparison is carried out, the node 1 and the node 2 are consistent with the input level, the second level comparison is continued, only the node 1 is consistent with the input level, finally, the level input by the node 1 is judged to be consistent, and the equipment connected with the node 1 obtains arbitration priority.

According to the above, the logic line or circuit can select the multilevel symbol with the highest output voltage value, the multilevel symbol generates a plurality of logic levels after passing through the regeneration circuit, and the plurality of logic levels generate the standard voltage corresponding to the multilevel symbol through the divider resistor, namely the multilevel symbol, so that the accuracy of the logic judgment of the digital circuit is ensured, and meanwhile, the on-state voltage of the logic line or circuit is reduced, and more levels in different states can be divided under the same voltage amplitude. The multi-system symbol is compared with the threshold voltage to generate a logic level, and the transmission noise and the error of the multi-system symbol are eliminated firstly. Further, since the multilevel symbol is compared with the threshold voltage, the generated logic level carries the information and characteristics of the multilevel symbol, and the logic level is converted into the standard voltage corresponding to the multilevel symbol according to the information and characteristics. As can be seen from the conventional knowledge, the more levels are divided in the same voltage amplitude, the smaller the voltage difference between the levels of the adjacent states is, which easily causes the logic judgment of the digital circuit to be misplaced. While the circuit uses multilevel to represent the multilevel symbol, the error regeneration circuit eliminates the transmission error of the multilevel symbol and improves the accuracy of the state judgment of the multilevel symbol.

Example two

The difference between the second embodiment and the first embodiment is that:

the data bus is 3 twisted-pair lines, the fast arbitration bus is divided into 3 fast arbitration time slots in one time slice, the slow arbitration bus is divided into 3 slow arbitration time slots in one long time slice, and the time length of one long time slice is 3 times that of the time slice. The sub data bus and the data bus are identical.

In this embodiment, the transmission completion rate of one arbitration frame of the slow arbitration bus in one time slice is 100%, so the transmission completion rate of the multilevel symbol string is also 100%, and if the multilevel symbol strings are completely consistent, all the multilevel symbol strings transmitted by the fast arbitration bus in the 3 fast arbitration time slots in the time slice are considered to be correct. At the beginning of the next time slice, selecting a group of twisted-pair lines for transmitting data to be transmitted of the repeater corresponding to the multi-system symbol strings which are transmitted in the first fast arbitration time slot, selecting a second group of twisted-pair lines for transmitting data to be transmitted of the repeater corresponding to the multi-system symbol strings which are transmitted in the second fast arbitration time slot, and selecting a third group of twisted-pair lines for transmitting data to be transmitted of the repeater corresponding to the multi-system symbol strings which are transmitted in the third arbitration time slot; and if the priority of the multilevel symbol string is lower than the voltage priority on the arbitration bus in the central bus, retransmitting the multilevel symbol string in the next arbitration time slot.

The following description will be made with specific numerical values. Taking 10 symbols with the length of the multi-system symbol string; the fast arbitration bus rate is 2.5M symbols per second, and the time slot length of the fast arbitration bus is 5 microseconds; the slow arbitration bus rate is 1M symbol per second, and the time slot length is 14 microseconds; three data buses, the time slice lasts for 16 microseconds and comprises 3 fast arbitration time slots, and the long time slice lasts for 48 microseconds and comprises 3 slow arbitration time slots;

at the beginning of an arbitration time slot, an interface control circuit of a first arbitration control module compares a corresponding multi-system symbol string with the voltage of an arbitration bus bit by bit, if the priority of the multi-system symbol is higher than the priority of the arbitration bus voltage, the multi-system symbol is output to the arbitration bus, if the priority of the multi-system symbol is lower than the priority of the arbitration bus voltage, the transmission of the rest symbols is stopped, and the corresponding first arbitration control module waits for the data line competition of the next arbitration time slot.

And comparing the transmitted multi-system symbol strings of the first arbitration frame on the fast arbitration bus and the slow arbitration bus in a time slice. When the transmission of the first arbitration frame on the slow arbitration bus ends, the 10 symbols last 10 microseconds, shorter than the slot length of the slow arbitration bus, 14 microseconds, and shorter than the duration of the time slice, 16 microseconds. The first arbitration frame on the fast arbitration bus is now transmitted within 4 microseconds. Thus, during the period of time from 10 microseconds to 16 microseconds, the interface control circuit may compare 10 multilevel symbol strings of the same content sent on two arbitration buses of different rates.

If the two are completely the same, the multilevel symbol strings successfully transmitted in all the fast arbitration time slots on the fast arbitration bus in the time slice are all considered to be correct. Starting after the next time slice, namely 16 microseconds, the multilevel symbol string corresponds to the data to be sent of the double-rate arbitration sensor, sequentially selecting a group of data buses for transmission until all the data buses are completely distributed, and entering the bus competition of the next time slice after the time slice, namely 16 microseconds, is finished if the double-rate arbitration sensor which is not distributed with the data buses does not exist.

If the two are not identical, the multi-system symbol string transmitted by the slow arbitration bus is used as the basis of data transmission, and starts after the next long time slice, namely 48 microseconds, the multi-system symbol string corresponds to the data to be sent of the double-rate arbitration sensor, one group of data buses are sequentially selected for transmission until all the data buses are completely distributed, and the double-rate arbitration sensor which distributes the data buses does not exist, and then enters the bus competition of the next time slice after the current long time slice, namely 48 microseconds finishes.

In the two embodiments, if the arbitration result of the slow arbitration bus is used as the data transmission basis, a time slice can be used for transmitting the data frame at the beginning of the next long time slice, or a long time slice can be used for transmitting the data frame, so that the dynamic rate transmission of the data bus is realized, and the accuracy of long-distance data transmission is guaranteed.

EXAMPLE III

The difference between the third embodiment and the first embodiment is that:

referring to fig. 1 and 4, the double-rate arbitration relay device for the bus system further includes a medium-rate arbitration bus, and the time slot length of the medium-rate arbitration bus is greater than that of the fast-rate arbitration bus and smaller than that of the slow-rate arbitration bus. The sub-bus also comprises a sub-medium speed arbitration bus, and the functions of the sub-bus and the central bus are completely the same.

And if the first multi-system symbol string output to the fast arbitration bus in the time slice is not consistent with the first multi-system symbol string output to the slow arbitration bus after transmission, comparing the multi-system symbol string output to the medium-speed arbitration bus with the multi-system symbol string output to the slow arbitration bus, and if the two are consistent, outputting the multi-system symbol string output to the medium-speed arbitration bus as an arbitration result.

The transmission rate of the slow arbitration bus meets the maximum line length delay, the basic transmission rate of the arbitration signal is ensured, when no device far away from the fast arbitration bus participates in arbitration, the transmission rate of the arbitration signal of the device near the fast arbitration bus can be increased, and the transmission rate of the arbitration signal of the device with medium distance is increased by the medium arbitration bus.

Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the protection scope of the present invention, although the present invention is described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions can be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims (6)

1. A dual rate arbitration relay device for use in a bus system, characterized by: the system comprises a main interface, an interface control module, a cache and control module, a bus control module, a sub-bus and a plurality of secondary interfaces, wherein the main interface is used for being connected with a central bus, and the secondary interfaces are used for being connected with a sensor;

the interface control module comprises a first arbitration control module and a first data transmission module, and the first arbitration control module and the first data transmission module are respectively connected with the central bus and the cache and control module; the bus control module comprises a second arbitration control module and a second data transmission module, and the second arbitration control module and the second data transmission module are respectively connected with the sub-bus and the cache and control module;

the central bus and the sub-buses have the same functional structure and respectively comprise: a slow arbitration bus, a fast arbitration bus and a data bus;

the data bus at least comprises 2 pairs of copper twisted pairs, and data to be sent is transmitted in a time slice through a data frame, wherein the time slice is the duration time required by the data bus for transmitting one data frame;

the fast arbitration bus transmits a multilevel symbol string in a fast arbitration time slot in the time slice through an arbitration frame, the fast arbitration time slot is the duration time required by the fast arbitration bus to transmit an arbitration frame, and the number of the fast arbitration time slot contained in one time slice is not less than the number of twisted wire pairs in the data bus; the multilevel symbols are represented by multilevel, comprising different voltage amplitude states separated by a plurality of thresholds, the higher the voltage amplitude the higher the priority;

the slow arbitration bus transmits a multilevel symbol string in a slow arbitration time slot in a long time slice through an arbitration frame, the slow arbitration time slot is the duration time required by the slow arbitration bus to transmit one arbitration frame, the slow arbitration time slot is longer than 2 times of the fast arbitration time slot, the long time slice is the duration time of a plurality of slow arbitration time slots, the number of the slow arbitration time slots is not less than the number of twisted wire pairs in the data bus, and the duration time of the long time slice is usually longer than 2 times of the duration time of the time slice;

the second data transmission module in a receiving state receives data sent to a sub data bus and stores the data in a cache and control module, the second arbitration control module obtains a new multi-system symbol string through weighted calculation according to the received multi-system symbol string corresponding to the received data and the number of data to be sent cached in the cache module, and the priority of the new multi-system symbol string is higher than or equal to that of the originally received multi-system symbol string;

when data in the cache and control module needs to be uploaded through the central hub bus, the interface control module repeatedly sends a new multi-system symbol string to the fast arbitration bus in each fast arbitration time slot in a time slice, and simultaneously repeatedly sends a new multi-system symbol string to the slow arbitration bus in each slow arbitration time slot in a long time slice, a first arbitration control module in the interface control module compares the new multi-system symbol string with the voltage on the arbitration bus in the central hub one by one, if the priority of the new multi-system symbol is higher than the voltage priority on the arbitration bus in the central hub, the new multi-system symbol is output to the arbitration bus in the central hub, and simultaneously detects and arbitrates the first arbitration frame respectively received on the fast arbitration bus and the slow arbitration bus in a time slice, and if the priority of the new multi-system symbol is lower than the voltage priority on the arbitration bus in the central hub, suspending the transmission of the subsequent unsent symbols of the new multilevel symbol string and retransmitting the new multilevel symbol string at the next arbitration time slot;

if the transmitted multi-system symbol strings in the first arbitration frame respectively received by the fast arbitration bus and the slow arbitration bus in one time slice are completely the same, the slow arbitration bus stops sending the arbitration frame and the fast arbitration bus simultaneously enters the arbitration of the next time slice; the interface control module successfully sends the complete multilevel symbol string through the fast arbitration bus at the first fast arbitration time slot, selects a group of data buses for data transmission through the data transmission module for the data to be uploaded in the cache and control module at the beginning of the next time slice, and successfully sends the complete new multilevel symbol string through the fast arbitration bus at the second fast arbitration time slot, selects another group of data buses for data transmission through the data transmission module for the data to be uploaded in the beginning cache and control module of the next time slice until all the data buses are completely distributed, and then enters the arbitration of the next time slice;

if the new multi-system symbol strings which are transmitted in the first arbitration frame detected from the fast arbitration bus and the slow arbitration bus are not identical, the fast arbitration bus stops the transmission of the arbitration frame until the slow arbitration bus finishes the transmission of the arbitration frame of a long time slice, and enters the arbitration of the next time slice together with the slow arbitration bus; the interface control module successfully sends the complete multilevel symbol string through the slow arbitration bus in the first slow arbitration time slot, selects one group of data buses for data transmission through the data transmission module for the data to be uploaded in the cache and control module at the beginning of the next slow time slice, and successfully sends the complete new multilevel symbol string through the slow arbitration bus in the second slow arbitration time slot, and selects the other group of data buses for data transmission through the data transmission module at the beginning of the next slow time slice until all the data buses are completely distributed, and then the interface control module enters the arbitration of the next time slice;

when a sensor needs to send data to the double-rate arbitration relay equipment or a cache and a control module of the double-rate arbitration relay equipment needs to send data to the sensor, an interface control module and a bus control module of the sensor repeatedly send a multilevel symbol string to a sub-fast arbitration bus in each fast arbitration time slot in a time slice, and simultaneously repeatedly send the multilevel symbol string to the sub-slow arbitration bus in each slow arbitration time slot in a slow time slice, a second arbitration control module in the interface control module and the bus control module of the sensor compares the multilevel symbol string with the voltage on the sub-arbitration bus bit by bit, if the priority of the multilevel symbol is higher than the voltage priority on the sub-arbitration bus in the sub-bus, the multilevel symbol is output to the sub-arbitration bus in the sub-bus, and the second arbitration control module respectively received on the sub-fast arbitration bus and the sub-slow arbitration bus in the time slice are detected and compared at the same time An arbitration frame, if the priority of the multilevel symbol is lower than the voltage priority of the arbitration bus in the sub-bus, suspending the transmission of the subsequent unsent symbol of the multilevel symbol string, and retransmitting the multilevel symbol string in the next arbitration time slot;

if the multi-system symbol strings which are transmitted in the first arbitration frame and are respectively received by the sub-fast arbitration bus and the sub-slow arbitration bus in one time slice are completely the same, the sub-slow arbitration bus stops sending the arbitration frame and simultaneously enters the arbitration of the next time slice together with the sub-fast arbitration bus; the method comprises the steps that an interface control module and a bus control module of a sensor of a complete multilevel system symbol string are successfully sent through a sub-fast arbitration bus in a first sub-fast arbitration time slot, data transmission is carried out on data to be sent through a group of sub-data buses at the beginning of the next time slice, the interface control module and the bus control module of the sensor of the complete multilevel system symbol string are successfully sent through the fast arbitration bus in a second sub-fast arbitration time slot, the data to be sent are transmitted through another group of sub-data buses at the beginning of the next time slice, and arbitration of the next time slice is carried out until all the sub-data buses are distributed completely;

if the multi-system symbol strings which are transmitted in the first arbitration frame respectively received by the sub fast arbitration bus and the sub slow arbitration bus in one time slice are not identical, the sub fast arbitration bus stops the transmission of the arbitration frame until the sub slow arbitration bus finishes the transmission of the arbitration frame in one time slice, and the multi-system symbol strings and the sub slow arbitration bus enter the arbitration of the next time slice together; and the interface control module and the bus control module of the sensor successfully send the complete multilevel symbol string through the sub-slow arbitration bus at the first sub-slow arbitration time slot, the data to be sent is transmitted through one group of sub-data buses at the beginning of the next long time slice, the interface control module and the bus control module of the sensor successfully send the complete multilevel symbol string through the sub-slow arbitration bus at the second sub-slow arbitration time slot, the data to be sent is transmitted through the other group of sub-data buses at the beginning of the next long time slice until all the sub-data buses are distributed, and then the arbitration of the next time slice is started.

2. The apparatus as claimed in claim 1, wherein the first data transmission module of the interface control module comprises an identification module, when the identification module detects the identification information of the dual-rate arbitration relay apparatus from the data received from the hub bus, the identification module stores the arriving data in the local cache and control module, and forwards the arriving data to the sub data bus inside the neuron through the bus control module, and when the identification information matching with the neuron is not detected, the identification module directly discards the data received from the hub bus.

3. The relay device as claimed in claim 1 or 2, wherein the second data transmission module of the bus control module comprises an identification module, when the identification module detects the identity information matching with the dual-rate arbitration relay device from the data received from the sub-data bus inside the relay device, the identification module stores the arriving data in the local cache and control module, and forwards the arriving data to the hub bus via the interface control module, and when the identity information matching with the neuron is not detected, the identification module directly discards the data received from the sub-data bus.

4. The dual-rate arbitration relay device for bus system as claimed in claim 1, wherein said arbitration control module comprises an arbitration circuit, said arbitration circuit comprises a logic wired-OR circuit, said logic wired-OR circuit comprises a fet and a first comparator, said fet drain is used as logic wired-OR circuit input, said fet gate is connected to first comparator output, said fet source is used as logic wired-OR circuit output, said first comparator inverting input is connected to fet source, said first comparator non-inverting input is connected to fet drain, if said fet drain voltage is higher than said fet source voltage, said first comparator output high level drives fet to conduct, said fet outputs an input multilevel symbol, otherwise, the first comparator outputs low level, and the field effect tube is cut off.

5. The dual-rate arbitration relay device for use in a bus system as recited in claim 4 wherein said logic wired-OR circuit further comprises a clearing circuit, said clearing circuit comprising a pull-down resistor and a switch tube, wherein one end of said pull-down resistor is connected to a logic wired-OR output terminal, the other end of said pull-down resistor is connected to an input terminal of said switch tube, an output terminal of said switch tube is connected to ground, a control terminal of said switch tube is connected to a device at the logic wired-OR input terminal, said device controls the switch tube to conduct at the end of a time slot.

6. The dual rate arbitration relay device for use in a bus system of claim 4 wherein said arbitration circuit further comprises an error cancellation circuit, an input of said error cancellation circuit being connected to a logical wired-OR circuit output, an output of said error cancellation circuit being connected to a device at said logical wired-OR circuit input, said error cancellation circuit comprising:

a threshold circuit for providing a plurality of threshold voltages corresponding to the multilevel symbols, the threshold voltages being used to distinguish the different voltage amplitude states;

the regenerative circuit comprises a plurality of second comparators corresponding to the threshold voltage and a plurality of divider resistors, wherein the in-phase input end of each second comparator is connected with the logic line or the output end of the logic line, the reverse phase input end of each second comparator is used for inputting different threshold voltages, the output end of each second comparator is connected with one divider resistor in series, the divider resistors are connected in parallel, the second comparators compare the multilevel symbols with the threshold voltages to generate logic levels, and all the logic levels are divided by the divider resistors to generate standard voltages corresponding to the multilevel symbols;

the equipment compares the standard voltage output by the error elimination circuit with the multilevel symbol output by the error elimination circuit, and if the standard voltage and the multilevel symbol are consistent, the equipment successfully sends the multilevel symbol.

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