CN111464052B - Novel rectifier circuit for wireless NFC energy collection - Google Patents
Novel rectifier circuit for wireless NFC energy collection Download PDFInfo
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- CN111464052B CN111464052B CN202010396042.7A CN202010396042A CN111464052B CN 111464052 B CN111464052 B CN 111464052B CN 202010396042 A CN202010396042 A CN 202010396042A CN 111464052 B CN111464052 B CN 111464052B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
- H02M7/02—Conversion of AC power input into DC power output without possibility of reversal
- H02M7/04—Conversion of AC power input into DC power output without possibility of reversal by static converters
- H02M7/12—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/21—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/217—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J50/00—Circuit arrangements or systems for wireless supply or distribution of electric power
- H02J50/10—Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling
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Abstract
The invention belongs to the technical field of rectifier circuits, and particularly relates to a novel rectifier circuit for wireless NFC energy collection, which comprises a Vin + end, a Vin-end and a Vout end, and further comprises capacitors C1, C2, C3, C4, C5, C6, C7, C8 and COUT, PMOS tubes MP1, MP2, MP3, MP4, MP5 and MP6, NMOS tubes MN1, MN2, MN3, MN4, MN5 and MN 6.
Description
Technical Field
The invention relates to the technical field of rectifier circuits, in particular to a novel rectifier circuit for wireless NFC energy collection.
Background
The wireless radio frequency energy collection technology is a technology for collecting spatial wireless radiation energy through a specific circuit structure, and storing and processing the energy to drive other circuits to work. In the related circuit structure, the rectifier circuit at the front end is responsible for rectifying the wireless radiation voltage waveform of alternating current into a direct current signal, and is the most core module for determining the performance and efficiency of the whole energy acquisition circuit structure. As shown in fig. 1, is a typical rectifier circuit configuration for rf energy harvesting.
The diode-type rectifier shown in fig. 1 is generally implemented by using a schottky diode, but such a diode is not easily available in a general Common Metal Oxide Semiconductor (CMOS) process, and is generally implemented by using a discrete diode device outside a chip, which increases system cost and PCB area.
Fig. 2 shows a conventional rectifier structure implemented by using MOS transistors, i.e., a cross-connection structure. The structure only uses MOS tubes and is completely compatible with the common CMOS process.
In the structure of the conventional rectifier circuit, the amplitude of the output voltage is lost by a diode drop or a threshold voltage drop, thereby reducing the output efficiency.
Disclosure of Invention
The invention aims to provide a novel rectifier circuit for wireless NFC energy collection, and the novel rectifier circuit is used for solving the problem that the output efficiency is reduced due to the fact that the amplitude of output voltage is subjected to loss of diode voltage drop or threshold voltage drop in the existing rectifier circuit provided in the background art.
In order to achieve the purpose, the invention provides the following technical scheme: a novel rectifier circuit for wireless NFC energy collection comprises a Vin + end, a Vin-end, a Vout end, capacitors C1, C2, C3, C4, C5, C6, C7, C8, COUT, PMOS tubes MP1, MP2, MP3, MP4, MP5, MP6, NMOS tubes MN1, MN2, MN3, MN4, MN5 and MN 6;
the Vin + end is connected with a capacitor C1 and a capacitor C5 through two leads respectively, the other end of the capacitor C1 is connected with the S pole of a PMOS tube MP1 and the D pole of an NMOS tube MN1 through leads, the D pole of the PMOS tube MP1 is connected with the Vout end, the S pole of the NMOS tube MN1 is connected with the S pole and the Vin-end of the PMOS tube MP4 through leads, the D pole of the PMOS tube MP4 is connected with the other end of the capacitor C5, one end of the capacitor C4 is connected with one end of a capacitor C8, the other ends of the capacitors C4 and C8 are connected with two ends of a capacitor COUT, one end of the capacitor COUT is connected with the Vout end, the other end of the capacitor COUT is connected with the D pole of the NMOS tube 4, and the S pole of the NMOS tube MN4 is connected with the D pole of the PMOS tube MP 4;
the Vin-end is further connected with one end of capacitors C3 and C7, the other end of the capacitors C3 and C7 is respectively connected with the D pole of a PMOS tube MP3 and the D pole of an NMOS tube MN6, the S pole of the PMOS tube MP3 is connected with the D pole of a PMOS tube MP1, the S pole of the NMOS tube MN6 is connected with the D pole of an NMOS tube MN4, the G pole of the PMOS tube MP4 is connected with the other end of the capacitor C7, the D pole and the G pole of the NMOS tube MN6, the G pole and the D pole of a PMOS tube MP6, the S pole of the PMOS tube MP6 is connected with the Vin-end, the G pole of the NMOS tube MN1 is connected with the other end of the capacitor C3, the D pole of the PMOS tube MP3, the G pole and the D pole of the NMOS tube MN3, the S pole of the NMOS tube MN3 is connected with the Vin-3636 1, the G pole of the PMOS tube MP 72 is connected with the S pole of the PMOS tube MN2, the PMOS tube MP pole of the PMOS tube MP 72, the PMOS tube MP pole 2, and the D pole of the PMOS tube 2, the two ends of the capacitor C2 are respectively connected with a D pole of a PMOS tube MP1 and a D pole of an NMOS tube MN2, an S pole of the NMOS tube MN2 is connected with a Vin-end, a G pole of the NMOS tube MN4 is connected with a G pole and a D pole of an NMOS tube MN5, a G pole and a D pole of a PMOS tube MP5 are connected with the capacitor C6, the other end of the capacitor C6 and the S pole of an NMOS tube MN5 are connected with the D pole of the NMOS tube MN4, and the S pole of the PMOS tube MP5 is connected with the Vin-end.
Preferably, the PMOS transistor MP1 and the PMOS transistor MP2 are PMOS transistors with the same size.
Preferably, the NMOS transistor MN2 is an NMOS transistor with a channel length greater than a channel width.
Preferably, the NMOS transistor MN2 provides bias voltage for the PMOS transistor MP1 and the PMOS transistor MP2 and stores the bias voltage in the capacitor C2.
Preferably, the NMOS transistor MN1, the PMOS transistor MP4, and the NMOS transistor MN4 are all configured with a threshold-voltage cancellation circuit.
Compared with the prior art, the invention has the beneficial effects that:
this scheme does not use the schottky diode, and only uses electric capacity and MOS pipe, and totally compatible ordinary CMOS technology compares in traditional MOS cast rectifier, can eliminate the influence of the threshold value pressure drop of MOS pipe, and for traditional structure, this structure can promote the voltage of rectification output for output conversion efficiency is showing the improvement than traditional structure, and under equal condition, efficiency can promote and be close one time.
Drawings
FIG. 1 is a schematic diagram of a circuit structure employing a Schottky type diode;
FIG. 2 is a schematic diagram of a rectifier circuit using MOS transistors;
fig. 3 is a schematic diagram of the circuit of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention.
Example (b):
referring to fig. 1, the present invention provides a technical solution: a novel rectifier circuit for wireless NFC energy collection comprises a Vin + end, a Vin-end, a Vout end, capacitors C1, C2, C3, C4, C5, C6, C7, C8, COUT, PMOS tubes MP1, MP2, MP3, MP4, MP5, MP6, NMOS tubes MN1, MN2, MN3, MN4, MN5 and MN 6;
the Vin + end is connected with a capacitor C1 and a capacitor C5 through two leads respectively, the other end of the capacitor C1 is connected with the S pole of a PMOS tube MP1 and the D pole of an NMOS tube MN1 through leads, the D pole of the PMOS tube MP1 is connected with the Vout end, the S pole of the NMOS tube MN1 is connected with the S pole and the Vin-end of the PMOS tube MP4 through leads, the D pole of the PMOS tube MP4 is connected with the other end of the capacitor C5, one end of the capacitor C4 is connected with one end of a capacitor C8, the other ends of the capacitors C4 and C8 are connected with two ends of a capacitor COUT, one end of the capacitor COUT is connected with the Vout end, the other end of the capacitor COUT is connected with the D pole of the NMOS tube 4, and the S pole of the NMOS tube MN4 is connected with the D pole of the PMOS tube MP 4;
the Vin-end is further connected with one end of capacitors C3 and C7, the other end of the capacitors C3 and C7 is respectively connected with the D pole of a PMOS tube MP3 and the D pole of an NMOS tube MN6, the S pole of the PMOS tube MP3 is connected with the D pole of a PMOS tube MP1, the S pole of the NMOS tube MN6 is connected with the D pole of an NMOS tube MN4, the G pole of the PMOS tube MP4 is connected with the other end of the capacitor C7, the D pole and the G pole of the NMOS tube MN6, the G pole and the D pole of a PMOS tube MP6, the S pole of the PMOS tube MP6 is connected with the Vin-end, the G pole of the NMOS tube MN1 is connected with the other end of the capacitor C3, the D pole of the PMOS tube MP3, the G pole and the D pole of the NMOS tube MN3, the S pole of the NMOS tube MN3 is connected with the Vin-3636 1, the G pole of the PMOS tube MP 72 is connected with the S pole of the PMOS tube MN2, the PMOS tube MP pole of the PMOS tube MP 72, the PMOS tube MP pole 2, and the D pole of the PMOS tube 2, the two ends of the capacitor C2 are respectively connected with a D pole of a PMOS tube MP1 and a D pole of an NMOS tube MN2, an S pole of the NMOS tube MN2 is connected with a Vin-end, a G pole of the NMOS tube MN4 is connected with a G pole and a D pole of an NMOS tube MN5, a G pole and a D pole of a PMOS tube MP5 are connected with the capacitor C6, the other end of the capacitor C6 and the S pole of an NMOS tube MN5 are connected with the D pole of the NMOS tube MN4, and the S pole of the PMOS tube MP5 is connected with the Vin-end.
Further, the PMOS transistor MP1 and the PMOS transistor MP2 are PMOS transistors with the same size.
Further, the NMOS transistor MN2 is an NMOS transistor with a channel length greater than a channel width.
Further, the NMOS transistor MN2 provides bias voltage for the PMOS transistor MP1 and the PMOS transistor MP2, and stores the bias voltage in the capacitor C2.
Further, the NMOS transistor MN1, the PMOS transistor MP4, and the NMOS transistor MN4 are all configured with a threshold-on voltage cancellation circuit.
As shown in fig. 1, the relationship between the output and the input of a diode rectifier implemented using schottky type diodes is expressed by the following equation:
Vout＝2*(Vin-Vd)
vin in the above equation is the peak value of the input signal, Vd is the forward conduction voltage drop of the diode, and Vout is the output dc voltage.
In the rectifier structure implemented by using MOS transistors shown in fig. 2, when an input signal with a differential amplitude of Vin is input, the output expression can be expressed as:
Vout＝2*Vin-Vthp-Vthn
wherein Vthp and Vthn are threshold voltages of the PMOS transistor and the NMOS transistor, respectively.
The working principle is as follows:
this scheme compares in traditional MOS cast rectifier, can eliminate the influence of the threshold value pressure drop of MOS pipe for output voltage can be expressed by the following formula:
Vout＝2*Vin
namely, for traditional structure, this structure can promote the voltage of rectification output for output conversion efficiency is showing the improvement than traditional structure, and under the same conditions, efficiency can promote and be close one time.
On the basis of the traditional MOS tube type rectifier, a threshold voltage drop elimination technology is introduced, as shown in figure 3.
When the input signal is in positive phase, i.e. the Vin + terminal is larger than the Vin-terminal, the Vin + terminal reaches the capacitor C4 through the capacitor C1 and the PMOS transistor MP1, and returns to the Vin-terminal to form the upper half of the signal closed loop. Meanwhile, the Vin + end returns to the Vin-end through a capacitor C5 and a PMOS tube MP4 to form a signal closed loop at the lower half part;
when the input signal is in negative phase, i.e. the Vin + terminal is smaller than the Vin-terminal, the Vin-terminal reaches the Vin + terminal through the NMOS transistor MN1 and the capacitor C1, forming the upper half of the signal closed loop. Meanwhile, the Vin-terminal returns to the Vin + terminal through the capacitor C8, the NMOS transistor MN4 and the capacitor C5 to form a lower half part of a closed signal loop.
The PMOS transistor MP1 and the PMOS transistor MP2 are PMOS transistors with the same size, the NMOS transistor MN2 is an NMOS transistor with the channel length larger than the channel width, and can provide bias voltage for the PMOS transistor MP1 and the PMOS transistor MP2 and store the bias voltage on the capacitor C2, so that the influence of threshold opening voltage of the PMOS transistor MP1 can be eliminated. The rest of the NMOS transistor MN1, the PMOS transistor MP4, and the NMOS transistor MN4 are all equipped with corresponding threshold-voltage-to-turn-on-voltage cancellation circuits, which can cancel the threshold voltage required for turning on the transistors.
While there have been shown and described the fundamental principles and essential features of the invention and advantages thereof, it will be apparent to those skilled in the art that the invention is not limited to the details of the foregoing exemplary embodiments, but is capable of other specific forms without departing from the spirit or essential characteristics thereof; the present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein, and any reference signs in the claims are not intended to be construed as limiting the claim concerned.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (5)
1. A novel rectifier circuit for wireless NFC energy harvesting comprises a Vin + terminal, a Vin-terminal and a Vout terminal, and is characterized in that: the high-power LED lamp also comprises capacitors C1, C2, C3, C4, C5, C6, C7, C8, COUT, PMOS tubes MP1, MP2, MP3, MP4, MP5 and MP6, NMOS tubes MN1, MN2, MN3, MN4, MN5 and MN 6;
the Vin + end is connected with a capacitor C1 and a capacitor C5 through two leads respectively, the other end of the capacitor C1 is connected with the S pole of a PMOS tube MP1 and the D pole of an NMOS tube MN1 through leads, the D pole of the PMOS tube MP1 is connected with the Vout end, the S pole of the NMOS tube MN1 is connected with the S pole and the Vin-end of the PMOS tube MP4 through leads, the D pole of the PMOS tube MP4 is connected with the other end of the capacitor C5, one end of the capacitor C4 is connected with one end of a capacitor C8, the other ends of the capacitors C4 and C8 are connected with two ends of a capacitor COUT, one end of the capacitor COUT is connected with the Vout end, the other end of the capacitor COUT is connected with the D pole of the NMOS tube 4, and the S pole of the NMOS tube MN4 is connected with the D pole of the PMOS tube MP 4;
the Vin-end is further connected with one end of capacitors C3 and C7, the other end of the capacitors C3 and C7 is respectively connected with the D pole of a PMOS tube MP3 and the D pole of an NMOS tube MN6, the S pole of the PMOS tube MP3 is connected with the D pole of a PMOS tube MP1, the S pole of the NMOS tube MN6 is connected with the D pole of an NMOS tube MN4, the G pole of the PMOS tube MP4 is connected with the other end of the capacitor C7, the D pole and the G pole of the NMOS tube MN6, the G pole and the D pole of a PMOS tube MP6, the S pole of the PMOS tube MP6 is connected with the Vin-end, the G pole of the NMOS tube MN1 is connected with the other end of the capacitor C3, the D pole of the PMOS tube MP3, the G pole and the D pole of the NMOS tube MN3, the S pole of the NMOS tube MN3 is connected with the Vin-3636 1, the G pole of the PMOS tube MP 72 is connected with the S pole of the PMOS tube MN2, the PMOS tube MP pole of the PMOS tube MP 72, the PMOS tube MP pole 2, and the D pole of the PMOS tube 2, the two ends of the capacitor C2 are respectively connected with a D pole of a PMOS tube MP1 and a D pole of an NMOS tube MN2, an S pole of the NMOS tube MN2 is connected with a Vin-end, a G pole of the NMOS tube MN4 is connected with a G pole and a D pole of an NMOS tube MN5, a G pole and a D pole of a PMOS tube MP5 are connected with the capacitor C6, the other end of the capacitor C6 and the S pole of an NMOS tube MN5 are connected with the D pole of the NMOS tube MN4, and the S pole of the PMOS tube MP5 is connected with the Vin-end.
2. The novel rectifier circuit for wireless NFC energy harvesting of claim 1, wherein: the PMOS tube MP1 and the PMOS tube MP2 are PMOS tubes with the same size.
3. The novel rectifier circuit for wireless NFC energy harvesting of claim 1, wherein: the NMOS transistor MN2 is an NMOS transistor with the channel length larger than the channel width.
4. The novel rectifier circuit for wireless NFC energy harvesting of claim 3, wherein: the NMOS transistor MN2 provides bias voltage for the PMOS transistor MP1 and the PMOS transistor MP2 and stores the bias voltage in the capacitor C2.
5. The novel rectifier circuit for wireless NFC energy harvesting of claim 1, wherein: and the NMOS transistor MN1, the PMOS transistor MP4 and the NMOS transistor MN4 are all provided with a threshold value starting voltage elimination circuit.
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Effective date of registration: 20240628 Address after: Room 524, 5th Floor, Building 1, No. 1318 Xiangda East Road, Qingpu District, Shanghai, 201799 Patentee after: Shanghai Duojing Industrial Co.,Ltd. Country or region after: China Address before: Room 1305, 13th Floor, Phase I, Guoyu Building, No. 8 Dongwu North Road, Wuzhong District, Suzhou City, Jiangsu Province, 215000 Patentee before: Suzhou Xinda Microelectronics Technology Co.,Ltd. Country or region before: China |