CN111446955B

CN111446955B - Pre-coding swing controllable low-power consumption SST driver

Info

Publication number: CN111446955B
Application number: CN202010379074.6A
Authority: CN
Inventors: 周健军; 金晶; 康昊鹏
Original assignee: Jiangsu Jicui Intelligent Integrated Circuit Design Technology Research Institute Co ltd
Current assignee: Jiangsu Jicui Intelligent Integrated Circuit Design Technology Research Institute Co ltd
Priority date: 2020-05-07
Filing date: 2020-05-07
Publication date: 2023-07-14
Anticipated expiration: 2040-05-07
Also published as: CN111446955A

Abstract

The invention relates to a low-power consumption SST driver with a controllable precoding swing, which comprises an SST driving circuit and a coding circuit. The SST driving circuit comprises an output resistor and shunt resistors connected in parallel at two ends of the output resistor, and the number of slices of a main tap in the SST driving circuit is adjustable; the coding circuit is used for coding the data type and driving the SST driving circuit, and comprises a latch group, a logic gate group and a selector group, wherein the latch group outputs four paths of signals, and the logic gate group is arranged at the front stage of the selector group. The invention can further reduce the power consumption, improve the eye diagram quality, is easy to adjust the swing amplitude, and is suitable for being applied to high-speed serial link communication.

Description

Pre-coding swing controllable low-power consumption SST driver

Technical Field

The invention belongs to the technical field of high-speed serial communication, and particularly relates to a low-power consumption SST driver with a controllable precoding swing.

Background

In high-speed serial communications, SST and CML are the main two drive configurations. The SST Driver has more advantages in power consumption, and the conventional SST Driver also has a certain optimization space in power consumption, because the conventional SST Driver divides the z total Driver into a plurality of sub units which are connected in parallel, and the feedforward equalization function (FFE) is realized and meanwhile the impedance matching requirement is met by distributing different numbers of the sub units to the main and auxiliary taps. However, the static power consumption of SST of this structure is large and rises singly as the equalization coefficient increases. In addition, when the driver is to match the interface protocol, the power supply voltage needs to be changed again, and power consumption is increased.

Fig. 1 shows a classical differential SST-Driver structure, which has a simple design concept and can realize impedance matching and feedforward equalization at the same time, but the disadvantage of this structure is that the static power consumption is large, and the power consumption increases after FFE is turned on, as shown in the following formula:

G _kill +G _sig ＝G _T (1)

wherein N is the number of slices, and M and N-M respectively represent the number of slices accessed to the main tap and the auxiliary tap. It is apparent that the output current only consumes minimal power when the differential output voltage is equal to the supply voltage, but no FFE effect is present at this time. The strongest difference in equalization coefficient is output 0 and the power consumption is doubled.

To improve this structure, in the prior art, when the impedance matching and FFE functions are implemented, a resistor may be connected in parallel across the output voltage, so as to implement the output current minimization. Such a modified SST-Driver is shown in fig. 2. Similarly, the expressions for its output voltage and output current can be written as follows:

G _sig +G _shunt ＝G _T (4)

comparing (3) with (6), it can be seen that the current amplitude is greatly reduced, but the SST-Driver structure requires encoding the data type. A conventional encoding circuit is shown in fig. 3. The sign of equation (5) depends on the current flow direction. For example, in fig. 2, the current flows from left to right in the same direction as the output voltage, and is thus positive, and vice versa.

Although the power consumption optimized SST-Driver is realized by the circuits of fig. 2 and 3, it still has two problems.

First: because the driving capability of the three logic gates is inconsistent, the pull-up and pull-down tubes of the Driver and the parallel switch tubes have different opening speeds, so that intersymbol interference (ISI) is generated, thereby increasing jitter and error rate and reducing performance.

Second,: in order to be compatible with different protocol requirements, the Driver needs to have controllable output signal swing, however, in the traditional method, a linear voltage regulator (LDO) is added in a chip, so that power consumption and area are wasted further for a while, and the output of the LDO is generally fixed, so that the design difficulty of the LDO is increased if the resolution and the range of the output voltage are both increased.

In summary, the conventional SST driver has the problems of high static power consumption and difficult signal swing adjustment.

Disclosure of Invention

The invention aims to provide a low-power consumption SST driver with controllable precoding type swing, which reduces static power consumption and is easy to adjust signal swing.

In order to achieve the above purpose, the invention adopts the following technical scheme:

a low power SST driver with a controllable pre-coding mode swing, comprising:

the SST driving circuit comprises an output resistor and shunt resistors connected in parallel with two ends of the output resistor, and the number of slices of a main tap in the SST driving circuit is adjustable;

the coding circuit is used for coding the data type and driving the SST driving circuit, and comprises a latch group for outputting four paths of signals, a logic gate group and a selector group, wherein the logic gate group is arranged at the front stage of the selector group.

The SST driving circuit further comprises a first resistor, a second resistor, a third resistor and a fourth resistor, wherein the first resistor, the output resistor and the second resistor are sequentially connected in series and coupled between a power end and the ground to form a first branch, the third resistor, the output resistor and the fourth resistor are sequentially connected in series and coupled between the power end and the ground to form a second branch, and the first branch and the second branch are arranged in a crisscross manner.

The first resistor is provided by a first pull-up transistor, the second resistor is provided by a first pull-down transistor, the third resistor is provided by a second pull-up transistor, the fourth resistor is provided by a second pull-down transistor, and the shunt resistor is provided by a parallel transistor.

The gate circuit group comprises two paths of NAND gates, two paths of NAND gates and two paths of exclusive-OR gates, wherein the first path of NAND gates, the first path of NAND gates and the first path of exclusive-OR gates are all connected with a first path of signals and a third path of signals output by the latch group, and the first path of NAND gates, the first path of NAND gates and the first path of exclusive-OR gates are all connected with a second path of signals and a fourth path of signals output by the latch group.

The selector group comprises three paths of selectors, wherein the first path of selectors is connected with signals output by the two paths of NOR gates, the second path of selectors is connected with signals output by the two paths of NAND gates, the third path of selectors is connected with signals output by the two paths of NOR gates, the first path of selectors outputs signals corresponding to the first pull-up transistor or the second pull-up transistor, the second path of selectors outputs signals corresponding to the first pull-down transistor or the second pull-down transistor, and the third path of selectors outputs signals corresponding to the parallel transistors.

The latch set comprises five latches, wherein the input end of a first latch and the input end of a second latch form the input end of the latch set, the input end of a third latch is connected with the output end of the first latch, the input end of a fourth latch is connected with the output end of a second latch, the input end of the fifth latch is connected with the output end of a third latch, the output end of the third latch forms the first output end of the latch set and outputs a first path signal, the output end of the fifth latch forms the second output end of the latch set and outputs a second path signal, the output end of the fourth latch forms the third output end of the latch set and outputs a third path signal, and the output end of the second latch forms the fourth output end of the latch set and outputs a fourth path signal.

Due to the application of the technical scheme, compared with the prior art, the invention has the following advantages: the invention can further reduce the power consumption, improve the ISI, is easy to adjust the swing amplitude, and is suitable for being applied to high-speed serial link communication.

Drawings

FIG. 1 is a schematic diagram of a classical differential SST-Driver.

FIG. 2 is a schematic diagram of an improved SST-Driver.

Fig. 3 is a schematic diagram of a conventional encoding circuit.

Fig. 4 is a schematic diagram of an SST driving circuit in a low power SST driver with a controllable pre-coding swing according to the present invention.

Fig. 5 is a schematic diagram of the encoding circuit in the low power SST driver with a controllable pre-encoding swing of the present invention.

Fig. 6 is a schematic diagram of the differential signal swing of the present invention.

Fig. 7 is a diagram of the near-end eye diagram and the far-end eye diagram of the output signal of the present invention.

Detailed Description

The invention will be further described with reference to examples of embodiments shown in the drawings.

Embodiment one: based on the existing SST driver, the problem that the output swing amplitude of the SST driver is adjustable is solved. See fig. 2 and equation (5). The output swing can be adjusted by limiting the maximum number of main tap counts. The schematic diagram of the modified SST driving circuit is thus seen in fig. 4. The method comprises the following steps:

G _sig +G _shunt ＝G _T (7)

comparing (5) and (8) can find that the output voltage swing can be controlled by redistributing the limit values of the parallel tube and the pull-up pull-down tube, thereby avoiding the complexity of modulating the power supply. Of course, the precondition is still to satisfy the condition of impedance matching.

Secondly, to cancel ISI, we can put the coding circuit in the front stage, as shown in fig. 5. The 2-string 1 serializer is utilized to realize a re-timing function by self-carrying clocks, so that jitter generated by the problem of non-uniform driving capability of logic gates is eliminated. Although logic gates and selector blocks are added in this case, the reduction in speed also causes little increase in power consumption as they are pushed to the previous stage.

In summary, and referring to fig. 4 and fig. 5, the specific scheme of the present application is as follows:

a low-power consumption SST driver with controllable pre-coding swing comprises an SST driving circuit and a coding circuit.

The SST driving circuit comprises an output resistor and shunt resistors connected in parallel at two ends of the output resistor, and the slicing number m-n of the main tap in the SST driving circuit determines the equalization strength and the output swing. Specifically, the SST driving circuit further includes a first resistor, a second resistor, a third resistor, and a fourth resistor, where the first resistor, the output resistor, and the second resistor are sequentially connected in series and coupled to the power supply terminal V _drv A first branch is formed between the first resistor and the ground, a third resistor, an output resistor and a fourth resistor are connected in series in turn and are coupled to a power supply end V _drv And a second branch is formed between the first branch and the ground, and the first branch and the second branch are arranged in a crisscross manner. Wherein the first resistor is provided by a first pull-up transistor, the second resistor is provided by a first pull-down transistor, the third resistor is provided by a second pull-up transistor, the fourth resistor is provided by a second pull-down transistor, and the shunt resistor is provided by a parallel transistor. The first branch and the second branch are respectively started, and the state of the first branch when the first branch is started is shown in fig. 4.

The coding circuit is used for coding the data type and driving the SST driving circuit and comprises a latch group, a logic gate group and a selector group, wherein the latch group outputs four-way signals, and the logic gate group is arranged at the front stage of the selector group. The latch set comprises five latches, wherein the input end of a first latch and the input end of a second latch form the input end of the latch set, the input end of a third latch is connected with the output end of the first latch, the input end of a fourth latch is connected with the output end of the second latch, the input end of a fifth latch is connected with the output end of the third latch, the output end of the third latch forms the first output end of the latch set and outputs a first path signal, the output end of the fifth latch forms the second output end of the latch set and outputs a second path signal, the output end of the fourth latch forms the third output end of the latch set and outputs a third path signal, and the output end of the second latch forms the fourth output end of the latch set and outputs a fourth path signal. The gate circuit group comprises two paths of NAND gates, two paths of NAND gates and two paths of exclusive-or gates, wherein the first path of NAND gates, the first path of NAND gates and the first path of exclusive-or gates are all connected with a first path of signals and a third path of signals output by the latch group, and the first path of NAND gates, the first path of NAND gates and the first path of exclusive-or gates are all connected with a second path of signals and a fourth path of signals output by the latch group. The selector group comprises three paths of selectors, wherein the first path of selector is connected with signals output by two paths of NAND gates, the second path of selector is connected with signals output by two paths of NAND gates, the third path of selector is connected with signals output by two paths of NAND gates, the first path of selector outputs signals corresponding to a first pull-up transistor or a second pull-up transistor, the second path of selector outputs signals corresponding to the first pull-down transistor or the second pull-down transistor, and the third path of selector outputs signals corresponding to parallel transistors.

To combat channel attenuation at different frequencies, we can adjust the number of SST-drivers to achieve the degree of FFE equalization, as shown in fig. 6. In this design, the equalization step size is 20mV and the maximum swing of the differential signal is 800mV.

Fig. 7 shows a near-end eye diagram and a far-end eye diagram of an output signal. The transmission rate of the signal is 28Gb/s, so the equalization degree is high, and the (a) in FIG. 7 shows the near-end eye diagram after FFE equalization, and it can be seen that FFE realizes pre-distortion according to the channel characteristics. Fig. 7 (b) is a far-end eye diagram. The pre-distortion nature of FFE in SST-Driver is de-emphasis, attenuating the low frequency content of the signal, so that the high frequency content is attenuated after passing through the channel, the proportion of the total frequency content of the signal is substantially unchanged, only the energy is attenuated. The SST-Driver is therefore well suited for high-speed serial link communication applications.

The above embodiments are provided to illustrate the technical concept and features of the present invention and are intended to enable those skilled in the art to understand the content of the present invention and implement the same, and are not intended to limit the scope of the present invention. All equivalent changes or modifications made in accordance with the spirit of the present invention should be construed to be included in the scope of the present invention.

Claims

1. A low power SST driver with a controllable pre-coding swing, characterized in that: the low-power consumption SST driver with controllable precoding swing comprises:

the coding circuit is used for coding the data type and driving the SST driving circuit, and comprises a latch group for outputting four paths of signals, a logic gate group and a selector group, wherein the logic gate group is arranged at the front stage of the selector group;

the SST driving circuit further comprises a first resistor, a second resistor, a third resistor and a fourth resistor, wherein the first resistor, the output resistor and the second resistor are sequentially connected in series and coupled between a power end and the ground to form a first branch, the third resistor, the output resistor and the fourth resistor are sequentially connected in series and coupled between the power end and the ground to form a second branch, and the first branch and the second branch are arranged in a crisscross manner; the first resistor is provided by a first pull-up transistor, the second resistor is provided by a first pull-down transistor, the third resistor is provided by a second pull-up transistor, the fourth resistor is provided by a second pull-down transistor, and the shunt resistor is provided by a parallel transistor;

the logic gate group comprises two paths of NAND gates, two paths of NAND gates and two paths of exclusive-OR gates, wherein the first path of NAND gates, the first path of NAND gates and the first path of exclusive-OR gates are all connected with a first path of signals and a third path of signals output by the latch group, and the first path of NAND gates, the first path of NAND gates and the first path of exclusive-OR gates are all connected with a second path of signals and a fourth path of signals output by the latch group;

the selector group comprises three paths of selectors, wherein the first path of selectors is connected with signals output by the two paths of NOR gates, the second path of selectors is connected with signals output by the two paths of NAND gates, the third path of selectors is connected with signals output by the two paths of NOR gates, the first path of selectors outputs signals corresponding to the first pull-up transistor or the second pull-up transistor, the second path of selectors outputs signals corresponding to the first pull-down transistor or the second pull-down transistor, and the third path of selectors outputs signals corresponding to the parallel transistors;