CN111446700A - Battery protector - Google Patents
Battery protector Download PDFInfo
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- CN111446700A CN111446700A CN201910044276.2A CN201910044276A CN111446700A CN 111446700 A CN111446700 A CN 111446700A CN 201910044276 A CN201910044276 A CN 201910044276A CN 111446700 A CN111446700 A CN 111446700A
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- Prior art keywords
- bonding pad
- chip
- external port
- terminal bonding
- pad
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/18—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for batteries; for accumulators
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Abstract
The present invention provides a battery protector, comprising: the lead frame is provided with a chip substrate, an IC chip external port and an MOS chip external port; the MOS chip is fixed on the upper surface of the chip substrate and is provided with a first external bonding pad and an IC chip connecting bonding pad; the battery protection IC chip is fixed on the upper surface of the MOS chip and is provided with a second external bonding pad and an MOS chip connecting bonding pad; the external port of the IC chip is connected with the second external bonding pad, the external port of the MOS chip is connected with the first external bonding pad, and the IC chip connecting bonding pad is connected with the MOS chip connecting bonding pad. The battery protector integrates overcurrent, short circuit, overvoltage, undervoltage and overtemperature protection, has small volume, small internal resistance, high current conduction, high precision, low power consumption, low temperature rise, high reaction speed, stability and reliability, is vibration-proof, impact-resistant, moisture-proof, pressure-resistant, aging-resistant, high-low temperature-resistant, not easy to be influenced by the environment, long in quality guarantee period, long in service life of device action times and production cost saving.
Description
Technical Field
The invention belongs to the field of semiconductor integrated packaging, and particularly relates to a battery protector.
Background
In the current big data era, smart phones, smart home appliances and intelligent wearing are the development directions in the present and future, and the existing battery protection devices are greatly limited in the application field.
At present, no battery protection device integrating overcurrent, short circuit, overvoltage, undervoltage and overtemperature protection is available. Known protective devices applied to battery protection mainly include Breaker, FUES and PTC. Breaker: the volume of the device is large, the device is afraid of strong vibration in use and cannot be extruded by external force, the passing current is more than dozens of times of that of high temperature when the environment is at low temperature, the device only can play a role of protection in high temperature environment, and the current and temperature difference acting in high and low temperature change environment are particularly large. FUES: the fuse wire needs more than 1A of current to heat the internal fuse wire in an overvoltage state, the heating time can be only ten seconds to dozens of seconds at the fastest speed at normal temperature to fuse the fuse wire, a large amount of heat can be generated in a small electronic product, the service life of the product is influenced, the fuse wire can be only fused after being heated for a few minutes in a low-temperature environment, and the fuse wire is disposable, so that the whole electronic product cannot be used again after being fused, cannot be recovered, and has a large volume. PTC: the thermistor material is greatly influenced by the environmental temperature, the protection action speed is low, the internal resistance is gradually increased after multiple actions, the thermistor material is heated until power failure in a keeping state after the actions, the leakage current is high, the action power is kept to be about 1.2W generally, certain influence is caused on the service life of an electronic product, in addition, when the environmental temperature is higher, the PTC holding current is reduced, the protection effect can not be normally realized if the PTC holding current is extruded by external force, and the stability is reduced.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a battery protector, which integrates overcurrent, short circuit, overvoltage, undervoltage and overtemperature protection, and has the advantages of small volume, small internal resistance, large current passing, high precision, low power consumption, low temperature rise, fast reaction speed, stability, reliability, vibration resistance, impact resistance, moisture resistance, pressure resistance, aging resistance, high and low temperature resistance, environmental protection, long shelf life, long device operation frequency life, and production cost saving.
To achieve the above and other related objects, the present invention provides a battery protector, comprising:
the lead frame is provided with a chip substrate, an IC chip external port and an MOS chip external port;
the MOS chip is fixed on the upper surface of the chip substrate and is provided with a first external bonding pad and an IC chip connecting bonding pad;
the battery protection IC chip is fixed on the upper surface of the MOS chip and is provided with a second external bonding pad and an MOS chip connecting bonding pad;
the IC chip external port is connected with the second external bonding pad, the MOS chip external port is connected with the first external bonding pad, and the IC chip connecting bonding pad is connected with the MOS chip connecting bonding pad.
Optionally, the MOS chip includes a dual MOS chip.
Optionally, the kind of the dual MOS chip includes a dual NMOS chip.
Optionally, the lead frame further has a no-load port, the IC chip external port includes a power supply positive external port, and the MOS chip external port includes a first negative external port and a second negative external port.
Optionally, the first negative external port and the second negative external port include at least one port connected to the outside.
Optionally, the first negative external port and the power supply positive external port are located on the left side of the chip substrate, and the second negative external port and the idle port are located on the right side of the chip substrate.
Optionally, the MOS chip further has a drain terminal pad, the first external connection pad includes a first source terminal pad and a second source terminal pad, and the IC chip connection pad includes: a third source terminal pad, a fourth source terminal pad, a first gate terminal pad, and a second gate terminal pad.
Optionally, the first source terminal pad is located in a left region of the MOS chip, and the second source terminal pad is located in a right region of the MOS chip.
Optionally, the second external pad includes a power supply positive terminal pad, and the MOS chip connection pad includes: a third gate terminal bonding pad, a fourth gate terminal bonding pad, a first negative terminal bonding pad and a second negative terminal bonding pad.
Optionally, the power supply positive terminal pad is located in a left region of the battery protection IC chip.
Optionally, the power source positive terminal pad is connected to the power source positive external port, the first negative terminal pad is connected to the third source terminal pad, the third gate terminal pad is connected to the first gate terminal pad, the fourth gate terminal pad is connected to the second gate terminal pad, and the second negative terminal pad is connected to the fourth source terminal pad.
Optionally, the power source positive terminal pad is connected to the power source positive external port through a metal wire, the first negative terminal pad is connected to the third source terminal pad through a metal wire, the third gate terminal pad is connected to the first gate terminal pad through a metal wire, the fourth gate terminal pad is connected to the second gate terminal pad through a metal wire, and the second negative terminal pad is connected to the fourth source terminal pad through a metal wire.
Optionally, the first source terminal pad is connected to the first cathode external port, and the second source terminal pad is connected to the second cathode external port.
Optionally, the first source terminal pad and the first cathode external port are connected through a first metal strip, and the second source terminal pad and the second cathode external port are connected through a second metal strip.
Optionally, the species of the first metal strip and the second metal strip comprises a copper strip.
Optionally, the first metal strap and the second metal strap include a vertical portion and a horizontal portion, the vertical portion is connected to and integrally formed with the horizontal portion, the horizontal portion of the first metal strap is fixed to the first source terminal pad, the vertical portion of the first metal strap is fixed to the first negative external port, the horizontal portion of the second metal strap is fixed to the second source terminal pad, and the vertical portion of the second metal strap is fixed to the second negative external port.
Optionally, the horizontal portion of the first metal strip is fixed to the first source terminal pad by solder, the vertical portion of the first metal strip is fixed to the first external negative electrode port by solder, the horizontal portion of the second metal strip is fixed to the second source terminal pad by solder, and the vertical portion of the second metal strip is fixed to the second external negative electrode port by solder.
Optionally, the MOS chip is fixed to the upper surface of the chip substrate by solder.
Optionally, the battery protection IC chip is fixed to the upper surface of the MOS chip by an insulating and heat-insulating adhesive.
Optionally, the battery protector further comprises a quad flat non-leaded package structure.
As described above, the present invention provides a battery protector having the following effects:
the battery protector integrates overcurrent, short circuit, overvoltage, undervoltage and overtemperature protection, has small volume, small internal resistance, high current conduction, high precision, low power consumption, low temperature rise, high reaction speed, stability and reliability, is vibration-proof, impact-resistant, moisture-proof, pressure-resistant, aging-resistant, high-low temperature-resistant, not easy to be influenced by the environment, long in quality guarantee period, long in service life of device action times and production cost saving.
Furthermore, the first source terminal bonding pad is connected with the first cathode external port through a first metal strip, and the second source terminal bonding pad is connected with the second cathode external port through a second metal strip, so that the large flow is ensured to pass through.
The battery protection IC chip is fixed in the upper surface of MOS chip makes the device volume reduce 50%, and the metal wire shortens and has reduced the line loss, and the volume reduces and has reduced the encapsulation cost, has improved stability and interference killing feature simultaneously.
Drawings
Fig. 1 is a schematic top view of the battery protector according to the present invention.
Fig. 2 is a schematic front view of the battery protector according to the present invention.
Description of the element reference numerals
101 MOS chip
102 drain terminal pad
103 first source terminal pad
104 second source terminal pad
105 third source terminal pad
106 fourth source terminal pad
107 first gate terminal pad
108 second gate terminal pad
109 chip substrate
110 power supply anode external port
111 unloaded port
112 first cathode external port
113 second negative external port
114 first metal strip
115 second metal strip
116 insulating and heat-insulating glue
117-121 solder
122 battery protection IC chip
123 first negative terminal pad
124 third gate terminal pad
125 fourth gate terminal pad
126 second negative terminal pad
127 Power supply positive terminal pad
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1-2. It should be understood that the structures, ratios, sizes, and the like shown in the drawings and described in the specification are only used for matching with the disclosure of the specification, so as to be understood and read by those skilled in the art, and are not used to limit the conditions under which the present invention can be implemented, so that the present invention has no technical significance, and any structural modification, ratio relationship change, or size adjustment should still fall within the scope of the present invention without affecting the efficacy and the achievable purpose of the present invention. In addition, the terms "upper", "lower", "left", "right", "middle" and "one" used in the present specification are for clarity of description, and are not intended to limit the scope of the present invention, and the relative relationship between the terms and the terms is not to be construed as a scope of the present invention.
As shown in fig. 1 to 2, the present embodiment provides a battery protector including: a lead frame, a MOS chip 101, a battery protection IC chip 122, a wire, a metal tape.
The lead frame has a chip substrate 109, an IC chip external port, and a MOS chip external port.
And port substrates are arranged on the lower surfaces of the external port of the IC chip and the external port of the MOS chip.
The kind of the chip substrate 109 and the port substrate includes a copper substrate.
The lead frame is further provided with a no-load port 111, the external ports of the IC chip comprise a positive external port 110 of a power supply, and the external ports of the MOS chip comprise a first negative external port 112 and a second negative external port 113.
The external port 110 of the power supply anode is connected with the power supply anode, the external port 112 of the first cathode is connected with the negative electrode of the charger and a load to play a role in charging and supplying power, and the external port 113 of the second cathode is connected with the negative electrode of the battery.
The first negative external port 112 and the second negative external port 113 include at least 1 port connected to the outside.
In this embodiment, the first negative external port 112 and the second negative external port 113 have 3 ports connected to the outside.
The first negative external port 112 and the power positive external port 110 are located on the left side of the chip substrate 109, and the second negative external port 113 and the idle port 111 are located on the right side of the chip substrate 109.
The MOS chip 101 is fixed to the upper surface of the chip substrate 109, and the MOS chip 101 has a first external bonding pad and an IC chip bonding pad.
The MOS chip 101 is fixed to the upper surface of the chip substrate 109 by solder.
As an example, the MOS chip 101 includes a dual MOS chip. The kind of the double MOS chip comprises a double NMOS chip.
In this embodiment, the MOS chip 101 is a dual NMOS chip.
The MOS chip 101 further has a drain terminal pad 102, the first external connection pad includes a first source terminal pad 103 and a second source terminal pad 104, and the IC chip connection pad includes: a third source terminal pad 105, a fourth source terminal pad 106, a first gate terminal pad 107, a second gate terminal pad 108.
The first source terminal pad 103, the second source terminal pad 104, the third source terminal pad 105, and the fourth source terminal pad 106 are connected to the source of the MOS chip 101, the first gate terminal pad 107 and the second gate terminal pad 108 are connected to the gate of the MOS chip 101, and the drain terminal pad 102 is connected to the drain of the MOS chip 101.
The first source terminal pad 103 is located in a left region of the MOS chip 101, and the second source terminal pad 104 is located in a right region of the MOS chip 101.
The battery protection IC chip 122 is fixed to the upper surface of the MOS chip 101, and the battery protection IC chip 122 has a second external pad and a MOS chip 101 connection pad.
The battery protection IC chip 122 is fixed to the upper surface of the MOS chip 101 by an insulating adhesive 116.
The second external pad includes a power source positive terminal pad 127, and the MOS chip 101 connection pad includes: a third gate terminal pad 124, a fourth gate terminal pad 125, a first negative terminal pad 123, and a second negative terminal pad 126. The power supply positive terminal pad 127 is located in a left region of the battery protection IC chip 122.
The battery protection IC chip 122 is fixed on the upper surface of the MOS chip 101, so that the volume of the device is reduced by 50%, the wire loss is reduced by shortening the metal wire, the packaging cost is reduced by reducing the volume, and the stability and the anti-interference capability are improved.
The IC chip external port is connected with the second external bonding pad, the MOS chip external port is connected with the first external bonding pad, and the IC chip connecting bonding pad is connected with the MOS chip 101 connecting bonding pad.
The power source positive terminal pad 127 is connected to the power source positive external port 110, the first negative terminal pad 123 is connected to the third source terminal pad 105, the third gate terminal pad 124 is connected to the first gate terminal pad 107, the fourth gate terminal pad 125 is connected to the second gate terminal pad 108, and the second negative terminal pad 126 is connected to the fourth source terminal pad 106.
The power source positive terminal pad 127 is connected with the power source positive external port 110 through a metal wire, the first negative terminal pad 123 is connected with the third source terminal pad 105 through a metal wire, the third gate terminal pad 124 is connected with the first gate terminal pad 107 through a metal wire, the fourth gate terminal pad 125 is connected with the second gate terminal pad 108 through a metal wire, and the second negative terminal pad 126 is connected with the fourth source terminal pad 106 through a metal wire.
The first source terminal pad 103 is connected to the first cathode external port 112, and the second source terminal pad 104 is connected to the second cathode external port 113. The first source terminal pad 103 and the first cathode external port 112 are connected by a first metal strap 114, and the second source terminal pad 104 and the second cathode external port 113 are connected by a second metal strap 115. The species of the first metal strip 114 and the second metal strip 115 comprise copper strips.
The first source terminal pad 103 is connected to the first cathode external port 112 through a first metal strap 114, the second source terminal pad 104 is connected to the second cathode external port 113 through a second metal strap 115, and the first metal strap 114 and the second metal strap 115 have larger cross-sectional areas, so that the resistance value is effectively reduced, and the large flow can be realized.
The first metal strap 114 and the second metal strap 115 include a vertical portion and a horizontal portion, the vertical portion is connected with the horizontal portion and integrally formed, the horizontal portion of the first metal strap 114 is fixed to the first source terminal pad 103, the vertical portion of the first metal strap 114 is fixed to the first negative external port 112, the horizontal portion of the second metal strap 115 is fixed to the second source terminal pad 104, and the vertical portion of the second metal strap 115 is fixed to the second negative external port 113.
The horizontal portion of the first metal strap 114 is fixed to the first source terminal pad 103 by solder 119, the vertical portion of the first metal strap 114 is fixed to the first cathode external port 112 by solder 117, the horizontal portion of the second metal strap 115 is fixed to the second source terminal pad 104 by solder 120, and the vertical portion of the second metal strap 115 is fixed to the second cathode external port 113 by solder 118.
The battery protector also includes a quad flat non-leaded package structure.
In summary, the present invention provides a battery protector, which has the following functions: the battery protector integrates overcurrent, short circuit, overvoltage, undervoltage and overtemperature protection, has small volume, small internal resistance, high current conduction, high precision, low power consumption, low temperature rise, high reaction speed, stability and reliability, is vibration-proof, impact-resistant, moisture-proof, pressure-resistant, aging-resistant, high-low temperature-resistant, not easy to be influenced by the environment, long in quality guarantee period, long in service life of device action times and production cost saving. Further, the first source terminal pad 103 and the first cathode external port 112 are connected through a first metal strap 114, and the second source terminal pad 104 and the second cathode external port 113 are connected through a second metal strap 115, so as to ensure a large flow rate. The battery protection IC chip 122 is fixed on the upper surface of the MOS chip 101, so that the volume of the device is reduced by 50%, the wire loss is reduced by shortening the metal wire, the packaging cost is reduced by reducing the volume, and the stability and the anti-interference capability are improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (20)
1. A battery protector, comprising:
the lead frame is provided with a chip substrate, an IC chip external port and an MOS chip external port;
the MOS chip is fixed on the upper surface of the chip substrate and is provided with a first external bonding pad and an IC chip connecting bonding pad;
the battery protection IC chip is fixed on the upper surface of the MOS chip and is provided with a second external bonding pad and an MOS chip connecting bonding pad;
the IC chip external port is connected with the second external bonding pad, the MOS chip external port is connected with the first external bonding pad, and the IC chip connecting bonding pad is connected with the MOS chip connecting bonding pad.
2. The battery protector of claim 1, wherein: the MOS chip comprises a double MOS chip.
3. The battery protector of claim 2, wherein: the kind of the double MOS chip comprises a double NMOS chip.
4. The battery protector of claim 2, wherein: the lead frame is also provided with a no-load port, the external port of the IC chip comprises a positive external port of a power supply, and the external port of the MOS chip comprises a first negative external port and a second negative external port.
5. The battery protector of claim 4, wherein: the first negative external port and the second negative external port comprise at least one port connected with the outside.
6. The battery protector of claim 4, wherein: the first negative external port and the power supply positive external port are located on the left side of the chip substrate, and the second negative external port and the idle port are located on the right side of the chip substrate.
7. The battery protector of claim 4, wherein: the MOS chip also has a drain terminal pad, the first external pad includes a first source terminal pad and a second source terminal pad, the IC chip connection pad includes: a third source terminal pad, a fourth source terminal pad, a first gate terminal pad, and a second gate terminal pad.
8. The battery protector of claim 7, wherein: the first source terminal bonding pad is located in the left side area of the MOS chip, and the second source terminal bonding pad is located in the right side area of the MOS chip.
9. The battery protector of claim 7, wherein: the second external bonding pad comprises a power supply positive terminal bonding pad, and the MOS chip connecting bonding pad comprises: a third gate terminal bonding pad, a fourth gate terminal bonding pad, a first negative terminal bonding pad and a second negative terminal bonding pad.
10. The battery protector of claim 9, wherein: the power supply positive terminal bonding pad is positioned in the left area of the battery protection IC chip.
11. The battery protector of claim 9, wherein: the power supply positive terminal bonding pad is connected with the power supply positive external port, the first negative terminal bonding pad is connected with the third source terminal bonding pad, the third grid terminal bonding pad is connected with the first grid terminal bonding pad, the fourth grid terminal bonding pad is connected with the second grid terminal bonding pad, and the second negative terminal bonding pad is connected with the fourth source terminal bonding pad.
12. The battery protector of claim 11, wherein: the power supply positive terminal bonding pad is connected with the power supply positive external port through a metal wire, the first negative terminal bonding pad is connected with the third source terminal bonding pad through a metal wire, the third grid terminal bonding pad is connected with the first grid terminal bonding pad through a metal wire, the fourth grid terminal bonding pad is connected with the second grid terminal bonding pad through a metal wire, and the second negative terminal bonding pad is connected with the fourth source terminal bonding pad through a metal wire.
13. The battery protector of claim 9, wherein: the first source terminal bonding pad is connected with the first cathode external port, and the second source terminal bonding pad is connected with the second cathode external port.
14. A battery protector as set forth in claim 13 wherein: the first source terminal bonding pad is connected with the first cathode external port through a first metal strip, and the second source terminal bonding pad is connected with the second cathode external port through a second metal strip.
15. A battery protector as set forth in claim 14 wherein: the species of the first metal strip and the second metal strip comprise copper strips.
16. A battery protector as set forth in claim 14 wherein: the first metal strip and the second metal strip comprise a vertical part and a horizontal part, the vertical part is connected with the horizontal part and is integrally formed, the horizontal part end of the first metal strip is fixed on the first source terminal bonding pad, the vertical part end of the first metal strip is fixed on the first cathode external port, the horizontal part end of the second metal strip is fixed on the second source terminal bonding pad, and the vertical part end of the second metal strip is fixed on the second cathode external port.
17. A battery protector as set forth in claim 16 wherein: the horizontal portion end of the first metal strip is fixed to the first source terminal bonding pad through soldering tin, the vertical portion end of the first metal strip is fixed to the first cathode external connection port through soldering tin, the horizontal portion end of the second metal strip is fixed to the second source terminal bonding pad through soldering tin, and the vertical portion end of the second metal strip is fixed to the second cathode external connection port through soldering tin.
18. The battery protector of claim 1, wherein: the MOS chip is fixed on the upper surface of the chip substrate through soldering tin.
19. The battery protector of claim 1, wherein: the battery protection IC chip is fixed on the upper surface of the MOS chip through insulating and heat-insulating glue.
20. The battery protector of claim 1, wherein: the battery protector also includes a quad flat non-leaded package structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910044276.2A CN111446700A (en) | 2019-01-17 | 2019-01-17 | Battery protector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910044276.2A CN111446700A (en) | 2019-01-17 | 2019-01-17 | Battery protector |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111446700A true CN111446700A (en) | 2020-07-24 |
Family
ID=71648461
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910044276.2A Pending CN111446700A (en) | 2019-01-17 | 2019-01-17 | Battery protector |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111446700A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5596474A (en) * | 1994-09-28 | 1997-01-21 | Nittetsu Semiconductor Co., Ltd. | Power protection circuitry for a semiconductor integrated circuit |
| CN101663749A (en) * | 2007-11-21 | 2010-03-03 | 万国半导体股份有限公司 | Stacked-die package for battery power management |
| US20110090605A1 (en) * | 2000-06-22 | 2011-04-21 | Renesas Technology Corp. | Semiconductor integrated circuit |
| CN103066338A (en) * | 2011-10-20 | 2013-04-24 | 三星Sdi株式会社 | Protective circuit module and battery pack having same |
| CN105390487A (en) * | 2014-08-27 | 2016-03-09 | Itm半导体有限公司 | Battery protection circuit package |
| CN107768368A (en) * | 2016-08-23 | 2018-03-06 | 万国半导体(开曼)股份有限公司 | The ESD protections of USB c-type on-load switches |
-
2019
- 2019-01-17 CN CN201910044276.2A patent/CN111446700A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5596474A (en) * | 1994-09-28 | 1997-01-21 | Nittetsu Semiconductor Co., Ltd. | Power protection circuitry for a semiconductor integrated circuit |
| US20110090605A1 (en) * | 2000-06-22 | 2011-04-21 | Renesas Technology Corp. | Semiconductor integrated circuit |
| CN101663749A (en) * | 2007-11-21 | 2010-03-03 | 万国半导体股份有限公司 | Stacked-die package for battery power management |
| CN103066338A (en) * | 2011-10-20 | 2013-04-24 | 三星Sdi株式会社 | Protective circuit module and battery pack having same |
| CN105390487A (en) * | 2014-08-27 | 2016-03-09 | Itm半导体有限公司 | Battery protection circuit package |
| CN107768368A (en) * | 2016-08-23 | 2018-03-06 | 万国半导体(开曼)股份有限公司 | The ESD protections of USB c-type on-load switches |
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Application publication date: 20200724 |