CN111446335B - A kind of light-emitting diode and preparation method thereof - Google Patents
A kind of light-emitting diode and preparation method thereof Download PDFInfo
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- CN111446335B CN111446335B CN202010211462.3A CN202010211462A CN111446335B CN 111446335 B CN111446335 B CN 111446335B CN 202010211462 A CN202010211462 A CN 202010211462A CN 111446335 B CN111446335 B CN 111446335B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/81—Bodies
- H10H20/811—Bodies having quantum effect structures or superlattices, e.g. tunnel junctions
- H10H20/812—Bodies having quantum effect structures or superlattices, e.g. tunnel junctions within the light-emitting regions, e.g. having quantum confinement structures
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/01—Manufacture or treatment
- H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
- H10H20/013—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
- H10H20/0133—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials
- H10H20/01335—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials the light-emitting regions comprising nitride materials
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/81—Bodies
- H10H20/822—Materials of the light-emitting regions
- H10H20/824—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP
- H10H20/825—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP containing nitrogen, e.g. GaN
- H10H20/8252—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP containing nitrogen, e.g. GaN characterised by the dopants
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Abstract
本发明涉及显示技术领域，公开了一种发光二极管及其制备方法，制备方法包括：在衬底上形成阵列分布的发光二极管单元，沿背离衬底的方向，每个发光二极管单元包括缓冲层、n‑GaN层、MQW层以及p‑GaN层；在发光二极管单元上形成第一金属层，且通过构图工艺将第一金属层图案化，形成第一金属图案；以第一金属图案为掩膜，在p‑GaN层部分区域内形成侧壁限制结构。本发明提供的发光二极管制备方法制备的发光二极管在p‑GaN层内局部位置形成侧壁限制结构，侧壁限制结构可以抑制侧壁效应。上述发光二极管制备方法不仅可以在大尺寸发光二极管实现小电流注入、避免侧壁效应，而且该制备方法可与现有半导体工艺兼容。
The invention relates to the technical field of display, and discloses a light-emitting diode and a preparation method thereof. The preparation method comprises: forming light-emitting diode units distributed in an array on a substrate, and along a direction away from the substrate, each light-emitting diode unit includes a buffer layer, n-GaN layer, MQW layer and p-GaN layer; forming a first metal layer on the light emitting diode unit, and patterning the first metal layer through a patterning process to form a first metal pattern; using the first metal pattern as a mask , forming a sidewall confinement structure in a partial region of the p-GaN layer. The light emitting diode prepared by the light emitting diode manufacturing method provided by the present invention forms a sidewall confinement structure at a local position in the p-GaN layer, and the sidewall confinement structure can suppress the sidewall effect. The above light-emitting diode manufacturing method can not only realize small current injection and avoid sidewall effect in large-sized light-emitting diodes, but also the manufacturing method is compatible with the existing semiconductor process.
Description
Technical Field
The invention relates to the technical field of display, in particular to a light-emitting diode and a preparation method thereof.
Background
In recent years, Micro Light-Emitting diodes (Micro LEDs) have attracted attention as a new self-Light-Emitting display technology. Compared with a Liquid Crystal Display (LCD for short), the structure of the Micro LED is simpler, and as a self-luminous technology, the Micro LED is superior to the LCD in Display contrast, response speed, color gamut, visual angle and the like; compared with an Organic Light-Emitting Diode (OLED), the Micro LED has certain advantages in brightness, efficiency, and lifetime.
In the current Micro LED display technology, the size of an LED is relatively large (generally more than 30 um), and the current density of the LED is 1-10A/cm2And therefore the total injected current in the LED is large. To further reduce the injection current to reduce the brightness and reduce the power consumption, thereby meeting the brightness and power consumption requirements of most display products, the mainstream solution is to reduce the size of the LED.
However, this solution has the following problems: the size reduction of the LED causes a significant size effect, i.e. the current density of the LED is increased and the peak External Quantum Efficiency (EQE) is reduced. Micro LEDs typically require transfer from an original substrate to a target substrate. Taking pick and place transfer method as an example, the reduction in LED size reduces the accuracy and yield of the transfer method, further increasing the difficulty of mass transfer.
Disclosure of Invention
The invention discloses a light-emitting diode and a preparation method thereof, wherein the preparation method of the light-emitting diode not only can realize small current injection in a large-size light-emitting diode and avoid the side wall effect, but also can be compatible with the existing semiconductor process.
In order to achieve the purpose, the invention provides the following technical scheme:
a method for preparing a light-emitting diode comprises the following steps:
forming light emitting diode units distributed in an array on a substrate, wherein each light emitting diode unit comprises a buffer layer, an n-GaN layer, an MQW layer and a p-GaN layer along the direction deviating from the substrate;
forming a first metal layer on the light emitting diode unit, and patterning the first metal layer through a composition process to form a first metal pattern;
and forming a side wall limiting structure in the partial region of the p-GaN layer by taking the first metal pattern as a mask.
In the preparation method of the light-emitting diode, the light-emitting diode units distributed in an array mode are formed on the substrate, the first metal layer is formed on one side, away from the substrate, of the light-emitting diode units, the first metal pattern is formed through the composition process, the first metal pattern is used as a mask, and the side wall limiting structure is formed in the p-GaN layer.
The LED prepared by the LED preparation method provided by the invention forms a side wall limiting structure at a local position in the p-GaN layer, and the side wall limiting structure can inhibit the side wall effect.
Therefore, the preparation method of the light-emitting diode not only can realize small current injection in a large-size light-emitting diode and avoid the side wall effect, but also can be compatible with the existing semiconductor process.
Preferably, the method of forming the sidewall limiting structure comprises:
implanting deep-level impurity ions into the p-GaN layer by using the first metal pattern as a mask through an ion implantation process to form an implanted region, and reducing the conductivity of the implanted region through a 700-800 ℃ annealing process; the deep level impurity ions are impurity level impurity ions which are about 1-1.7eV away from the conduction band bottom or the valence band top of the GaN.
Preferably, after reducing the conductivity of the implanted region, the method further comprises:
removing the first metal pattern, and etching to the n-GaN layer along the direction of the p-GaN layer pointing to the substrate by a composition process outside the coverage of the injection region;
forming a first insulating layer on the n-GaN layer, and forming a first via hole on the first insulating layer through a patterning process;
forming a first electrode layer on the first insulating layer, and forming a first electrode pattern on the first electrode layer through a patterning process, wherein the first electrode pattern is connected with the n-GaN layer through the first via hole;
forming a second insulating layer on the first electrode pattern, and forming a second via hole and a third via hole on the second insulating layer through a patterning process, wherein a vertical projection of the third via hole on the substrate covers a vertical projection of the first via hole on the substrate;
and forming a second electrode layer on the second insulating layer, wherein the second electrode layer is partially filled in the third via hole, and the second insulating layer is formed into a second electrode pattern through a composition process, and the second electrode pattern is connected with the p-GaN layer through the second via hole.
Preferably, when the second electrode layer is patterned to form the second electrode pattern, an annealing process needs to be performed in a nitrogen atmosphere, where the annealing condition is that the temperature is 500 ℃ and the duration is 30 min.
Preferably, the method of forming the sidewall limiting structure comprises:
and implanting Si ions into the partial region of the p-GaN layer by using the first metal pattern as a mask through an ion implantation process to form an n-type conductive region.
Preferably, after the n-type conductive region is formed, the method further includes:
removing the first metal pattern, and forming an ohmic contact electrode ITO layer on the p-GaN layer;
bonding a silicon wafer on the ITO layer by a bonding process;
peeling off the substrate;
removing the buffer layer;
forming a second metal layer on the n-GaN layer, and patterning the second metal layer through a composition process to form a second metal pattern;
injecting Mg ions into the partial region of the n-GaN layer by using the second metal pattern as a mask through an ion injection process to form a p-type conductive region;
removing the second metal pattern, forming an insulating layer on the n-GaN layer, and forming a first via hole on the insulating layer through a composition process;
and forming a first electrode layer on the insulating layer, forming a first electrode pattern on the first electrode layer through a composition process, and connecting the first electrode pattern with the n-GaN layer through the first via hole.
Preferably, the preparation process for forming the first metal layer is one of a magnetron sputtering process, a thermal evaporation process, an electron beam evaporation process and an electroplating process.
Preferably, the patterning process for forming the first metal pattern is a photolithography process, an etching process and a photoresist removing process, wherein the etching process includes one of a wet etching process, a reactive ion etching process or an ion beam etching process.
Preferably, the patterning process for forming the light emitting diode units distributed in an array on the substrate includes a photolithography process, a reactive ion etching process, and a photoresist removing process.
The invention also provides a light-emitting diode which is prepared by adopting any one of the preparation methods of the light-emitting diode provided by the technical scheme.
Drawings
Fig. 1 is a schematic flow chart of a method for manufacturing a light emitting diode according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a film layer according to a first embodiment of the present invention;
FIG. 3 is a schematic view of a film layer according to a first embodiment of the present invention;
FIG. 4 is a schematic view of a first embodiment of the present invention;
FIG. 5 is a diagram illustrating a second embodiment of the present invention;
fig. 6 is a schematic diagram of a film layer in a second embodiment of the invention.
Icon: 10-a substrate; 20-a buffer layer; a 30-n-GaN layer; a 301-p type conductivity region; a 40-MQW layer; a 50-p-GaN layer; 501-an injection region; a 502-n type conductive region; 60-a first metal pattern; 70-an insulating layer; 80-a first electrode pattern; 90-a second electrode pattern; 100-an ITO layer; 110-BCB glue; a 120-silicon wafer; 130-second metal pattern.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 3 and fig. 5, the present invention provides a method for manufacturing a light emitting diode, including:
step S101: forming an array of light emitting diode units on a substrate 10, each light emitting diode unit comprising a buffer layer 20, an n-GaN layer 30, an MQW layer 40 and a p-GaN layer 50 in a direction away from the substrate 10;
step S102: forming a first metal layer on the light emitting diode unit, and patterning the first metal layer through a patterning process to form a first metal pattern 60;
step S103: a sidewall restriction structure is formed in a partial region of the p-GaN layer 50 using the first metal pattern 60 as a mask.
In the above method for manufacturing the light emitting diode, the light emitting diode units are formed on the substrate 10 in an array, the first metal layer is formed on the side of the light emitting diode units away from the substrate 10, the first metal pattern 60 is formed by using a patterning process, and the sidewall limiting structure is formed in the p-GaN layer 50 by using the first metal pattern 60 as a mask.
The light-emitting diode prepared by the preparation method of the light-emitting diode provided by the invention forms a side wall limiting structure at a local position in the p-GaN layer 50, and the side wall limiting structure can inhibit the side wall effect.
Therefore, the preparation method of the light-emitting diode not only can realize small current injection in a large-size light-emitting diode and avoid the side wall effect, but also can be compatible with the existing semiconductor process.
It should be noted that, due to the fact that the sidewalls of the LED have a large number of defects and dangling bonds caused by patterning processes such as etching, the defects introduce impurity levels into the semiconductor energy band and cause indirect (SRH) non-radiative recombination, so that the light emitting efficiency and brightness of the LED are reduced under the same current density, that is, the sidewall effect is generated.
It is noted that the size of each led unit can be set according to the requirement, for example, the size of the led unit can be set to be less than 30 μm in the present embodiment; the substrate 10 may be a sapphire substrate, a silicon substrate, a SiC substrate, a glass substrate, or the like, and specifically, in each embodiment of the present invention, the material for preparing the substrate 10 is a sapphire substrate as an example; the MQW layer is called Multiple Quantum Well in English and called Multiple Quantum Well in Chinese.
Of course, the surface of the substrate 10 needs to be cleaned by a standard cleaning process before the light emitting diode unit is formed on the substrate 10.
In addition, the preparation process for forming the first metal layer may be one of a magnetron spraying process, a thermal evaporation process, an electron beam evaporation process, or an electroplating process, and takes the magnetron spraying process as an example: the preparation material of the first metal layer can be Ni or Cr, and the thickness is 300-500 nm; the patterning process of the first metal layer comprises photoetching, a wet etching process and a photoresist removing process, wherein the alternative process of the wet etching process is a reactive ion ICP (inductively coupled plasma) etching process or an ion beam IBE (ion beam) etching process.
On the basis of the above technical solutions, it should be noted that there are various methods for forming the sidewall limiting structure, which are at least one of the following two ways, and the specific embodiments are as follows:
the first implementation mode comprises the following steps:
in one embodiment, a horizontal structure micro light emitting diode with a p-region partially electrically modified, and specifically, a method for forming a sidewall limiting structure includes:
implanting deep-level impurity ions into the p-GaN layer 50 by using the first metal pattern 60 as a mask through an ion implantation process to form an implantation region 501, and reducing the conductivity of the implantation region 501 through a 700-and 800-DEG annealing process; the deep level impurity ions are impurity level impurity ions about 1-1.7eV from the conduction band bottom or the valence band top of GaN.
The reasons for the decrease in conductivity are specifically: (1) the ion bombardment causes lattice defects, and defect energy levels are formed in energy bands to play a role in capturing carriers; (2) after the ions enter the crystal lattice, the ions are positioned in the gap position and can play a scattering role on the current carriers. Therefore, the conductivity is reduced due to defects and the scattering of substitutional ions, and the mobility is greatly reduced, thereby significantly increasing the resistance. Furthermore, the implanted ions form a lateral electric field in the LED, further suppressing the sidewall effect, as shown in fig. 2.
Setting an ion implantation process: energy of 50-250keV and dose of 2-6 x 1013cm-2The implanted ion is N+、F+Or B+And the like. As shown in FIG. 4 as N+As a result of the experiment after ion implantation, the resistance increased by 4 orders or more at an appropriate temperature.
On the basis of the above technical solution, after reducing the conductivity of the implanted region, the method further includes:
removing the first metal pattern 60, and etching to the n-GaN layer 30 along the direction of the p-GaN layer 50 pointing to the substrate 10 by the composition process outside the coverage of the injection region 501;
forming a first insulating layer on the n-GaN layer 30, and forming a first via hole on the first insulating layer through a patterning process;
forming a first electrode layer on the first insulating layer, and forming the first electrode layer into a first electrode pattern 80 through a patterning process, the first electrode pattern 80 being connected to the n-GaN layer 30 through a first via hole;
forming a second insulating layer on the first electrode pattern 80, and forming a second via hole and a third via hole on the second insulating layer through a patterning process, wherein a vertical projection of the third via hole on the substrate 10 covers a vertical projection of the first via hole on the substrate 10;
a second electrode layer is formed on the second insulating layer, the second electrode layer partially fills the third via hole, and the second insulating layer is patterned to form a second electrode pattern 90, and the second electrode pattern 90 is connected to the p-GaN layer 50 through the second via hole, as shown in fig. 3.
It is noted that, in the method described in the above technical solution, the electrode on the n-GaN layer 30 includes a first electrode layer and a second electrode layer, and the electrode on the p-GaN layer 50 is only the second electrode layer; embodiment one the insulating layer 70 in fig. 3 includes a first insulating layer and a second insulating layer.
Note that, the process of removing the first metal pattern 60 is wet etching; the composition process of etching to the n-GaN layer 30 along the direction of the p-GaN layer 50 pointing to the substrate 10 is photoetching, ICP etching and photoresist removing; the first insulating layer and the second insulating layer are formed by Plasma Enhanced Chemical Vapor Deposition (PECVD), which can be SiOx or SiNx with a thickness of 300-500 nm; the processes for forming the first via hole and the second via hole are photolithography, RIE etching process and photoresist removing process.
In addition, the preparation process for forming the first electrode layer is a magnetron sputtering process, the preparation material is Ti or Al, the thickness is 10-30nm when the preparation material is Ti, and the thickness is 200-300nm when the preparation material is Al; the process of forming the first electrode pattern 80 from the first electrode layer is photolithography, wet etching, and photoresist removal.
Specifically, the preparation process for forming the second electrode layer is a magnetron sputtering process, the preparation material is Ni or Au or Ti or Al, the thickness is 5-30nm when the preparation material is Ni, the thickness is 5-30nm when the preparation material is Au, the thickness is 10-30nm when the preparation material is Ti, and the thickness is 600-800nm when the preparation material is Al.
On the basis of the above technical solution, when the second electrode layer is formed into the second electrode pattern 90 by the composition process, an annealing process needs to be performed in a nitrogen atmosphere, wherein the annealing condition is that the temperature is 500 ℃ and the duration is 30 min.
The second embodiment:
the second embodiment is a vertical structure micro light emitting diode with p region and n region partially reversely doped, and specifically, the method for forming the sidewall limiting structure includes:
si ions are implanted into a partial region of the p-GaN layer 50 using an ion implantation process using the first metal pattern (not shown) as a mask to form an n-type conductive region 502.
On the basis of the above technical solution, after the n-type conductive region 502 is formed, the method further includes:
removing the first metal pattern and forming an ohmic contact electrode ITO layer 100 on the p-GaN layer 50;
bonding a silicon wafer 120 on the ITO layer 100 by a bonding process;
peeling off the substrate 10;
removing the buffer layer 20;
forming a second metal layer on the n-GaN layer 30, and patterning the second metal layer through a patterning process to form a second metal pattern 130;
using the second metal pattern 130 as a mask, and implanting Mg ions into a partial region of the n-GaN layer 30 by using an ion implantation process to form a p-type conductive region;
removing the second metal pattern 130, forming an insulating layer 70 on the n-GaN layer 30, and forming a first via hole on the insulating layer 70 through a patterning process;
a first electrode layer is formed on the insulating layer 70 and is formed into a first electrode pattern 80 through a patterning process, and the first electrode pattern 80 is connected to the n-GaN layer 30 through first via holes, as shown in fig. 5 and 6.
It should be noted that the process of removing the first metal pattern is wet etching; the thickness of the ITO layer 100 is 600-800 nm; BCB paste 110 (chinese benzocyclobutene, english benzo cyclo butyl paste) is spin-coated on the surface of the ITO layer 100 before the silicon wafer 120 is bonded on the ITO layer 100 using a bonding process; the process of removing the substrate 10 is a laser lift-off LLO process; the buffer layer 20 is made of AlN or GaN.
In addition, the preparation process for forming the second metal layer may be one of a magnetron spraying process, a thermal evaporation process, an electron beam evaporation process, or an electroplating process, and takes the magnetron spraying process as an example: the preparation material of the second metal layer can be Ni or Cr, and the thickness is 300-500 nm; the second metal layer patterning process comprises photoetching, a wet etching process and a photoresist removing process, wherein the alternative process of the wet etching process is a reactive ion ICP (inductively coupled plasma) etching process or an ion beam IBE (ion beam) etching process.
The insulating layer 70 is formed by Plasma Enhanced Chemical Vapor Deposition (PECVD), which may be SiOx or SiNx with a thickness of 300-500 nm; the process for forming the first via hole comprises photoetching, RIE etching process and photoresist removing process; the preparation process for forming the first electrode layer is a magnetron sputtering process, the preparation material is Ti or Al, the thickness is 10-30nm when the preparation material is Ti, and the thickness is 200-300nm when the preparation material is Al; the process of forming the first electrode pattern 80 from the first electrode layer is photolithography, wet etching, and photoresist removal.
It should be noted that, when Mg ions are implanted, there is a certain requirement for the implantation depth of Mg ions along the direction from the n-GaN layer 30 to the p-GaN layer 50: at most, not more than the mqw layer and reaches the n-type conductive region 502 formed by the previous implantation to avoid Mg ion implantation from causing the n-type conductive region 502 formed in the p-GaN layer 50 to return to p-type conductivity.
In this embodiment, the p-GaN layer 50 is implanted with Si ions to form the n-type conductive region 502, and the n-GaN layer 30 is implanted with Mg ions to form the p-type conductive region, so that the sidewall confinement is achieved by reverse cut of the pn junction. Wherein ion implantation in the p-GaN layer 50 is a semiconductor doping process, the conductivity may be reduced or increased depending on the number of ions to be doped.
On the basis of the technical solutions in the first embodiment and the second embodiment, it should be noted that the patterning process for forming the light emitting diode units distributed in an array on the substrate 10 includes photolithography, a reactive ion ICP etching process, and a photoresist removing process.
The invention also provides a light-emitting diode which is prepared by adopting any one of the preparation methods of the light-emitting diode provided by the technical scheme.
It will be apparent to those skilled in the art that various changes and modifications may be made in the embodiments of the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (6)
1. A method for preparing a light-emitting diode is characterized by comprising the following steps:
forming light emitting diode units distributed in an array on a substrate, wherein each light emitting diode unit comprises a buffer layer, an n-GaN layer, an MQW layer and a p-GaN layer along the direction deviating from the substrate;
forming a first metal layer on the light emitting diode unit, and patterning the first metal layer through a composition process to form a first metal pattern;
forming a side wall limiting structure in the partial area of the p-GaN layer by taking the first metal pattern as a mask;
the method of forming the sidewall limiting structure comprises:
with the first metal pattern as a mask, implanting Si ions into a region of the p-GaN layer, which is not covered by the first metal pattern, by adopting an ion implantation process to form an n-type conductive region; using a second metal pattern as a mask, and adopting an ion implantation process to implant Mg ions into the region of the n-GaN layer, which is not covered by the second metal pattern, so as to form a p-type conductive region; the n-type conductive region and the p-type conductive region coincide in a vertical direction, and sidewall confinement is achieved by reverse cut of a pn junction.
2. The method of claim 1, further comprising, after forming the n-type conductive region:
removing the first metal pattern, and forming an ohmic contact electrode ITO layer on the p-GaN layer;
bonding a silicon wafer on the ITO layer by a bonding process;
peeling off the substrate;
removing the buffer layer;
forming a second metal layer on the n-GaN layer, and patterning the second metal layer through a composition process to form a second metal pattern;
using the second metal pattern as a mask, and adopting an ion implantation process to implant Mg ions into the region of the n-GaN layer, which is not covered by the second metal pattern, so as to form a p-type conductive region;
removing the second metal pattern, forming an insulating layer on the n-GaN layer, and forming a first via hole on the insulating layer through a composition process;
and forming a first electrode layer on the insulating layer, forming a first electrode pattern on the first electrode layer through a composition process, and connecting the first electrode pattern with the n-GaN layer through the first via hole.
3. The production method according to any one of claims 1 to 2, wherein a production process of forming the first metal layer is one of a magnetron sputtering process, a thermal evaporation process, an electron beam evaporation process, and an electroplating process.
4. The method of claim 3, wherein the patterning process for forming the first metal pattern is a photolithography process, an etching process and a photoresist removal process, wherein the etching process includes one of a wet etching process, a reactive ion etching process or an ion beam etching process.
5. The method according to claim 3, wherein the patterning process for forming the light emitting diode units distributed in an array on the substrate comprises a photolithography process, a reactive ion etching process and a photoresist removing process.
6. A light-emitting diode produced by the method for producing a light-emitting diode according to any one of claims 1 to 5.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10163576A (en) * | 1996-12-02 | 1998-06-19 | Toyota Central Res & Dev Lab Inc | Method for manufacturing compound semiconductor device |
| CN103078038A (en) * | 2011-10-26 | 2013-05-01 | 索尼公司 | Light emitting element, method of manufacturing the same, and light emitting device |
| CN109155345A (en) * | 2016-06-30 | 2019-01-04 | 苹果公司 | The LED structure compound for the non-radiative side wall of reduction |
| CN110010542A (en) * | 2019-04-18 | 2019-07-12 | 广东省半导体产业技术研究院 | Micro LED device, micro LED array and manufacturing method |
| CN110047984A (en) * | 2019-04-10 | 2019-07-23 | 深圳市华星光电半导体显示技术有限公司 | Micro LED component and display panel |
| CN110071198A (en) * | 2019-04-17 | 2019-07-30 | 深圳市华星光电半导体显示技术有限公司 | A kind of light-emitting component and preparation method thereof, array substrate |
| CN110212069A (en) * | 2019-04-18 | 2019-09-06 | 华灿光电（浙江）有限公司 | Light-emitting diode chip for backlight unit and preparation method thereof |
| CN110323313A (en) * | 2018-03-30 | 2019-10-11 | 脸谱科技有限责任公司 | The reduction of surface recombination loss in miniature LED |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8263422B2 (en) * | 2010-04-26 | 2012-09-11 | Varian Semiconductor Equipment Associates, Inc. | Bond pad isolation and current confinement in an LED using ion implantation |
-
2020
- 2020-03-24 CN CN202010211462.3A patent/CN111446335B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10163576A (en) * | 1996-12-02 | 1998-06-19 | Toyota Central Res & Dev Lab Inc | Method for manufacturing compound semiconductor device |
| CN103078038A (en) * | 2011-10-26 | 2013-05-01 | 索尼公司 | Light emitting element, method of manufacturing the same, and light emitting device |
| CN109155345A (en) * | 2016-06-30 | 2019-01-04 | 苹果公司 | The LED structure compound for the non-radiative side wall of reduction |
| CN110323313A (en) * | 2018-03-30 | 2019-10-11 | 脸谱科技有限责任公司 | The reduction of surface recombination loss in miniature LED |
| CN110047984A (en) * | 2019-04-10 | 2019-07-23 | 深圳市华星光电半导体显示技术有限公司 | Micro LED component and display panel |
| CN110071198A (en) * | 2019-04-17 | 2019-07-30 | 深圳市华星光电半导体显示技术有限公司 | A kind of light-emitting component and preparation method thereof, array substrate |
| CN110010542A (en) * | 2019-04-18 | 2019-07-12 | 广东省半导体产业技术研究院 | Micro LED device, micro LED array and manufacturing method |
| CN110212069A (en) * | 2019-04-18 | 2019-09-06 | 华灿光电（浙江）有限公司 | Light-emitting diode chip for backlight unit and preparation method thereof |
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