CN111446240A - MOS tube structure with electrostatic self-protection - Google Patents

Abstract

The invention discloses a MOS tube structure with electrostatic self-protection. The active area of the source area or the active area of the drain area is divided into specific shapes that are staggered and interlocked with each other through a field oxygen isolation trench. The path of the contact hole or the contact hole from the gate to the active area of the drain area is changed from a traditional straight line to a curved one, realizing the increase from the gate to the source under the smaller area of the active area of the source area and the active area of the drain area. The effective path between the area active area contact hole and the drain area active area contact hole, or between the same gate to source area active area contact hole and from gate to drain area active area The areas of the active region of the drain region and the active region of the source region are reduced under the path.

Description

MOS tube structure with electrostatic self-protection

technical field

The invention relates to the field of semiconductor device design and manufacture, in particular to a MOS tube structure with electrostatic self-protection.

Background technique

Static electricity is an objective natural phenomenon that can be generated in many ways, such as contact, friction, and induction between electrical appliances. Static electricity is characterized by long-term accumulation, high voltage, low power, low current and short duration of action. Static electricity can cause serious harm in many fields. Friction electrification and human body static electricity are two major hazards in the electronics industry, which often cause unstable operation or even damage to electronic and electrical products.

As the feature size of the manufacturing process of semiconductor integrated circuits is getting smaller and smaller, and the size of the chip unit is getting smaller and smaller, the antistatic capability of the chip becomes more and more important. Static electricity often causes permanent damage to semiconductor components and computer systems, thus affecting the circuit function of integrated circuits and making electronic products work abnormally. Therefore, some protection measures or functions must be designed to protect the chip from electrostatic discharge. destroy.

For products used in power management, the electrostatic protection solution adopts a self-protection solution due to its large area, as shown in Figure 1, which is the structure diagram of the existing self-protected metal field effect transistor, the vertical in the figure. The wire-shaped one is the polysilicon gate 1 , and the two sides of the polysilicon gate 1 are the source active region 2 and the drain active region 3 . A plurality of parallel polysilicon gates 1 are drawn out and then connected with metal 4 to form the overall gate of the MOS transistor. There are a plurality of contact holes in the active region 2 of the source region and the active region 3 of the drain region, that is, the black solid squares in FIG. 1 , and these contact holes lead out the source and drain of the MOS transistor. The so-called electrostatic self-protection means that the protected circuit itself has a certain electrostatic discharge ability, and no additional electrostatic protection measures are required; however, the self-protection ability of ordinary devices is weak due to the untargeted optimized structure. The electrostatic protection structure is used to drive high-current power devices. Although the ESD protection capability is sufficient, its area may be more than double that of ordinary devices, mainly because the metal contact holes in the drain or source regions are connected to the polysilicon gate The distance L is much larger than that of ordinary devices, and the size of L is directly related to the electrostatic protection capability of the device. The larger the L, the stronger the electrostatic protection capability. For example, ordinary devices are 0.5um, while traditional electrostatic protection structures require more than 2.5um. However, increasing the L in the existing structure will increase the area of the pipe and increase the cost.

SUMMARY OF THE INVENTION

The technical problem to be solved by the present invention is to provide a MOS tube with electrostatic self-protection, so as to ensure better electrostatic self-protection capability in a smaller tube size.

In order to solve the above problems, in the MOS tube structure with electrostatic self-protection according to the present invention, the MOS tube is placed above the semiconductor substrate as a whole, and is a MOS tube with a larger overall size formed by a plurality of sub-MOS tubes with smaller sizes. The sub-MOS transistors are arranged in a multi-finger structure.

In a top view, the source region and the drain region of the MOS device are respectively located on both sides of the polysilicon gate, and the polysilicon gate is in the form of a polysilicon line with a characteristic size and width. The gates of the sub-MOS transistors also serve as wires for connecting the gates of the multiple sub-MOS transistors.

In the active area of the entire MOS tube structure, there are a plurality of polysilicon lines arranged in parallel. Except for the two outermost active areas of the source area, the active area of the source area and the active area of the drain area in the middle area are all Adjacent MOS transistors are shared, that is, the active area of the source area or the active area of the drain area between each adjacent two polysilicon lines is used by the two adjacent polysilicon lines to form MOS transistors; Both the source active area and the drain active area have a plurality of contact holes to respectively lead out the source active area and the drain active area.

The direction perpendicular to the polysilicon line, that is, the channel direction, is defined as the X direction, and the direction of the polysilicon line, that is, the vertical direction of the channel, is defined as the Y direction.

There are a plurality of contact holes in the source active region and the drain active region of the MOS transistor.

In the drain active region and/or the drain active region of the MOS transistor, in addition to the two outermost active regions of the source region, there is also a field oxygen isolation trench, and the field oxygen isolation trench is also provided. The trench divides the active area of the source area and/or the active area of the drain area by surrounding a plurality of contact holes in the active area of the source area and/or the active area of the drain area, so that the active area from the gate to the source area is active The path of the contact hole and/or the contact hole from the gate to the active area of the drain area is changed from a straight path to a curved path, and the size of the active area of the source area and/or the active area of the drain area is reduced under the premise of ensuring the same path distance. area; or from gate to source active area contact hole and/or from gate to drain active area contact hole under the same area of source active area and/or drain active area Paths have longer distances.

Further, reducing the area of the active region of the source region and/or the active region of the drain region can reduce the overall size of the device and reduce the process cost of the device; extend the contact hole from the gate to the active region of the source region and/or from the gate to the drain The path of the contact hole in the active region can improve the electrostatic self-protection capability of the device.

In order to solve the above problems, in the MOS tube structure with electrostatic self-protection described in the present invention, the MOS tube is placed above the semiconductor substrate as a whole, and is formed by a plurality of sub-MOS tubes with smaller sizes and has a larger overall size. MOS tubes, the sub-MOS tubes are arranged in a multi-finger structure.

In a top view, the source region and the drain region of the MOS device are respectively located on both sides of the polysilicon gate, and the polysilicon gate is in the form of a polysilicon line with a characteristic size and width. The gates of the sub-MOS transistors also serve as wires for connecting the gates of the multiple sub-MOS transistors.

In the active area of the entire MOS tube structure, there are a plurality of polysilicon lines arranged in parallel. Except for the two outermost active areas of the source area, the active area of the source area and the active area of the drain area in the middle area are all Adjacent MOS transistors are shared, that is, the active area of the source area or the active area of the drain area between each adjacent two polysilicon lines is used by the two adjacent polysilicon lines to form MOS transistors; Both the source active area and the drain active area have a plurality of contact holes to respectively lead out the source active area and the drain active area.

The direction perpendicular to the polysilicon line, that is, the channel direction, is defined as the X direction, and the direction of the polysilicon line, that is, the vertical direction of the channel, is defined as the Y direction.

In the active area of the source area of the MOS transistor, there are contact holes in the active area of the source area in a single row and multiple rows.

In the active region of the drain region of the MOS transistor, there is also a field oxygen isolation trench, and the contact holes in the active region of the drain region are arranged in two rows in the Y direction, and are staggered in the X direction. Arranged in multiple rows, each row has only one contact hole, and there is a larger spacing in the Y direction between every two rows; the field oxygen isolation trench is C-shaped to surround and half surround the contact hole of the second row. The contact holes in the first row are surrounded in a C-shape and then extend down to the contact holes in the fourth row along the Y direction, and the contact holes in the fourth row are also surrounded by a C-shaped shape, and then the contact holes in the third row are surrounded in a C-shape. Then extend downward in the Y direction and repeat..., and so on, and finally divide the active regions of the drain regions of two adjacent MOS transistors into "concave" and "convex" shapes that engage with each other.

A further improvement is that the direction between the contact hole in the active region of the drain region of the MOS transistor and the gate is L-shaped, that is, from the gate to the active region of the drain region through the gap between the field oxide isolation trenches contact hole.

A further improvement is that the L-shaped trend can increase the effective path from the gate to the contact hole in the active region of the drain region while ensuring a smaller area of the active region of the drain region, or in the same direction from the gate electrode. The area of the active region of the drain region is reduced under the effective path between the contact holes of the active region of the drain region.

A further improvement is that the width of the active region of the source region in the X direction is smaller than the width of the active region of the drain region.

In order to solve the above problems, the present invention provides a MOS tube structure with electrostatic self-protection. The MOS tube is placed above the semiconductor substrate as a whole, and is a MOS tube with a larger overall size formed by a plurality of sub-MOS tubes with smaller sizes. The sub-MOS transistors are arranged in a multi-finger structure.

In a top view, the source region and the drain region of the MOS device are respectively located on both sides of the polysilicon gate, and the polysilicon gate is in the form of a polysilicon line with a characteristic size and width. The gate of each sub-MOS tube is also used as a wire connecting the gates of multiple sub-MOS tubes;

In the active area of the entire MOS tube structure, there are a plurality of polysilicon lines arranged in parallel. Except for the two outermost active areas of the source area, the active area of the source area and the active area of the drain area in the middle area are all Adjacent MOS transistors are shared, that is, the active area of the source area or the active area of the drain area between each adjacent two polysilicon lines is used by the two adjacent polysilicon lines to form MOS transistors; Both the source active area and the drain active area have a plurality of contact holes to respectively lead out the source active area and the drain active area.

The direction perpendicular to the polysilicon line, that is, the channel direction, is defined as the X direction, and the direction of the polysilicon line, that is, the vertical direction of the channel, is defined as the Y direction.

The active area of the source area of the MOS transistor has contact holes of the source area in a single row and multiple rows, and the width of the active area of the source area in the X direction is smaller than the width of the active area of the drain area.

In the active region of the drain region of the MOS transistor, there is also a field oxygen isolation trench, and the plurality of contact holes in the active region of the drain region are arranged in a row in the Y direction, and every two are in a row. A group is formed in the Y direction, and each group is separated by a larger distance in the Y direction; the field oxygen isolation trench is downward in the Y direction in a C-shape and encircles and half surrounds the contacts of the second row in each group The holes are then in a C-shaped reverse to surround the contact holes in the first row, and then go down the Y direction, then extend to the left in the X direction and down the Y axis to the contact holes of the second row in the second group, which are also C-shaped. The contact holes in the second row of the group are surrounded by half, and then the contact holes in the first row are surrounded in a C-shape, and then the Y-direction extends downward and repeats..., and so on, and finally the drain regions of the two adjacent MOS transistors are activated. The area is divided into a train hook-type interlocking form.

A further improvement is that the direction between the contact hole in the active region of the drain region and the gate of the MOS is C-shaped, that is, from the gate to the active region of the drain region through the gap between the field oxide isolation trenches contact hole.

A further improvement is that the C-shaped trend can increase the effective path from the gate to the contact hole of the active region of the drain region while ensuring a smaller area of the active region of the drain region, or in the same way from the gate to the contact hole of the active region of the drain region. The area of the active region of the drain region is reduced under the effective path between the electrode and the contact hole of the active region of the drain region.

A further improvement is that the width of the active region of the source region in the X direction is smaller than the width of the active region of the drain region.

In order to solve the above problems, the present invention provides a MOS tube structure with electrostatic self-protection. The MOS tube is placed above the semiconductor substrate as a whole, and is a MOS tube with a larger overall size formed by a plurality of sub-MOS tubes with smaller sizes. The sub-MOS transistors are arranged in a multi-finger structure.

In a top view, the source region and the drain region of the MOS device are respectively located on both sides of the polysilicon gate, and the polysilicon gate is in the form of a polysilicon line with a characteristic size and width. The gate of each sub-MOS tube is also used as a wire connecting the gates of multiple sub-MOS tubes;

In the active area of the entire MOS tube structure, there are a plurality of polysilicon lines arranged in parallel. Except for the two outermost active areas of the source area, the active area of the source area and the active area of the drain area in the middle area are all Adjacent MOS transistors are shared, that is, the active area of the source area or the active area of the drain area between each adjacent two polysilicon lines is used by the two adjacent polysilicon lines to form MOS transistors; Both the source active area and the drain active area have a plurality of contact holes to respectively lead out the source active area and the drain active area.

The direction perpendicular to the polysilicon line, that is, the channel direction, is defined as the X direction, and the direction of the polysilicon line, that is, the vertical direction of the channel, is defined as the Y direction.

In the active region of the drain region of the MOS transistor, there is also a field oxygen isolation trench, and the contact holes in the active region of the drain region are arranged in two rows in the Y direction, and are staggered in the X direction. Arranged in multiple rows, each row has only one contact hole, and there is a larger spacing in the Y direction between every two rows; the field oxygen isolation trench is C-shaped to surround and half surround the contact hole of the second row. The contact holes in the first row are surrounded in a C-shape and then extend down to the contact holes in the fourth row along the Y direction, and the contact holes in the fourth row are also surrounded by a C-shaped shape, and then the contact holes in the third row are surrounded in a C-shape. Then extend downward in the Y direction and repeat..., and so on, and finally divide the active regions of the drain regions of two adjacent MOS transistors into "concave" and "convex" shapes that engage with each other.

Except for the two outermost active regions of the source region, in the active region of the source region of the MOS transistor, there are two rows of contact holes in the active region of the source region; in the source region of the MOS transistor The active area also has a field oxygen isolation trench. The contact holes in the active area of the source area are arranged in two columns in the Y direction, and are arranged in multiple rows staggered in the X direction, and each row has only one Contact holes, and there is a larger spacing in the Y direction between every two rows; the field oxygen isolation trench is C-shaped to surround and half surround the contact holes of the second row, and then surround the contact holes of the first row in a C-shape After the hole, it extends down to the contact hole of the fourth row along the Y direction, and also surrounds the contact hole of the fourth row in a C-shape, and then surrounds the contact hole of the third row in a C-shape, and then extends downward in the Y direction and repeats... , and so on, and finally the active regions of the source regions of two adjacent MOS transistors are divided into "concave" and "convex" forms that engage with each other.

A further improvement is that the direction between the contact hole in the active region of the drain region of the MOS and the gate is L-shaped, that is, the gate starts to pass through the gap between the field oxide isolation trenches to reach the contact in the active region of the source region. The path of the hole is L-shaped; except for the outermost active region of the source region, the direction between the contact hole of the active region of the source region and the gate is L-shaped, that is, it starts from the gate and passes through the field oxygen isolation trench The path from the gap between the grooves to the contact hole in the active region of the source region is L-shaped.

A further improvement is that the L-shaped trend increases the contact holes from the gate to the active region of the source region and the active region from the gate to the drain region while ensuring a smaller active region of the drain region and the active region of the source region. The effective path between the active areas, or the active area of the drain area, the source area, and the active area of the drain area are reduced under the same effective path from the gate to the contact hole of the active area of the source area and from the gate to the active area of the drain area. area of the active area.

In order to solve the above problems, the present invention provides a MOS tube structure with electrostatic self-protection. The MOS tube is placed above the semiconductor substrate as a whole, and is a MOS tube with a larger overall size formed by a plurality of sub-MOS tubes with smaller sizes. The sub-MOS transistors are arranged in a multi-finger structure.

In a top view, the source region and the drain region of the MOS device are respectively located on both sides of the polysilicon gate, and the polysilicon gate is in the form of a polysilicon line with a characteristic size and width. The gate of each sub-MOS tube is also used as a wire connecting the gates of multiple sub-MOS tubes;

In the active area of the entire MOS tube structure, there are a plurality of polysilicon lines arranged in parallel. Except for the two outermost active areas of the source area, the active area of the source area and the active area of the drain area in the middle area are all Adjacent MOS transistors are shared, that is, the active area of the source area or the active area of the drain area between each adjacent two polysilicon lines is used by the two adjacent polysilicon lines to form MOS transistors; Both the source active area and the drain active area have a plurality of contact holes to respectively lead out the source active area and the drain active area.

The direction perpendicular to the polysilicon line, that is, the channel direction, is defined as the X direction, and the direction of the polysilicon line, that is, the vertical direction of the channel, is defined as the Y direction.

In the active region of the drain region of the MOS transistor, there is also a field oxygen isolation trench, and the plurality of contact holes in the active region of the drain region are arranged in a row in the Y direction, and every two are in a row. A group is formed in the Y direction, and each group is separated by a larger distance in the Y direction; the field oxygen isolation trench is downward in the Y direction in a C-shape and encircles and half surrounds the contacts of the second row in each group The holes are then in a C-shaped reverse to surround the contact holes in the first row, and then go down the Y direction, then extend to the left in the X direction and down the Y axis to the contact holes of the second row in the second group, which are also C-shaped. The contact holes in the second row of the group are surrounded by half, and then the contact holes in the first row are surrounded in a C-shape, and then the Y-direction extends downward and repeats..., and so on, and finally the drain regions of the two adjacent MOS transistors are activated. The area is divided into a train hook-type interlocking form.

In the active area of the source area of the MOS tube, there are contact holes in the active area of the source area in a single row and multiple rows; except for the active area in the source area located at the outermost side, the active area in the source area of the MOS tube , and also has a field oxygen isolation trench. The multiple contact holes in the active region of the source region are arranged in one column in the Y direction, and each two forms a group in the Y direction, and each group is in the Y direction. There is a larger spacing in the Y direction; the field oxygen isolation trenches in the Y direction downwards in a C-shape to surround and half surround the contact holes of the second row in each group, and then reversely surround the contact holes of the first row in a C-shape. The contact holes extend downward along the Y direction, leftward along the X direction and downward along the Y axis to the contact holes of the second row in the second group, and also encircle the contact holes of the second row in the second group in a C-shape. Then surround the contact holes in the first row in a C shape, and then extend downward in the Y direction to repeat... and so on, and finally divide the active regions of the source regions of the two adjacent MOS transistors into a shape of a train hook-type interlocking.

A further improvement is that the direction between the contact hole in the active region of the drain region of the MOS transistor and the gate is C-shaped, that is, the gate starts to pass through the gap between the field oxygen isolation trenches to reach the active region of the drain region. Area contact hole; except for the outermost active area of the source area, the direction between the contact hole of the active area of the source area of the MOS and the gate is C-shaped, that is, it starts from the gate and passes through the field oxygen isolation trench The gaps between reach the active area contact holes of the source area.

A further improvement is that the C-shaped trend increases the distance from the gate to the active region of the source region and the contact hole between the active region of the drain region and the active region of the drain region with a smaller area of the active region of the drain region and the active region of the drain region. Effective path, or reducing the area of the active area of the drain area and the active area of the source area under the same effective path from the gate to the active area of the source area and from the gate to the active area of the drain area .

The MOS tube structure with electrostatic self-protection according to the present invention is mainly increased by increasing the contact hole from the gate to the active area of the source area or the active area of the drain area without increasing the area of the active area of the source area or the active area of the drain area. It is the effective distance from the gate to the contact hole in the active region of the drain region, or on the premise that the effective distance L from the gate to the contact hole in the active region of the source region or the contact hole in the active region of the drain region remains unchanged. The area of the active region of the lower source region or the active region of the drain region remains unchanged, which improves the electrostatic self-protection capability of the device. The above-mentioned technical principles and objectives are achieved by dividing the active region of the source region or the active region of the drain region into specific shapes that are staggered and interlocked with each other by using the field oxygen isolation trench.

Description of drawings

Figure 1 is a layout of an existing MOS transistor with electrostatic self-protection.

FIG. 2 is the layout of the MOS transistor with electrostatic self-protection according to the first embodiment of the present invention.

FIG. 3 is the layout of the MOS transistor with electrostatic self-protection according to the second embodiment of the present invention.

FIG. 4 is the layout of the MOS transistor with electrostatic self-protection according to the third embodiment of the present invention.

FIG. 5 is the layout of the MOS transistor with electrostatic self-protection according to the fourth embodiment of the present invention.

FIG. 6 is a schematic diagram of the current path of electrostatic discharge in the structure of the present invention.

FIG. 7 is a schematic diagram of the implementation and application structure of the structure of the present invention.

Detailed ways

Example 1

As shown in FIG. 2, it is a MOS tube structure with electrostatic self-protection provided by the present invention. The MOS tube is placed above the semiconductor substrate as a whole, and is formed by a plurality of sub-MOS tubes with smaller sizes. For large MOS tubes, the sub-MOS tubes are arranged in a multi-finger structure.

In a top view, the source region and the drain region of the MOS device are respectively located on both sides of the polysilicon gate, and the polysilicon gate is in the form of a polysilicon line with a characteristic size and width. The gates of the sub-MOS transistors also serve as wires for connecting the gates of the multiple sub-MOS transistors.

In the active area of the entire MOS tube, there are a plurality of polysilicon lines arranged in parallel. Except for the two outermost active areas of the source area, the active area of the source area and the active area of the drain area in the middle area are all Adjacent MOS transistors are shared, that is, the active area of the source area or the active area of the drain area between each adjacent two polysilicon lines is used by the two adjacent polysilicon lines to form MOS transistors; Both the source active area and the drain active area have a plurality of contact holes to respectively lead out the source active area and the drain active area.

Define the direction perpendicular to the polysilicon line, that is, the channel direction as the X direction (including the positive X direction and the negative X direction), and define the direction of the polysilicon line, that is, the vertical direction of the channel as the Y direction (including the positive Y direction and the negative Y direction) .

In the active area of the source area of the MOS transistor, there are contact holes in the active area of the source area in a single row and multiple rows.

In the active region of the drain region of the MOS transistor, there is also a field oxygen isolation trench, and the contact holes in the active region of the drain region are arranged in two rows in the Y direction, and are staggered in the X direction. Arranged in multiple rows, each row has only one contact hole, and there is a larger spacing in the Y direction between every two rows; the field oxygen isolation trench is C-shaped to surround and half surround the contact hole of the second row. The contact holes in the first row are surrounded in a C-shape and then extend down to the contact holes in the fourth row along the Y direction, and the contact holes in the fourth row are also surrounded by a C-shaped shape, and then the contact holes in the third row are surrounded in a C-shape. Then extend downward in the Y direction and repeat... and so on, and finally divide the active regions of the drain regions of two adjacent MOS transistors into "concave" and "convex" shapes that are staggered and interlocked with each other. The width of the active region of the source region in the X direction is smaller than that of the active region of the drain region.

As shown by the arrows in FIG. 2 , the direction between the contact hole in the active area of the drain area of the MOS transistor and the gate is L-shaped, that is, from the gate to the drain through the gap between the field oxygen isolation trenches area active area contact holes.

Embodiment 2

As shown in FIG. 3, it is a MOS tube structure with electrostatic self-protection provided by the present invention. In the active area of the entire MOS tube structure, there are multiple polysilicon lines arranged in parallel, except for the two outermost source areas. Outside the active area, the active area of the source area and the active area of the drain area in the middle area are shared by the adjacent MOS transistors, that is, the active area of the source area or the drain area between each adjacent two polysilicon lines The active area is formed by the two adjacent polysilicon lines to form MOS transistors; there are multiple contact holes in the active area of the source area and the active area of the drain area. The source regions are drawn out separately.

In the active area of the source area of the MOS transistor, there are contact holes in the active area of the source area in a single row and multiple rows, which are consistent with the active area of the source area of the conventional MOS transistor.

The width of the active region of the source region in the X direction is smaller than that of the active region of the drain region.

The difference from the first embodiment is that the arrangement of the contact holes in the active region of the drain region of the second embodiment and the direction of the field oxygen isolation trench are different: in the active region of the drain region of the MOS transistor, there are also There are field oxygen isolation trenches, and the plurality of contact holes in the active region of the drain region are arranged in a row in the Y direction, and every two forms a group in the Y direction, and the Y direction between each group is The upper space is separated by a larger distance; the field oxygen isolation trenches in the Y direction downward in a C-shape surrounds and half surrounds the contact holes in the second row of each group, and then surrounds the contact holes in the first row in a C-shape reversely. The contact holes of the second row in the second group are also extended downward along the Y direction, left along the X direction and downward along the Y direction, and also encircle the contact holes of the second row in the second group in a C-shaped shape. The C-shape surrounds the contact holes in the first row, and then extends downward in the Y direction to repeat..., and so on, and finally divide the active regions of the drain regions of the two adjacent MOS transistors into train hook-type shapes that engage with each other, which is similar to In the form of the fingers of the left and right hands hooking each other.

As shown by the arrow in FIG. 3 , the direction between the contact hole in the active region of the drain region of the MOS transistor and the gate is C-shaped, that is, the gate starts to pass through the gap between the field oxygen isolation trenches to reach the gate. The contact hole of the active region of the drain region forms a C-shaped path.

Embodiment 3

As shown in FIG. 4, it is a MOS tube structure with electrostatic self-protection provided by the present invention. The third embodiment is basically the same as the first embodiment, and the direction of the field oxygen isolation trench and the arrangement of the contact holes are the same, and the difference is different. The point is that in the source active area of the third embodiment, except for the outermost two source active areas, the rest of the source active areas also maintain the same layout design as the drain active areas:

Except for the two outermost active regions of the source region, in the active region of the source region of the MOS transistor, there are two rows of contact holes in the active region of the source region; in the source region of the MOS transistor The active area also has a field oxygen isolation trench. The contact holes in the active area of the source area are arranged in two columns in the Y direction, and are arranged in multiple rows staggered in the X direction, and each row has only one Contact holes, and there is a larger spacing in the Y direction between every two rows; the field oxygen isolation trench is C-shaped to surround and half surround the contact holes of the second row, and then surround the contact holes of the first row in a C-shape After the hole, it extends down to the contact hole of the fourth row along the Y direction, and also surrounds the contact hole of the fourth row in a C-shape, and then surrounds the contact hole of the third row in a C-shape, and then extends downward in the Y direction and repeats... , and so on, and finally the active regions of the source regions of two adjacent MOS transistors are divided into "concave" and "convex" forms that engage with each other.

Therefore, the direction between the contact hole in the active region of the drain region and the gate and the path between the contact hole in the active region in the source region and the gate of the MOS transistor are L-shaped, that is, the field oxygen starts from the gate. The path from the gap between the isolation trenches to the contact hole in the active region of the source region is L-shaped.

Embodiment 4

As shown in FIG. 5, it is a MOS tube structure with electrostatic self-protection provided by the present invention. The fourth embodiment is basically the same as the second embodiment, and the direction of the field oxygen isolation trench and the arrangement of the contact holes are the same, but different The point is that in the source active area of the fourth embodiment, except for the two outermost active areas of the source area, the remaining active areas of the source area also maintain the same layout design as the active area of the drain area: except for the most active area of the source area In addition to the two outer active regions of the source region, the active region of the source region of the MOS transistor also has a field oxygen isolation trench, and the plurality of contact holes in the active region of the source region are in the Y direction. The upper row is 1 column, and every two forms a group in the Y direction, and there is a larger space between each group in the Y direction; the field oxygen isolation trench is C-shaped downward in the Y direction The contact holes in the second row of each group are encircled and half-enclosed, and then the contact holes in the first row are reversely surrounded in a C-shape, and then extend downward along the Y direction, leftward along the X direction, and downward along the Y axis to the second group. The contact holes in the second row also encircle the contact holes in the second row in a C-shape, and then surround the contact holes in the first row in a C-shape, and then extend downward in the Y direction. Repeat... and so on. The active regions of the source regions of two adjacent MOS transistors are divided into a shape of a train hook type interlocking with each other.

Therefore, the direction between the contact hole in the active region of the drain region and the gate, and the direction between the contact hole in the active region in the source region and the gate of the MOS transistor are C-shaped, that is, the field starts from the gate and passes through the field. The gap between the oxygen isolation trenches reaches the contact hole in the active region of the drain region, and the direction from the gate to the contact hole in the active region of the source region through the gap between the field oxygen isolation trenches is C-shaped.

The main technical idea of the MOS tube structure with electrostatic self-protection according to the present invention is to increase the contact from the gate to the active area of the source area without increasing the area of the active area of the source area or the active area of the drain area The hole is either the effective distance L from the gate to the contact hole in the active region of the drain region; Under the premise of changing, the area of the active region of the source region or the active region of the drain region is unchanged or even reduced, which improves the electrostatic self-protection capability of the device. The active area of the source area or the active area of the drain area is divided into specific shapes that are staggered and interlocked with each other by the field oxide isolation trench. The path direction is changed from the traditional straight line to the zigzag L-shaped or C-shaped direction, so as to increase the contact holes from the gate to the active area of the source area and the active area of the drain area with a smaller area of the active area of the source area and the active area of the drain area. The effective path between the contact holes in the active area of the drain area, or the effective path from the gate to the active area of the source area and the effective path from the gate to the active area of the drain area is reduced. Source area, source area The area of the active area.

As shown in FIG. 6 , the current path is described with the structure of the first embodiment of the present invention, and the NMOS is shown in the figure. Due to the existence of the field oxide isolation trench, the active region of the drain region is divided into the form of concave and convex occlusion. When static electricity enters the electrostatic protection device structure of the present invention from the drain, it flows out from the metal contact hole in the source region through the channel, and the distance from the polysilicon gate to the drain and source contact holes in the entire current path remains a distance L (same as the traditional electrostatic protection structure) does not shorten the distance L due to the reduction of the area of the drain-source region, thus ensuring that the electrostatic capacity remains unchanged, while the occupied area is reduced.

7 is a schematic diagram of the application of the present invention. When the structure of the present invention has electrostatic discharge input, the static electricity is discharged to the ground through the structure of the present invention.

The above are only preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and variations of the present invention are possible for those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims (16)

1. The utility model provides a MOS tubular structure of electrostatic self preservation protects which characterized in that: the MOS tube is integrally arranged above the semiconductor substrate and is an MOS tube with a larger overall size formed by a plurality of sub-MOS tubes with smaller sizes, and the sub-MOS tubes are arranged into a multi-finger structure;

on a top plane, a source region and a drain region of the MOS device are respectively positioned at two sides of a polycrystalline silicon grid, the polycrystalline silicon grid is in the shape of a polycrystalline silicon line with a characteristic dimension width, and the polycrystalline silicon line is used as a grid of a plurality of sub-MOS tubes and is also used as a lead for connecting and leading out the grids of the plurality of sub-MOS tubes;

the active region of the whole MOS tube structure is provided with a plurality of polysilicon lines which are arranged in parallel, except for the active regions of the source regions at the two outermost sides, the active regions of the source region and the active regions of the drain region in the middle region are shared by adjacent MOS tubes, namely the active regions of the source region or the active regions of the drain region between every two adjacent polysilicon lines are respectively utilized by the two adjacent polysilicon lines to form the MOS tubes; a plurality of contact holes are formed in the source region active region and the drain region active region to lead out the source region active region and the drain region active region respectively;

defining the direction vertical to the polysilicon line, namely the channel direction as an X direction, and defining the trend direction of the polysilicon line, namely the vertical direction of the channel as a Y direction;

a plurality of contact holes are formed in the source region active region and the drain region active region of the MOS tube;

in the drain region active region and/or the drain region active region of the MOS transistor, a field oxide isolation groove is arranged besides two source region active regions positioned on the outermost side, and the field oxide isolation groove divides the source region active region and/or the drain region active region by surrounding a plurality of contact holes in the source region active region and/or the drain region active region, so that the path from a grid electrode to the source region active region contact hole and/or from the grid electrode to the drain region active region contact hole is changed into a curved path or a snake-shaped path from a straight path, and the area of the source region active region and/or the drain region active region is reduced on the premise of ensuring the same path distance; or the path from the gate to the source region contact hole and/or from the gate to the drain region contact hole has a longer distance under the same area of the source region active region and/or the drain region active region.

2. The esd self-protected MOS structure of claim 1, wherein: the area of the active region of the source region and/or the active region of the drain region is reduced, so that the overall size of the device can be reduced, and the process cost of the device can be reduced; extending the path from the gate to the source region contact opening and/or from the gate to the drain region contact opening can improve the electrostatic self-protection capability of the device.

3. The utility model provides a MOS tubular structure of electrostatic self preservation protects which characterized in that: the MOS tube is integrally arranged above the semiconductor substrate and is an MOS tube with a larger overall size formed by a plurality of sub-MOS tubes with smaller sizes, and the sub-MOS tubes are arranged into a multi-finger structure;

on a top plane, a source region and a drain region of the MOS device are respectively positioned at two sides of a polycrystalline silicon grid, the polycrystalline silicon grid is in the shape of a polycrystalline silicon line with a characteristic dimension width, and the polycrystalline silicon line is used as a grid of a plurality of sub-MOS tubes and is also used as a lead for connecting and leading out the grids of the plurality of sub-MOS tubes;

the active region of the whole MOS tube structure is provided with a plurality of polysilicon lines which are arranged in parallel, except for the active regions of the source regions at the two outermost sides, the active regions of the source region and the active regions of the drain region in the middle region are shared by adjacent MOS tubes, namely the active regions of the source region or the active regions of the drain region between every two adjacent polysilicon lines are respectively utilized by the two adjacent polysilicon lines to form the MOS tubes; a plurality of contact holes are formed in the source region active region and the drain region active region to lead out the source region active region and the drain region active region respectively;

defining the direction vertical to the polysilicon line, namely the channel direction as an X direction, and defining the trend direction of the polysilicon line, namely the vertical direction of the channel as a Y direction;

the MOS tube is characterized in that a single-column multi-row active region contact hole is formed in an active region of the MOS tube;

the MOS transistor is characterized in that a drain region active region of the MOS transistor is also provided with a field oxide isolation groove, contact holes in the drain region active region are arranged into two columns in the Y direction, and are staggered into a plurality of rows in the X direction, each row is provided with only one contact hole, and every two rows are spaced by a larger distance in the Y direction; the field oxide isolation trench surrounds the contact holes in the second row in a C-shaped mode, surrounds the contact holes in the first row in a C-shaped mode, then extends downwards to the contact holes in the fourth row along the Y direction, surrounds the contact holes in the fourth row in a C-shaped mode, surrounds the contact holes in the third row in a C-shaped mode, extends downwards in the Y direction repeatedly … …, and the like, and finally divides the drain region active regions of two adjacent MOS tubes into a concave and convex mutually-meshed state.

4. The MOS transistor structure with electrostatic self-protection as claimed in claim 3, wherein the contact hole of the drain region active region of the MOS transistor is L type with the gate, i.e. from the gate to the contact hole of the drain region active region through the gap between the field oxide isolation trenches.

5. The MOS transistor structure with electrostatic self-protection as claimed in claim 4, wherein said L-type trend can increase the effective path between the contact holes of the gate and the drain active region under the condition of ensuring smaller area of the drain active region, or decrease the area of the drain active region under the same effective path between the contact holes of the gate and the drain active region.

6. The esd self-protected MOS structure of claim 3, wherein: the width of the source region active region in the X direction is smaller than the width of the drain region active region.

7. The utility model provides a MOS tubular structure of electrostatic self preservation protects which characterized by: the MOS tube is integrally arranged above the semiconductor substrate and is an MOS tube with a larger overall size formed by a plurality of sub-MOS tubes with smaller sizes, and the sub-MOS tubes are arranged into a multi-finger structure;

on a top plane, a source region and a drain region of the MOS device are respectively positioned at two sides of a polycrystalline silicon grid, the polycrystalline silicon grid is in the shape of a polycrystalline silicon line with a characteristic dimension width, and the polycrystalline silicon line is used as a grid of a plurality of sub-MOS tubes and is also used as a lead for connecting and leading out the grids of the plurality of sub-MOS tubes;

the active region of the whole MOS tube structure is provided with a plurality of polysilicon lines which are arranged in parallel, except for the active regions of the source regions at the two outermost sides, the active regions of the source region and the active regions of the drain region in the middle region are shared by adjacent MOS tubes, namely the active regions of the source region or the active regions of the drain region between every two adjacent polysilicon lines are respectively utilized by the two adjacent polysilicon lines to form the MOS tubes; a plurality of contact holes are formed in the source region active region and the drain region active region to lead out the source region active region and the drain region active region respectively;

defining the direction vertical to the polysilicon line, namely the channel direction as an X direction, and defining the trend direction of the polysilicon line, namely the vertical direction of the channel as a Y direction;

the MOS tube is characterized in that a source region active region of the MOS tube is provided with a plurality of rows of source region active region contact holes in a single column, and the width of the source region active region in the X direction is smaller than that of the drain region active region;

the MOS transistor is characterized in that a drain region active region of the MOS transistor is also provided with a field oxide isolation groove, a plurality of contact holes in the drain region active region are arranged in 1 row in the Y direction, every two contact holes form a group in the Y direction, and each group is spaced by a larger distance in the Y direction; the field oxygen isolation groove is downward in a Y direction and surrounds and semi-surrounds the contact holes in the second row in each group in a C shape, then reversely surrounds the contact holes in the first row in a C shape, then downwards in the Y direction and downwards extends to the contact holes in the second row in the second group in the X direction and the Y axis, the contact holes in the second row in the group are also surrounded and semi-surrounded in a C shape, then the contact holes in the first row are repeatedly … … in a Y direction and downwards extending, and the like, and finally the drain region active regions of two adjacent MOS tubes are divided into train hook type mutually meshed shapes.

8. The esd self-protected MOS structure of claim 7, wherein: the direction between the drain region active region contact hole of the MOS and the grid is C-shaped, namely the grid penetrates through the gap between the field oxide isolation trenches to reach the drain region active region contact hole.

9. The esd self-protected MOS structure of claim 8, wherein: the C-shaped trend can increase the effective path from the grid to the contact hole of the drain region active region under the condition of ensuring the smaller area of the drain region active region, or reduce the area of the drain region active region under the same effective path from the grid to the contact hole of the drain region active region.

10. The esd self-protected MOS structure of claim 7, wherein: the width of the source region active region in the X direction is smaller than the width of the drain region active region.

11. The utility model provides a MOS tubular structure of electrostatic self preservation protects which characterized by: the MOS tube is integrally arranged above the semiconductor substrate and is an MOS tube with a larger overall size formed by a plurality of sub-MOS tubes with smaller sizes, and the sub-MOS tubes are arranged into a multi-finger structure;

on a top plane, a source region and a drain region of the MOS device are respectively positioned at two sides of a polycrystalline silicon grid, the polycrystalline silicon grid is in the shape of a polycrystalline silicon line with a characteristic dimension width, and the polycrystalline silicon line is used as a grid of a plurality of sub-MOS tubes and is also used as a lead for connecting and leading out the grids of the plurality of sub-MOS tubes;

the active region of the whole MOS tube structure is provided with a plurality of polysilicon lines which are arranged in parallel, except for the active regions of the source regions at the two outermost sides, the active regions of the source region and the active regions of the drain region in the middle region are shared by adjacent MOS tubes, namely the active regions of the source region or the active regions of the drain region between every two adjacent polysilicon lines are respectively utilized by the two adjacent polysilicon lines to form the MOS tubes; a plurality of contact holes are formed in the source region active region and the drain region active region to lead out the source region active region and the drain region active region respectively;

defining the direction vertical to the polysilicon line, namely the channel direction as an X direction, and defining the trend direction of the polysilicon line, namely the vertical direction of the channel as a Y direction;

the MOS transistor is characterized in that a drain region active region of the MOS transistor is also provided with a field oxide isolation groove, contact holes in the drain region active region are arranged into two columns in the Y direction, and are staggered into a plurality of rows in the X direction, each row is provided with only one contact hole, and every two rows are spaced by a larger distance in the Y direction; the field oxygen isolation trench surrounds the contact holes in the second row in a C-shaped manner, surrounds the contact holes in the first row in a C-shaped manner, then extends downwards to the contact holes in the fourth row along the Y direction, surrounds the contact holes in the fourth row in a C-shaped manner, surrounds the contact holes in the third row in a C-shaped manner, extends downwards in the Y direction repeatedly … …, and so on, and finally divides the drain region active regions of two adjacent MOS tubes into a concave and convex mutually-meshed state;

except two source region active regions positioned at the outermost side, two columns and multiple rows of source region active region contact holes are formed in the source region active regions of the MOS tube; the MOS transistor comprises a source region active region, a field oxide isolation groove, a drain electrode, a source electrode, a drain electrode and a drain electrode, wherein the source region active region of the MOS transistor is also provided with the field oxide isolation groove, contact holes in the source region active region are arranged in two lines in the Y direction, a plurality of staggered rows are arranged in; the field oxygen isolation groove surrounds the contact holes in the second row in a C-shaped mode, surrounds the contact holes in the first row in a C-shaped mode, then extends downwards to the contact holes in the fourth row in the Y direction, surrounds the contact holes in the fourth row in a C-shaped mode, surrounds the contact holes in the third row in a C-shaped mode, extends downwards in the Y direction repeatedly … …, and the like, and finally divides the active regions of the source regions of two adjacent MOS tubes into a concave and convex mutually-meshed mode.

12. The MOS transistor structure with electrostatic self-protection as claimed in claim 11, wherein the MOS transistor has a contact hole between the drain region active region contact hole and the gate electrode of L type, i.e., the path from the gate electrode to the source region active region contact hole through the gap between the field oxide isolation trenches is L type, and the contact hole between the source region active region contact hole and the gate electrode except the outermost source region active region is L type, i.e., the path from the gate electrode to the source region active region contact hole through the gap between the field oxide isolation trenches is L type.

13. The MOS transistor structure with electrostatic self-protection as claimed in claim 12, wherein said L-type trend increases the effective path from the gate to the source contact hole and from the gate to the drain active region under the condition of ensuring smaller area of the drain active region and the source active region, or decreases the area of the drain active region and the source active region under the same effective path from the gate to the source contact hole and from the gate to the drain active region.

14. The utility model provides a MOS tubular structure of electrostatic self preservation protects which characterized by: the MOS tube is integrally arranged above the semiconductor substrate and is an MOS tube with a larger overall size formed by a plurality of sub-MOS tubes with smaller sizes, and the sub-MOS tubes are arranged into a multi-finger structure;

on a top plane, a source region and a drain region of the MOS device are respectively positioned at two sides of a polycrystalline silicon grid, the polycrystalline silicon grid is in the shape of a polycrystalline silicon line with a characteristic dimension width, and the polycrystalline silicon line is used as a grid of a plurality of sub-MOS tubes and is also used as a lead for connecting and leading out the grids of the plurality of sub-MOS tubes;

the active region of the whole MOS tube structure is provided with a plurality of polysilicon lines which are arranged in parallel, except for the active regions of the source regions at the two outermost sides, the active regions of the source region and the active regions of the drain region in the middle region are shared by adjacent MOS tubes, namely the active regions of the source region or the active regions of the drain region between every two adjacent polysilicon lines are respectively utilized by the two adjacent polysilicon lines to form the MOS tubes; a plurality of contact holes are formed in the source region active region and the drain region active region to lead out the source region active region and the drain region active region respectively;

defining the direction vertical to the polysilicon line, namely the channel direction as an X direction, and defining the trend direction of the polysilicon line, namely the vertical direction of the channel as a Y direction;

the MOS transistor is characterized in that a drain region active region of the MOS transistor is also provided with a field oxide isolation groove, a plurality of contact holes in the drain region active region are arranged in 1 row in the Y direction, every two contact holes form a group in the Y direction, and each group is spaced by a larger distance in the Y direction; the field oxygen isolation groove surrounds the contact holes in the second row in each group in a C-shaped mode downwards in the Y direction, surrounds the contact holes in the second row in each group in a C-shaped mode, reversely surrounds the contact holes in the first row in a C-shaped mode, then extends downwards along the Y direction, extends to the contact holes in the second row in the second group leftwards along the X direction and downwards along the Y axis, surrounds the contact holes in the second row in the group in a C-shaped mode, surrounds the contact holes in the first row in a C-shaped mode, extends downwards along the Y direction repeatedly … …, and the like, and finally divides the drain region active regions of two adjacent MOS tubes into train hook type mutually-meshed states;

the MOS tube is characterized in that a single-column multi-row active region contact hole is formed in an active region of the MOS tube; the MOS transistor comprises a source region active region, a field oxide isolation groove, a plurality of contact holes and a plurality of field oxide isolation grooves, wherein the source region active region is positioned on the outermost side, the source region active region of the MOS transistor is also provided with the field oxide isolation groove, the contact holes in the source region active region are arranged in 1 row in the Y direction, every two contact holes form a group in the Y direction, and each group is spaced by a larger distance in the Y direction; the field oxygen isolation groove is downward in a Y direction and surrounds and semi-surrounds the contact holes in the second row in each group in a C shape, then reversely surrounds the contact holes in the first row in a C shape, then downwards in the Y direction and downwards extends to the contact holes in the second row in the second group in the X direction and the Y axis, the contact holes in the second row in the group are also surrounded and semi-surrounded in a C shape, then the contact holes in the first row are repeatedly … … in a Y direction and downwards in an extending mode, and the like, and finally the active regions of two adjacent MOS tubes are divided into train hook-type mutually-meshed shapes.

15. The esd self-protected MOS structure of claim 14, wherein: the direction between the drain region active region contact hole of the MOS tube and the grid is C-shaped, namely the MOS tube penetrates through a gap between the field oxide isolation trenches from the grid to reach the drain region active region contact hole; except for the source region active region on the outermost side, the direction between the source region active region contact hole of the MOS and the grid is C-shaped, namely the grid penetrates through the gap between the field oxide isolation trenches to reach the source region active region contact hole.

16. The esd self-protected MOS structure of claim 15, wherein: the C-shaped trend increases the effective path from the grid to the source region active region and the contact hole of the drain region active region under the smaller area of the drain region active region and the drain region active region, or reduces the area of the drain region active region and the source region active region under the same effective path from the grid to the contact hole of the source region active region and from the grid to the drain region active region.

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