CN111414199B - A method and device for realizing instruction fusion - Google Patents

Abstract

The invention relates to microprocessor design technology, in particular to a method and device for implementing instruction fusion. The method of the invention combines a prefix instruction and the next instruction that can be fused with it into a fusion instruction in the decoding stage, and the source operation of the prefix instruction The number becomes a source operand of the fused instruction, replacing the implicit source operand. If the fused instruction is submitted normally in the commit phase, the commit address is advanced by two instructions. If an exception occurs in the fused instruction, the exception is reported at the prefix instruction. The prefix instruction Architecture state is not updated, and the exception return address is the address of the prefixed instruction. The invention can effectively realize instruction fusion, has simple design, and can ensure accurate exception.

Description

A method and device for realizing instruction fusion

technical field

The invention relates to microprocessor design technology, in particular to a method and device for realizing instruction fusion.

Background technique

When the processor architecture with a fixed instruction length expands new instructions, due to the increase in the number of instructions, more coded bits are needed as opcodes to represent the instruction function. After removing the opcode, the remaining bits in the instruction code can represent the operation. The number is limited, so some instructions may not be encoded properly. For example, under normal circumstances, a floating-point multiply-add instruction requires 3 source operands and 1 destination operand, we use FPMA Rd, Rs1, Rs2, Rs3 to represent, the function completed by this instruction is Rd=(Rs1xRs2)+Rs3 . The architecture usually defines 32 software-visible floating-point registers. A floating-point register operand requires 5 bits to represent, and 3 source operands and 1 destination operand require 20-bit instruction codes. When the operands of 4 floating-point register types cannot be encoded, the architecture uses the accumulate multiply instruction. Such an instruction only explicitly encodes 2 source operands and 1 destination operand. We use FPFMA Rd, RS1, Rs2 to represent, the purpose The operand Rd is implicitly used as a source operand, and the completed function is Rd=(Rs1xRs2)+Rd. The accumulative multiplication instruction also completes the floating-point multiplication and addition function, but it is a destructive instruction, and the addend in the multiplication and addition operation is The content is broken. Assuming that the function of the normal floating-point multiply-accumulate instruction (Rs1xRs2)+Rs3 is to be completed, it is FPFMA Rs3, Rs1, Rs2 if it is completed by the multiply-accumulate instruction, that is, Rs3=(Rs1xRs2)+Rs3, and the addend Rs3 is rewritten.

Some architectures define a prefix instruction, which is used to complete the non-destructive instruction function together with the instruction immediately following it. For the convenience of description, we use PREFIX Rd, Rs to represent the prefix instruction. Its function is to write the value in the floating-point register Rs to Rd. This instruction can be fused with the following instruction that meets certain conditions into one instruction for execution. . For example, we use the following prefix instructions and multiply-accumulate instructions to perform normal floating-point multiply-accumulate functions:

PREFIX Rd, Rs3

FPFMA Rd, Rs1, Rs2

The function completed by the above two instructions is: Rd=(Rs1xRs2)+Rs3.

The architecture requires that when the microprocessor is designed, the prefix instruction and the subsequent instruction that can be fused with it (for the convenience of description, we call it the prefixed instruction) can be executed separately or fused into one instruction. No matter which method is used to execute, when an exception occurs in the prefixed instruction, it must ensure that the precise exception can be realized, that is, if the prefixed instruction updates the architectural state, then the exception is reported at the prefixed instruction, and the abnormal return address is the address of the prefixed instruction , if the prefix instruction does not update the architectural state, then the exception is reported at the prefix instruction, and the exception return address is the address of the prefix instruction.

In summary, when designing a microprocessor, it is easier to execute the prefix instruction and the prefixed instruction separately, but if they are combined into one instruction, it will benefit the performance and power consumption of the processor. How to ensure that the design meets the requirements of the architecture? The requirements are a challenge.

Contents of the invention

The technical problem to be solved by the present invention: Aiming at the above-mentioned problems in the prior art, a method and device for realizing instruction fusion are provided. The present invention can effectively realize instruction fusion, which is conducive to improving the performance of the processor and reducing the power consumption of the processor. And the design is simple, which can guarantee the realization of precise exception.

In order to solve the problems of the technologies described above, the technical solution adopted in the present invention is:

A method for realizing instruction fusion, the implementation steps comprising:

1) In the instruction fetch phase, the instruction is fetched;

2) In the decoding stage, it is judged whether there are prefix instructions and prefixed instructions that meet the fusion conditions appearing consecutively and being decoded at the same time. If so, the prefix instruction is fused to the prefixed instruction to form an instruction, and The instruction is marked as a fused instruction, and the source operand of the prefix instruction becomes a source operand of the fused instruction, replacing the implicit source operand; if not, the instruction is decoded normally;

3) Rename, dispatch and execute the instruction. If the instruction is a fused instruction, add a flag bit to the fused instruction, and pass the additional flag bit along the pipeline step by step;

4) In the submission stage, judge whether the fusion instruction with the additional flag bit is abnormal. If there is no abnormality in the fusion instruction, submit the fusion instruction and advance the submission address by two instructions. If the fusion instruction is abnormal, the fusion instruction cannot be submitted, and the prefix instruction Neither the prefix instruction nor the prefixed instruction update the architectural state, and the current commit address stays at the prefix instruction, so an exception is reported at the prefix instruction, and the exception return address is the address of the prefix instruction.

Optionally, the detailed steps of step 2) include:

2.1) Determine whether the prefix instruction is included in the instruction decoded at the same time, if it is included, skip to step 2.2); otherwise, skip to step 2.6);

2.2) Determine whether the prefix instruction is the last valid instruction, if not, jump to step 2.3), otherwise jump to step 2.6);

2.3) Determine whether the next instruction of the prefix instruction satisfies the fusion condition and can be fused with the prefix instruction. If the fusion condition is met, then jump to step 2.4), otherwise jump to step 2.6);

2.4) Fuse the prefix instruction into the next instruction to form an instruction, mark the instruction as a fusion instruction, and then jump to step 2.5);

2.5) The source operand of the prefix instruction becomes a source operand of the fusion instruction, replacing the implicit source operand, and then jumps to step 3);

2.6) Perform normal decoding, and then jump to step 3).

Optionally, the detailed steps of step 4) include:

4.1) According to the flag bit passed through the pipeline step by step, it is judged whether the instruction entering the submission stage is a fusion instruction. If it is a jump, execute step 4.2); otherwise, skip and execute step 4.5);

4.2) Judging whether an exception has occurred in the fusion instruction, if an exception occurs, jump to step 4.3), otherwise jump to step 4.4);

4.3) Report an exception at the prefix instruction, and the exception return address is the address of the prefix instruction;

4.4) Submit the fusion command, and submit the address to advance two commands;

4.5) Judging whether an exception has occurred in the non-fusion instruction, if so, jump to step 4.6), otherwise jump to step 4.7);

4.6) An exception is reported at the instruction, and the exception return address is the address of the instruction;

4.7) Submit the instruction, and the submission address advances by one instruction.

In addition, the present invention also provides a device for implementing instruction fusion, the device for implementing instruction fusion is programmed or configured to execute the steps of the method for implementing instruction fusion.

In addition, the present invention also provides a microprocessor, which is programmed or configured to execute the steps of the implementation method of instruction fusion.

Compared with the prior art, the present invention has the following advantages:

1. The present invention is simple in design. In the decoding stage, the present invention judges whether there are prefix instructions and prefixed instructions that meet the fusion conditions appearing continuously and being decoded at the same time. If so, the prefix instruction is fused to the prefixed instruction to form an instruction, and the instruction is marked For fused instructions, the flag bits are passed along the pipeline step by step, and the commit address is updated according to the flag bits in the commit phase, so the pipeline design is simple.

2. The present invention can guarantee the implementation of precise exceptions. In the present invention, when instruction fusion occurs, if the fusion instruction is submitted normally, the submission address advances two instructions, and if the fusion instruction is abnormal, an exception is reported at the prefix instruction, and the prefix instruction does not update the architectural state, and the abnormal return address is the address of the prefix instruction , which implements the exact exception.

Description of drawings

Fig. 1 is a schematic flow diagram of the basic process of the method of the embodiment of the present invention.

Fig. 2 is a schematic diagram of a detailed implementation process of an embodiment of the present invention.

Detailed ways

As shown in Figure 1, the implementation steps of the implementation method of instruction fusion in this embodiment include:

1) In the instruction fetching stage, the instruction is fetched; this step is the same as the prior art;

2) In the decoding stage, it is judged whether there are prefix instructions and prefixed instructions that meet the fusion conditions appearing consecutively and being decoded at the same time. If so, the prefix instruction is fused to the prefixed instruction to form an instruction, and The instruction is marked as a fused instruction, and the source operand of the prefix instruction becomes a source operand of the fused instruction, replacing the implicit source operand; if not, the instruction is decoded normally;

3) Rename, dispatch and execute the instruction. If the instruction is a fused instruction, add a flag bit to the fused instruction, and pass the additional flag bit along the pipeline step by step; this step has no difference between the fused instruction and the normal instruction;

4) In the submission stage, judge whether the fusion instruction with the additional flag bit is abnormal. If there is no abnormality in the fusion instruction, submit the fusion instruction and advance the submission address by two instructions. If the fusion instruction is abnormal, the fusion instruction cannot be submitted, and the prefix instruction Neither the prefixed instruction nor the prefixed instruction update the architectural state, and the current submission address stays at the prefixed instruction, so an exception is reported at the prefixed instruction, and the exception return address is the address of the prefixed instruction, so that floating-point accurate exceptions can be realized, which meets the requirements of the architecture .

In step 2) of this embodiment, the fusion condition is to judge whether there are prefix instructions and prefixed instructions that meet the fusion condition appear consecutively and are decoded at the same time. Therefore, if the prefix instruction is the last one of the effective instructions decoded at the same time, then instruction fusion will not occur, and the prefix instruction will be decoded normally and enter the renaming station without waiting for the arrival of subsequent instructions, so even if the program follows the prefix instruction Subsequent instructions can be fused with it, but fusion will not occur because it does not reach the decoding stage at the same time as the prefix instruction.

In this embodiment, the detailed steps of step 2) include:

2.1) Determine whether the prefix instruction is included in the instruction decoded at the same time, if it is included, skip to step 2.2); otherwise, skip to step 2.6);

2.2) Determine whether the prefix instruction is the last valid instruction, if not, jump to step 2.3), otherwise jump to step 2.6);

2.3) Determine whether the next instruction of the prefix instruction satisfies the fusion condition and can be fused with the prefix instruction. If the fusion condition is met, then jump to step 2.4), otherwise jump to step 2.6);

2.4) Fuse the prefix instruction into the next instruction to form an instruction, mark the instruction as a fusion instruction, and then jump to step 2.5);

2.5) The source operand of the prefix instruction becomes a source operand of the fusion instruction, replacing the implicit source operand, and then jumps to step 3);

2.6) Perform normal decoding, and then jump to step 3).

As shown in Figure 2, the detailed steps of step 4) include:

4.1) According to the flag bit passed through the pipeline step by step, it is judged whether the instruction entering the submission stage is a fusion instruction. If it is a jump, execute step 4.2); otherwise, skip and execute step 4.5);

4.2) Judging whether an exception has occurred in the fusion instruction, if an exception occurs, jump to step 4.3), otherwise jump to step 4.4);

4.3) Report an exception at the prefix instruction, and the exception return address is the address of the prefix instruction;

4.4) Submit the fusion command, and submit the address to advance two commands;

4.5) Judging whether an exception has occurred in the non-fusion instruction, if so, jump to step 4.6), otherwise jump to step 4.7);

4.6) An exception is reported at the instruction, and the exception return address is the address of the instruction;

4.7) Submit the instruction, and the submission address advances by one instruction.

To sum up, the implementation method of instruction fusion in this embodiment judges in the decoding stage whether there are prefix instructions and prefixed instructions that meet the fusion conditions appear consecutively and are decoded at the same time. If so, then fuse the prefix instruction to the prefixed instruction A fused instruction is formed on the instruction, and the source operand of the prefix instruction becomes a source operand of the fused instruction, replacing the implicit source operand. If the fused instruction is submitted normally during the commit phase, the commit address advances two instructions. If the fused instruction An exception occurs, the exception is reported at the prefix instruction, the prefix instruction does not update the architectural state, and the exception return address is the address of the prefix instruction. The invention has a simple design and can guarantee accurate abnormality.

In addition, this embodiment also provides a device for implementing instruction fusion, which is programmed or configured to execute the steps of the method for implementing instruction fusion.

In addition, this embodiment also provides a microprocessor, which is programmed or configured to execute the steps of the method for implementing instruction fusion.

Those skilled in the art should understand that the embodiments of the present application may be provided as methods, systems, or computer program products. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein. The present application is described with reference to flowcharts and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present application. It should be understood that each procedure and/or block in the flowchart and/or block diagram, and combinations of procedures and/or blocks in the flowchart and/or block diagram can be realized by computer program instructions. These computer program instructions may be provided to a general purpose computer, special purpose computer, embedded processor, or processor of other programmable data processing equipment to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing equipment produce a Means for realizing the functions specified in one or more steps of the flowchart and/or one or more blocks of the block diagram. These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to operate in a specific manner, such that the instructions stored in the computer-readable memory produce an article of manufacture comprising instruction means, the instructions The device realizes the function specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram. These computer program instructions can also be loaded onto a computer or other programmable data processing device, causing a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process, thereby The instructions provide steps for implementing the functions specified in the flow chart flow or flows and/or block diagram block or blocks.

The above descriptions are only preferred implementations of the present invention, and the protection scope of the present invention is not limited to the above-mentioned embodiments, and all technical solutions under the idea of the present invention belong to the protection scope of the present invention. It should be pointed out that for those skilled in the art, some improvements and modifications without departing from the principles of the present invention should also be regarded as the protection scope of the present invention.

Claims (4)

1. A method for realizing instruction fusion, characterized in that the implementation steps include: 1) In the instruction fetch phase, the instruction is fetched; 2) In the decoding stage, it is judged whether there are prefix instructions and prefixed instructions that meet the fusion conditions appearing consecutively and being decoded at the same time. If so, the prefix instruction is fused to the prefixed instruction to form an instruction, and The instruction is marked as a fused instruction, and the source operand of the prefix instruction becomes a source operand of the fused instruction, replacing the implicit source operand; if not, the instruction is decoded normally; 3) Rename, dispatch and execute the instruction. If the instruction is a fused instruction, add a flag bit to the fused instruction, and pass the additional flag bit along the pipeline step by step; 4) In the submission stage, judge whether the fusion instruction with the additional flag bit is abnormal. If there is no abnormality in the fusion instruction, submit the fusion instruction and advance the submission address by two instructions. If the fusion instruction is abnormal, the fusion instruction cannot be submitted, and the prefix instruction The architectural state is not updated with the prefixed instruction, and the current submission address stays at the prefixed instruction, so an exception is reported at the prefixed instruction, and the exception return address is the address of the prefixed instruction; The detailed steps of step 2) include: 2.1) Determine whether the prefix instruction is included in the instruction decoded at the same time, if it is included, skip to step 2.2); otherwise, skip to step 2.6); 2.2) Determine whether the prefix instruction is the last valid instruction, if not, jump to step 2.3), otherwise jump to step 2.6); 2.3) Determine whether the next instruction of the prefix instruction satisfies the fusion condition and can be fused with the prefix instruction. If the fusion condition is met, then jump to step 2.4), otherwise jump to step 2.6); 2.4) Fuse the prefix instruction into the next instruction to form an instruction, mark the instruction as a fusion instruction, and then jump to step 2.5); 2.5) The source operand of the prefix instruction becomes a source operand of the fusion instruction, replacing the implicit source operand, and then jumps to step 3); 2.6) Perform normal decoding, and then jump to step 3). 2. The method for realizing instruction fusion according to claim 1, wherein the detailed steps of step 4) include: 4.1) According to the flag bit passed through the pipeline step by step, it is judged whether the instruction entering the submission stage is a fusion instruction. If it is a jump, execute step 4.2); otherwise, skip and execute step 4.5); 4.2) Judging whether an exception has occurred in the fusion instruction, if an exception occurs, jump to step 4.3), otherwise jump to step 4.4); 4.3) Report an exception at the prefix instruction, and the exception return address is the address of the prefix instruction; 4.4) Submit the fusion command, and submit the address to advance two commands; 4.5) Judging whether an exception has occurred in the non-fusion instruction, if so, jump to step 4.6), otherwise jump to step 4.7); 4.6) An exception is reported at the instruction, and the exception return address is the address of the instruction; 4.7) Submit the instruction, and the submission address advances by one instruction. 3. A device for implementing instruction fusion, characterized in that the device for implementing instruction fusion is programmed or configured to execute the steps of the method for implementing instruction fusion according to claim 1 or 2. 4. A microprocessor, characterized in that the microprocessor is programmed or configured to execute the steps of the method for implementing instruction fusion as claimed in claim 1 or 2.

Images