CN111404537B - Overvoltage input I/O buffer circuit for FPGA - Google Patents
Overvoltage input I/O buffer circuit for FPGA Download PDFInfo
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- CN111404537B CN111404537B CN202010148775.9A CN202010148775A CN111404537B CN 111404537 B CN111404537 B CN 111404537B CN 202010148775 A CN202010148775 A CN 202010148775A CN 111404537 B CN111404537 B CN 111404537B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
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Abstract
An overvoltage input I/O buffer circuit for an FPGA can close PN junctions from a source drain electrode of a final-stage driving P pipe to an N well when the difference between the high-level voltage of an input signal and the I/O power supply voltage of the FPGA is smaller than or larger than the threshold voltage of a P pipe, reduce leakage current caused by overvoltage input, and meanwhile pull up the grid electrode of the final-stage driving P pipe to a higher voltage of the high-level voltage of the input signal and the I/O power supply voltage of the FPGA, so that the leakage current of the final-stage driving P pipe is further ensured to be kept below a smaller nanoampere (nA) value, and circuit power consumption is reduced. A circuit (100) comprising: the input buffer (109), 6 PMOS tubes and 2 NMOS tubes, wherein the first, second, third, fifth, sixth and seventh MOS tubes (101, 102, 103, 105, 106, 107) are PMOS tubes, and the fourth and eighth MOS tubes (104, 108) are NMOS tubes.
Description
Technical Field
The invention relates to the technical Field of digital integrated circuits, in particular to an overvoltage input I/O buffer circuit for an FPGA (Field-Programmable Gate Array, field programmable gate array in a digital integrated circuit), which is mainly used for reducing leakage current caused by overvoltage input.
Background
An FPGA is a high-density complex general-purpose programmable logic device. FPGA based on SRAM (Static Random-Access Memory) programming configuration is widely used.
The user can program the device with the static random access memory SRAM through software to realize the required logic functions without having to design and foundry the ASIC chip. It consists of many independent programmable logic modules, programmable interconnects, and programmable input/output I/O modules. And the programmable resource is controlled by downloading the configuration code stream to a configuration storage unit in the chip, so that the required logic function is realized. The FPGA is the result of the fusion of VLSI technology and CAD technology development. The FPGA-based application circuit design does not need to go through a streaming chip, and meanwhile, the FPGA-based application circuit design has the support of EDA software with strong functions. Thus, the product development cycle is greatly shortened compared to ASIC-based chip designs. And when the required quantity is not large, the application circuit design based on the FPGA has the advantage of low cost compared with the ASIC chip design. These advantages of FPGA make it widely applicable in many fields of computer hardware, data processing, industrial control, remote control telemetry, smart meters, broadcast television, medical devices, and aerospace. The FPGA has more application scenes, can realize different interfaces by programming without leaving the programmable I/O function of the FPGA, and is connected and communicated with more chip interfaces with different functions. The programmable I/O of the FPGA is different from one of the common chips, namely, the FPGA can support multiple power supply voltages. Thus, there may be some input signal voltages from other chips that are slightly higher than the I/O supply voltage of the FPGA during use. Too high input signal voltage can cause the problem that leakage current is too large in the final drive tube of the FPGA I/O output buffer, so that excessive power consumption of chip I/O is caused.
U.S. patent No. 6369613B1, entitled INPUT/OUTPUT driver, discloses an INPUT/OUTPUT driver, in which a well bias circuit compares a high level voltage of an INPUT signal with a higher voltage of an FPGA I/O power supply voltage by two PMOS transistors connected in a cross-coupling manner with two PMOS transistors connected in a diode manner, so as to realize an N-well potential of a P-tube driven by a final stage of clamping, thereby reducing leakage current caused by overvoltage INPUT. When the phase difference between the high-level voltage of an input signal and the FPGA I/O power supply voltage is larger than the threshold voltage of a P tube, the PN junction from the source drain electrode of the P tube to the N well of the final-stage driving P tube can be closed when the N well potential of the P tube is clamped, so that the leakage current is zero. However, when the difference between the high-level voltage of the input signal and the FPGA I/O power supply voltage is smaller than the threshold voltage of a P tube, the PN junction from the source drain electrode of the final-stage driving P tube to the N well is not closed when the N well potential of the final-stage driving P tube is clamped, so that leakage current flows into the N well when the final-stage driving P tube is driven, and the circuit power consumption is increased.
Disclosure of Invention
In order to overcome the defects of the prior art, the technical problem to be solved by the invention is to provide an overvoltage input I/O buffer circuit for an FPGA, which can close a PN junction from a source drain electrode of a final-stage driving P pipe to an N well when the difference between the high-level voltage of an input signal and the I/O power supply voltage of the FPGA is smaller than or larger than a threshold voltage of the P pipe, reduce leakage current caused by overvoltage input, and simultaneously pull up the grid electrode of the final-stage driving P pipe to the higher voltage of the high-level voltage of the input signal and the I/O power supply voltage of the FPGA, so that the leakage current of the final-stage driving P pipe is further ensured to be maintained below a smaller nanoampere (nA) value, and the circuit power consumption is reduced.
The technical scheme of the invention is as follows: such an overvoltage input I/O buffer circuit (100) for an FPGA, comprising: the input buffer (109), 6 PMOS tubes and 2 NMOS tubes, wherein the first, second, third, fifth, sixth and seventh MOS tubes (101, 102, 103, 105, 106, 107) are PMOS tubes, and the fourth and eighth MOS tubes (104, 108) are NMOS tubes;
the first input end (Psig) is connected with the gate G end of the third MOS tube (103), the drain D end and the base B end of the second MOS tube (102), the gate G end of the first MOS tube (101) and the source S end of the third MOS tube (103) are connected with the power supply VDD, the source S end of the P second MOS tube (102) is connected with the drain D end of the first MOS tube (101), the source S end and the base B end of the first MOS tube (101) are connected with the output end (pad), the output end pad is connected with the drain D end of the third MOS tube (103), the drain D end of the fourth MOS tube (104), the input end of the input buffer (109), the drain D end of the sixth MOS tube (106), the source S end and the base B end of the seventh MOS tube (107), the drain S end and the base B end of the third MOS tube (103) are connected with the fifth MOS tube (105), the source S end and the base S end of the sixth MOS tube (106) are connected with the drain S end of the gate (108) of the fifth MOS tube (107), the drain S end of the gate G end of the fifth MOS tube (106) is connected with the drain S end of the gate (108) of the fifth MOS tube (107) and the drain S end of the eighth MOS tube (108) is connected with the drain end of the drain G end of the gate (108) of the fifth MOS tube (108), the second input end (Nsig) is connected to the gate G end of the fourth MOS transistor (104).
When the high-level voltage of an input signal transmitted from other chips through an input end pad is larger than the input/output power voltage VDD of the FPGA and is smaller than the threshold voltage of a PMOS tube, PN junctions from the source S end and the drain D end of the third MOS tube to the base B end can be closed, leakage current is zero, and at the moment, the first MOS tube and the second MOS tube are in an off state, so that the grid electrode of the third MOS tube is the high-level voltage VDD of the first input end Psig and the third MOS tube can be turned off; when the high-level voltage of the input signal of the input end pad is larger than the threshold voltage of a PMOS tube of the FPGA I/O power supply voltage VDD, the PN junction from the source S end and the drain D end of the third MOS tube to the base B end is closed, the leakage current is zero, the drain D of the seventh MOS tube and the drain D of the eighth MOS tube are pulled up to a certain voltage, the fifth MOS tube connected with the seventh MOS tube and the eighth MOS tube is turned off, and at the moment, the first MOS tube and the second MOS tube are in a conducting state, so that the grid electrode of the third MOS tube is the high-level voltage of the input signal of the input end pad and the third MOS tube can be turned off; therefore, when the difference between the high-level voltage of the input signal and the FPGA I/O power supply voltage is smaller than or larger than the threshold voltage of a P tube, PN junctions from the source drain electrode of the final-stage driving P tube to the N well can be closed, leakage current caused by overvoltage input is reduced, meanwhile, the grid electrode of the final-stage driving third MOS tube is pulled up to enable the third MOS tube to be in an off state, and the leakage current of the final-stage driving P tube is further ensured to be maintained below a smaller nanoampere (nA) value, so that circuit power consumption is reduced.
Drawings
FIG. 1 is a circuit diagram of an overvoltage input I/O buffer circuit for an FPGA according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
In order that the present disclosure may be more fully described and fully understood, the following description is provided by way of illustration of embodiments and specific examples of the present invention; this is not the only form of practicing or implementing the invention as embodied. The description covers the features of the embodiments and the method steps and sequences for constructing and operating the embodiments. However, other embodiments may be utilized to achieve the same or equivalent functions and sequences of steps.
As shown in fig. 1, such an overvoltage input I/O buffer circuit 100 for an FPGA includes: the input buffer 109, 6 PMOS transistors and 2 NMOS transistors, the first, second, third, fifth, sixth and seventh MOS transistors 101, 102, 103, 105, 106, 107 are PMOS transistors, and the fourth and eighth MOS transistors 104, 108 are NMOS transistors;
the first input terminal Psig is connected to the gate G end of the third MOS transistor 103, the drain D end and the base B end of the second MOS transistor 102, the gate G end of the first MOS transistor 101 and the source S end of the third MOS transistor 103 are all connected to the power supply VDD, the source S end of the second MOS transistor 102 is connected to the drain D end of the first MOS transistor 101, the source S end and the base B end of the first MOS transistor 101 are connected to the output terminal pad, the output terminal pad is connected to the drain D end of the third MOS transistor 103, the drain D end of the fourth MOS transistor 104, the input end of the input buffer 109, the drain D end of the sixth MOS transistor 106, the source S end and the base B end of the seventh MOS transistor 107, the drain D end and the base B end of the third MOS transistor 103 are connected to the drain D end of the fifth MOS transistor 105, the source S end of the sixth MOS transistor 106 and the base B end of the base B transistor 106 are connected to the drain G end of the fourth MOS transistor 104, the gate G end of the seventh MOS transistor 107 and the drain G end of the eighth MOS transistor 108 are connected to the drain D end of the fourth MOS transistor 104.
When the high-level voltage of an input signal transmitted from other chips through an input end pad is larger than the input/output power voltage VDD of the FPGA and is smaller than the threshold voltage of a PMOS tube, PN junctions from the source S end and the drain D end of the third MOS tube to the base B end can be closed, leakage current is zero, and at the moment, the first MOS tube and the second MOS tube are in an off state, so that the grid electrode of the third MOS tube is the high-level voltage VDD of the first input end Psig and the third MOS tube can be turned off; when the high-level voltage of the input signal of the input end pad is larger than the threshold voltage of a PMOS tube of the FPGA I/O power supply voltage VDD, the PN junction from the source S end and the drain D end of the third MOS tube to the base B end is closed, the leakage current is zero, the drain D of the seventh MOS tube and the drain D of the eighth MOS tube are pulled up to a certain voltage, the fifth MOS tube connected with the seventh MOS tube and the eighth MOS tube is turned off, and at the moment, the first MOS tube and the second MOS tube are in a conducting state, so that the grid electrode of the third MOS tube is the high-level voltage of the input signal of the input end pad and the third MOS tube can be turned off; therefore, when the difference between the high-level voltage of the input signal and the FPGA I/O power supply voltage is smaller than or larger than the threshold voltage of a P tube, PN junctions from the source drain electrode of the final-stage driving P tube to the N well can be closed, leakage current caused by overvoltage input is reduced, meanwhile, the grid electrode of the final-stage driving third MOS tube is pulled up to enable the third MOS tube to be in an off state, and the leakage current of the final-stage driving P tube is further ensured to be maintained below a smaller nanoampere (nA) value, so that circuit power consumption is reduced.
Preferably, the first input terminal Psig is pulled up to a high level voltage, and the second input terminal Nsig is pulled down to a low level voltage 0.
The specific working principle of the circuit is as follows:
the I/O buffer operates in an input mode, i.e. the output of the input buffer 109 varies with the voltage input of the output pad of the circuit, while the first input Psig is pulled up to a high voltage and the second input Nsig is pulled down to a low voltage 0. When the high-level voltage of the input signals transmitted from other chips through the output end pad is larger than the FPGA I/O power supply voltage VDD and is smaller than the threshold voltage of one PMOS tube, the first MOS tube 101, the second MOS tube 102, the third MOS tube 103, the sixth MOS tube 106, the seventh MOS tube 107 and the fourth MOS tube 104 are all in an off state; the eighth MOS transistor 108 is in an on state, so that the gate of the fifth MOS transistor 105 is in a low-level voltage 0 and is in an on state, therefore, the base B end of the third MOS transistor 103 (i.e., the N-well of the third MOS transistor 103) is an I/O power supply voltage, the PN junction from the source S end and the drain D end of the third MOS transistor to the base B end can be closed, the leakage current is zero, and at this time, the first MOS transistor 101 and the second MOS transistor 102 are both in an off state, so that the gate of the third MOS transistor 103 is a high-level voltage VDD of the first input end Psig, and the third MOS transistor 103 can be turned off. When the high-level voltage of the input signal of the output end pad is greater than the power supply voltage VDD of the FPGA I/O by one PMOS tube threshold voltage, the first MOS tube 101 and the second MOS tube 102 are in an open state, the first input end Psig is pulled up to the high-level voltage of the input signal of the output end pad, so that the voltage of the gate G end of the third MOS tube 103 is greater than the power supply voltage VDD of the source S end, and the third MOS tube 103 is turned off; the sixth MOS transistor 106 and the seventh MOS transistor 107 are also in an on state, the base B end of the third MOS transistor 103 is pulled up to the high level voltage of the input signal of the output end pad, and the PN junction from the source S end and the drain D end of the third MOS transistor 103 to the base B end can be closed, so that the leakage current is zero. The seventh MOS transistor 107 is turned on, and the drain D of the seventh MOS transistor 107 and the drain D of the eighth MOS transistor 108 are pulled up to a certain voltage, so that the fifth MOS transistor 105 is in an off state, and the fourth MOS transistor 104 is also in an off state.
The invention is not limited by the particular implementation of the circuit or by the logic form employed by the circuit, for example, all underlying circuitry may be standard CMOS processes or other processes.
The present invention is not limited to the preferred embodiments, but can be modified in any way according to the technical principles of the present invention, and all such modifications, equivalent variations and modifications are included in the scope of the present invention.
Claims (2)
1. An overvoltage input I/O buffer circuit (100) for an FPGA, characterized by: it comprises the following steps: the input buffer (109), 6 PMOS tubes and 2 NMOS tubes, wherein the first, second, third, fifth, sixth and seventh MOS tubes (101, 102, 103, 105, 106, 107) are PMOS tubes, and the fourth and eighth MOS tubes (104, 108) are NMOS tubes;
the first input end (Psig) is connected with the gate G end of the third MOS tube (103), the drain D end of the second MOS tube (102) and the substrate B end, the gate G end of the second MOS tube (102), the gate G end of the first MOS tube (101) and the source S end of the third MOS tube (103) are all connected with the power supply VDD, the source S end of the P second MOS tube (102) is connected with the drain D end of the first MOS tube (101), the source S end of the first MOS tube (101) and the substrate B are connected with the output end (pad), the output end pad is connected with the drain D end of the third MOS tube (103), the drain D end of the fourth MOS tube (104), the input end of the input buffer (109), the drain D end of the sixth MOS tube (106), the source S end of the seventh MOS tube (107) and the substrate B end, the drain D end of the fifth MOS tube (103) and the substrate B end of the seventh MOS tube (107), the drain S end of the fifth MOS tube (105) and the substrate B end of the fifth MOS tube (103) are connected with the gate G end of the fifth MOS tube (108), the drain S end of the fifth MOS tube (108) and the gate G end of the eighth MOS tube (108) are connected with the gate G end of the fifth MOS tube (108) and the substrate B end of the fifth MOS tube (108) are all connected with the drain end of the gate G end of the fifth MOS tube (108) and the drain end of the fifth MOS tube (108) and the gate (108) are connected with the substrate G end, the output end of the input buffer (109) is connected to the chip core, and the second input end (Nsig) is connected with the gate G end of the fourth MOS tube (104);
when the high level voltage of the input signal transmitted from other chips through the input end pad is larger than that of the FPGA
When the I/O power supply voltage VDD is less than the threshold voltage of one PMOS tube, PN junctions from the source S end and the drain D end of the third MOS tube to the base B end can be closed, and the leakage current is zero.
2. The overvoltage input I/O buffer circuit for an FPGA of claim 1, wherein: the first input terminal (Psig) is pulled up to a high level voltage and the second input terminal (Nsig) is pulled down to a low level voltage 0.
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| CN202010148775.9A CN111404537B (en) | 2020-03-05 | 2020-03-05 | Overvoltage input I/O buffer circuit for FPGA |
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| CN111404537B true CN111404537B (en) | 2023-09-26 |
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| CN118232904B (en) * | 2024-05-23 | 2024-11-19 | 中科亿海微电子科技（苏州）有限公司 | Input buffer for realizing high voltage resistance by using low voltage device and working method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4743957A (en) * | 1985-05-02 | 1988-05-10 | Nec Corporation | Logic integrated circuit device formed on compound semiconductor substrate |
| KR20000066203A (en) * | 1999-04-14 | 2000-11-15 | 정명식 | Current-mode bidirectional input/output buffer |
| US6369613B1 (en) * | 1999-05-10 | 2002-04-09 | Altera Corporation | Input/output drivers |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130265094A1 (en) * | 2012-04-05 | 2013-10-10 | Freescale Semiconductor, Inc | Level shifter circuit |
| CN103794188A (en) * | 2014-02-10 | 2014-05-14 | 北京京东方显示技术有限公司 | Output buffering circuit, array substrate and display device |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4743957A (en) * | 1985-05-02 | 1988-05-10 | Nec Corporation | Logic integrated circuit device formed on compound semiconductor substrate |
| KR20000066203A (en) * | 1999-04-14 | 2000-11-15 | 정명식 | Current-mode bidirectional input/output buffer |
| US6369613B1 (en) * | 1999-05-10 | 2002-04-09 | Altera Corporation | Input/output drivers |
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