CN111404513A - CIC decimation filter and implementation method thereof - Google Patents
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Abstract
A CIC extraction filter and its realization method, input the data signal to the first 2 times extractor and the first polyphase filter in turn to form the first path signal, input the data signal to a unit delay unit, the second 2 times extractor and the second polyphase filter in turn to form the second path signal, after summing the first path signal and the second path signal, obtain the data after 2 times extraction, input the data after 2 times extraction to L grade integrator to carry out integral operation, carry out R/2 times extraction to the data obtained by integral operation, obtain the data after R times extraction, input the data after R times extraction to L grade comb filter to carry out filtering process and output.
Description
Technical Field
The present invention relates to the technical field of multirate digital signal processing in software radio digital front ends, and in particular, to a CIC decimation filter and an implementation method thereof.
Background
The software radio defines a traditional radio frequency Front End as an Analog Front End (AFE) and a Digital Front End (DFE), which are connected through a Digital-to-Analog converter (ADC), the Analog Front End converts a signal received by an antenna into a signal which can be sampled after amplification, frequency conversion and filtering, and the Digital Front End is a Digital signal processing circuit located between the ADC and a baseband processor, and one of its main functions is sampling rate conversion, that is, converting a high-speed Digital signal output by the ADC into a low-speed Digital signal required by a baseband.
The CIC decimation filter has a simple structure in hardware implementation, does not need a multiplier, and has a good anti-aliasing characteristic, and is a preferred structure of the first stage decimation filter after the ADC, as shown in fig. 1, the CIC decimation filter with a simple structure is firstly adopted to decimate the output of the ADC, i.e. the high-rate digital signal with the sampling frequency of Fs to a lower rate of Fs/R, and then subsequent complex filtering is performed at the lower rate of Fs/R, thereby achieving the purpose of reducing power consumption and realizing difficulty.
The structure of a multi-stage CIC decimation filter commonly used in the prior art is shown in fig. 2, wherein L represents the stage number of the CIC filter, and R represents the decimation multiple of the decimator, input data with sampling frequency Fs is firstly integrated by L stages of integrators, then decimated by R times, reduced to low-rate data with sampling frequency Fs/R, and then differentially operated and output by L stages of comb filters, it can be seen that L stages of integrators before the decimator all work at the high frequency of Fs, and L stages of comb filters after the decimator all work at the lower frequency of Fs/R.
Disclosure of Invention
In view of the above, in order to solve the above problems, an object of the present invention is to provide a CIC decimation filter and a method for implementing the CIC decimation filter, which can reduce dynamic power consumption and difficulty in implementing an integrator.
The purpose of the invention is realized by the following technical scheme:
in a first aspect, the present invention provides a method for implementing a CIC decimation filter, which is implemented by the following steps:
step S1, sequentially inputting data signals to a first 2-time extractor and a first polyphase filter to form a first path of signals, simultaneously sequentially inputting the data signals to a unit delay unit, a second 2-time extractor and a second polyphase filter to form a second path of signals, and summing the first path of signals and the second path of signals to obtain 2-time extracted data;
step S2, inputting the 2-time extracted data into a L-level integrator for integral operation, and performing R/2-time extraction on the data obtained by integral operation to obtain R-time extracted data;
and step S3, inputting the R-time extracted data into a L-level comb filter for filtering and outputting.
Further, the transfer function H of the first polyphase filter and the second polyphase filter in the Z frequency domainPF1(Z) and HPF2(Z) satisfies the following formula:
wherein: h is2kAnd h2n+1Coefficients representing transfer functions of the first polyphase filter and the second polyphase filter in the Z-frequency domain, respectively;
l represents the order of CIC decimation filter integrators and comb filters.
Further, the coefficients of the transfer function of the first polyphase filter in the Z-frequency domain are equal to the polynomial (1+ Z)-1)LCoefficients of the expanded even terms; the coefficients of the transfer function of the second polyphase filter in the Z frequency domain are equal to the polynomial (1+ Z)-1)LCoefficients of even-numbered terms after expansion, wherein the polynomial (1+ Z)-1)LAfter expansion, the following formula is satisfied:
(1+Z-1)L＝1+h1Z-1+h2Z-2+...+hLZ-L＝∑kh2kZ-2k+Z-1∑nh2n+1Z-2n。
in a second aspect, the invention provides a CIC decimation filter, which comprises a delay unit, a first 2-time decimator, a second two-time decimator, a first polyphase filter, a second polyphase filter, a summing unit, an L-stage integrator, an R/2-time decimator and a L-stage comb filter, wherein the first 2-time decimator and the first polyphase filter are connected in series to form a first series circuit, the unit delay unit, the second 2-time decimator and the second polyphase filter are connected in series to form a second series circuit, the first series circuit and the second series circuit are input to the summing unit in parallel, and the output of the summing unit is sequentially connected to a L-stage integrator, the R/2-time decimator and the L-stage comb filter.
Furthermore, the unit delay unit, the first 2-time decimator and the second 2-time decimator work under the highest working frequency Fs, the first polyphase filter and the second polyphase filter work under the frequency of Fs/2, the L-level integrator and the R/2-time decimator work under the frequency of Fs/2, and the L-level comb filter works under the frequency of Fs/R.
The invention has the beneficial effects that:
on the premise of ensuring the function, the working frequency of the L-grade integrator is reduced by half, and only one unit delay unit and two 2-time extractors are needed to be realized under the highest frequency, so that the dynamic power consumption is effectively reduced, and the difficulty in realizing the L-grade integrator is greatly relieved.
Drawings
FIG. 1 is a schematic diagram of sample rate conversion using a multi-stage CIC decimation filter;
FIG. 2 is a schematic diagram of a conventional multi-stage CIC decimation filter in the prior art;
FIG. 3 is a schematic block diagram of an R-times decimation L stage CIC decimation filter;
FIG. 4 is an equivalent schematic block diagram of an R-times decimation L-stage CIC decimation filter;
FIG. 5 is a sectional cascade equivalent schematic block diagram of an R-time decimation L-stage CIC decimation filter;
FIG. 6 is an equivalent schematic block diagram of a CIC filter with 2-time decimation L stages;
FIG. 7 is an equivalent schematic block diagram of an optimized 2-time decimation L-stage CIC filter;
FIG. 8 is a flow chart illustrating a method for implementing a CIC decimation filter according to the present invention;
FIG. 9 is a block diagram of an implementation of a CIC decimation filter according to the present invention;
fig. 10 is a block diagram of an implementation of a 5-stage CIC decimation filter in an embodiment of the present invention.
Detailed Description
The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.
The embodiments of the present disclosure are described below with specific examples, and other advantages and effects of the present disclosure will be readily apparent to those skilled in the art from the disclosure in the specification. It is to be understood that the described embodiments are merely illustrative of some, and not restrictive, of the embodiments of the disclosure. The disclosure may be embodied or carried out in various other specific embodiments, and various modifications and changes may be made in the details within the description without departing from the spirit of the disclosure. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.
A conventional R-times decimating L-stage CIC filter structure is shown in fig. 2, and its transfer function in the Z frequency domain can be expressed by equation (1):
where M is the delay of the comb filter, R is the decimation rate, L is the order, the functional block diagram of the CIC decimation filter can be seen directly in fig. 3, in combination with the transfer function in equation (1) and the principles of the decimation filter.
According to the Nobel identity in multi-rate digital signal processing, the signal can be represented by Z-MThe factorized polynomial is shifted to the left of the R-fold decimator and converted to Z-RMIs a polynomial of the factor, so that an equivalent functional block diagram of the CIC decimation filter can be obtained, as shown in fig. 4.
Based on the principle, firstly, a simple transformation is performed on the formula (1), as shown in the formula (2):
by splitting the R-fold extractor into a 2-fold extractor and an R/2-fold extractor according to equation (2), the functional block diagram in fig. 4 can be transformed into fig. 5 based on the Nobel identity.
It can be seen that an R-times decimation L-stage CIC filter can be equivalent to a cascade of a 2-times decimation L-stage CIC filter (such as CIC1 labeled in fig. 5) and an R/2-times decimation L-stage CIC filter (such as CIC2 labeled in fig. 5), i.e., an R-times decimation L-stage CIC filter can be implemented in segments by a cascade of 2-times decimation L-stage CIC filters and an R/2-times decimation L-stage CIC filter.
According to equation (1), the transfer function of the 2-time decimation L-stage CIC filter (such as the CIC1 labeled in fig. 5) can be expressed as follows:
where i is 0, 1, 2 …, L, hi represents coefficients of each term after the spread of the transfer function, and equation (3) is classified into even terms and odd terms, which can be obtained:
HCIC1(Z)＝∑kh2kZ-2k+∑nh2n+1Z-(2n+1)＝∑kh2kZ-2k+Z-1∑nh2n+1Z-2nformula (4)
Wherein:
an equivalent schematic block diagram of a 2-decimation L-stage CIC filter according to fig. 4 and equation (4) can be shown in fig. 6.
According to the Nobel identity transform, Z is included in FIG. 6-2The polynomial of the factor can be shifted to the right of the 2-fold extractor, and the factor Z is correspondingly shifted-2Transformation to Z-1Then fig. 6 can be equivalently transformed into fig. 7, i.e. 2-time decimation L stage CIC filter can be optimized as shown in fig. 7.
According to the equivalent processing of an R-time decimation L-level CIC filter, the invention proposes an implementation method of a CIC decimation filter, as shown in fig. 8, in combination with a polyphase filtering method, the method includes the following steps:
step S1, sequentially inputting data signals to a first 2-time extractor and a first polyphase filter to form a first path of signals, simultaneously sequentially inputting the data signals to a unit delay unit, a second 2-time extractor and a second polyphase filter to form a second path of signals, and summing the first path of signals and the second path of signals to obtain 2-time extracted data;
further, the transfer function H of the first polyphase filter and the second polyphase filter in the Z frequency domainPF1(Z) and HPF2(Z) satisfies the following formula:
wherein: h is2kAnd h2n+1Coefficients representing transfer functions of the first polyphase filter and the second polyphase filter in the Z-frequency domain, respectively;
l represents the order of CIC decimation filter integrators and comb filters.
Further, the coefficients of the transfer function of the first polyphase filter in the Z frequency domain are equal to the polynomial (1+ Z)-1)LCoefficients of the expanded even terms; the coefficients of the transfer function of the second polyphase filter in the Z frequency domain are equal to the polynomial (1+ Z)-1)LCoefficients of even-numbered terms after expansion, wherein the polynomial (1+ Z)-1)LAfter expansion, the following formula is satisfied:
step S2, inputting the 2-time extracted data into a L-level integrator for integral operation, and performing R/2-time extraction on the data obtained by integral operation to obtain R-time extracted data;
and step S3, inputting the R-time extracted data into a L-level comb filter for filtering and outputting.
Corresponding to the implementation method of a CIC decimation filter of the present invention, the present invention further provides a CIC decimation filter implemented by the above method, whose functional block diagram is shown in fig. 9, and the CIC decimation filter includes a delay unit, a first 2-time decimator, a second two-time decimator, a first polyphase filter, a second polyphase filter, a summation unit, an L stage integrator, an R/2-time decimator and a L stage comb filter.
The first 2-time decimator and the first polyphase filter are connected in series to form a first series circuit, the unit delay unit, the second 2-time decimator and the second polyphase filter are connected in series to form a second series circuit, the first series circuit and the second series circuit are connected in parallel and input into the summing unit, and the output of the summing unit is sequentially connected to the L-stage integrator, the R/2-time decimator and the L-stage comb filter.
The unit delay unit, the first and the second 2-time decimators work under the highest working frequency Fs, the first and the second polyphase filters work under the frequency of Fs/2, the L-level integrator and the R/2-time decimator work under the frequency of Fs/2, and the L-level comb filter works under the lowest frequency of Fs/R.
As can be seen from FIG. 9, compared with the conventional R-time decimation L-level CIC filter mechanism, only one unit delay unit and two 2-time decimators operate at the highest frequency Fs, and both the two polyphase filters and the L-level integrator in the conventional structure operate at the lower frequency of Fs/2, so that not only is the dynamic power consumption effectively reduced, but also the difficulty in implementing the digital sequential logic circuit corresponding to the L-level integrator is greatly alleviated.
For further explanation, using Fs 500MHz, L &ttttranslation = L "&tttl &/t &ttt ═ 5 as an example, if the conventional structure in fig. 2 is adopted, the 5-stage integrator needs to operate at a high frequency of 500MHz, not only dynamic power consumption is high, but also implementation difficulty of a digital sequential logic circuit corresponding to the integrator is great since a sampling period is only 2ns, and a block diagram of the structure of the 5-stage CIC filter implemented by the present invention is shown in fig. 10-1+5Z-2Second polyphase filter 5+10Z-1+Z-2And the 5-stage integrator works at a lower frequency of 250MHz, so that the dynamic power consumption is effectively reduced, and the difficulty in realizing a digital sequential logic circuit corresponding to the integrator is greatly relieved as the sampling period is increased from 2ns to 4 ns.
The above description is for the purpose of illustrating embodiments of the invention and is not intended to limit the invention, and it will be apparent to those skilled in the art that any modification, equivalent replacement, or improvement made without departing from the spirit and principle of the invention shall fall within the protection scope of the invention.
Claims (5)
1. A method for realizing CIC decimation filter is characterized in that: the method is realized by the following steps:
step S1, sequentially inputting data signals to a first 2-time extractor and a first polyphase filter to form a first path of signals, simultaneously sequentially inputting the data signals to a unit delay unit, a second 2-time extractor and a second polyphase filter to form a second path of signals, and summing the first path of signals and the second path of signals to obtain 2-time extracted data;
step S2, inputting the 2-time extracted data into a L-level integrator for integral operation, and performing R/2-time extraction on the data obtained by integral operation to obtain R-time extracted data;
and step S3, inputting the R-time extracted data into a L-level comb filter for filtering and outputting.
2. The method of claim 1, wherein the CIC decimation filter comprises: the transfer function H of the first polyphase filter and the second polyphase filter in the Z frequency domainPF1(Z) and HPF2(Z) satisfies the following formula:
wherein: h is2kAnd h2n+1Coefficients representing transfer functions of the first polyphase filter and the second polyphase filter in the Z-frequency domain, respectively;
l represents the order of CIC decimation filter integrators and comb filters.
3. The method of claim 2, wherein the CIC decimation filter comprises: the coefficients of the transfer function of the first polyphase filter in the Z frequency domain are equal to the polynomial (1+ Z)-1)LCoefficients of the expanded even terms; the coefficients of the transfer function of the second polyphase filter in the Z frequency domain are equal to the polynomial (1+ Z)-1)LCoefficients of even-numbered terms after expansion, wherein the polynomial (1+ Z)-1)LAfter expansion, the following formula is satisfied:
(1+Z-1)L＝1+h1Z-1+h2Z-2+…+hLZ-L＝∑kh2kZ-2k+Z-1∑nh2n+1Z-2n。
4. a CIC decimation filter is characterized by comprising a delay unit, a first 2-time decimator, a second two-time decimator, a first polyphase filter, a second polyphase filter, a summing unit, an L-stage integrator, an R/2-time decimator and a L-stage comb filter, wherein the first 2-time decimator and the first polyphase filter are connected in series to form a first series circuit, the unit delay unit, the second 2-time decimator and the second polyphase filter are connected in series to form a second series circuit, the first series circuit and the second series circuit are connected in parallel to be input into the summing unit, and the output of the summing unit is sequentially connected to a L-stage integrator, the R/2-time decimator and a L-stage comb filter.
5. The CIC decimation filter according to claim 4, wherein said unit delay unit and said first and second 2 decimators operate at a maximum operating frequency of Fs, said first and second polyphase filters operate at a frequency of Fs/2, said L-stage integrator and said R/2 decimator operate at a frequency of Fs/2, and said L-stage comb filter operates at a frequency of Fs/R.
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