CN111403336A - Array substrate, display panel and manufacturing method of array substrate - Google Patents

Abstract

The invention provides an array substrate, a display panel and a manufacturing method of the array substrate, wherein the manufacturing method of the array substrate comprises the following steps: depositing a grid metal layer on the substrate base plate, and carrying out a first photoetching process to form a grid and a grid line on the substrate base plate; sequentially depositing a gate insulating layer, a metal oxide semiconductor layer, a barrier layer and a source drain metal layer containing a Cu element on a substrate base plate on which a gate and a gate line are formed, and forming an anti-oxidation layer containing a CuNx layer on the source drain metal layer containing the Cu element; and carrying out a second photoetching process to enable the metal oxide semiconductor layer to form a metal oxide semiconductor pattern, enable the blocking layer to form an anti-diffusion pattern positioned between the metal oxide semiconductor pattern and the source electrode and the drain electrode, enable the source electrode and the drain electrode metal layer containing the Cu element to form the source electrode and the drain electrode, and enable the anti-oxidation layer to form the anti-oxidation pattern. The invention prevents Cu in the source electrode and the drain electrode from being oxidized by the film layer containing SiOx, and improves the reliability of the array substrate.

Description

Array substrate, display panel and manufacturing method of array substrate

technical field

The present invention relates to the field of display technology, and in particular, to an array substrate, a display panel and a manufacturing method of the array substrate.

Background technique

With the development of display technology, display panels are widely used in various consumer electronic products such as mobile phones, televisions, personal digital assistants, and notebook computers, and become the mainstream of display devices. In order to achieve high-resolution display, as the main driving element in the display panel, the size of Thin Film Transistor (TFT) device needs to be "miniaturized", and the realization of Back Channel Etching (BCE for short) ) structure is the key to "miniaturization" of TFT device size.

In the existing manufacturing process of the array substrate using back channel etching, the source and drain metal layers are deposited on the metal oxide semiconductor pattern and the gate insulating layer, and the source and drain metal layers are patterned by one etching process. After the chemical etching, the source electrode, the drain electrode and the channel between the source electrode and the drain electrode are obtained; and a passivation layer is deposited on the gate insulating layer formed with the metal oxide semiconductor pattern, the source electrode and the drain electrode . Among them, SiNx can be generally used for the passivation layer, but considering that metal oxide TFTs are sensitive to nitrogen elements, and sometimes even cause the metal oxide TFTs to lose their characteristics, silicon oxides can be selected as passivation layers.

However, when silicon oxide is used as the passivation layer, the Cu element on the surface of the source electrode and the drain electrode is easily oxidized, and the source electrode and the drain electrode are easily peeled off, resulting in poor reliability of the array substrate.

SUMMARY OF THE INVENTION

The invention provides an array substrate, a display panel and a manufacturing method of the array substrate, which can prevent the Cu element on the surface of the source electrode and the drain electrode from being oxidized, and prevent the source electrode and the drain electrode from peeling off, thereby improving the reliability of the array substrate.

A first aspect of the present invention provides a method for fabricating an array substrate, comprising: depositing a gate metal layer on a base substrate, and performing a first photolithography process to form gate electrodes and gate lines on the base substrate; A gate insulating layer, a metal oxide semiconductor layer, a barrier layer, and a source-drain metal layer containing Cu elements are sequentially deposited on the base substrate on which the gate and gate lines are formed, and the source-drain metal layer containing Cu elements is deposited on the An anti-oxidation layer including a CuNx layer is formed thereon; a second photolithography process is performed on the metal oxide semiconductor layer, the barrier layer, the source-drain metal layer containing Cu elements, and the anti-oxidation layer, so that the metal oxide semiconductor layer forms a metal oxide layer. The material semiconductor pattern, the barrier layer forms an anti-diffusion pattern between the metal oxide semiconductor pattern and the source and drain electrodes, the source and drain metal layers containing Cu elements form the source and drain electrodes, and the anti-oxidation layer forms an anti-oxidation pattern graphics.

A second aspect of the present invention provides an array substrate, comprising: a base substrate and a gate electrode, a gate insulating layer, a metal oxide semiconductor pattern, a blocking pattern, a source electrode and a drain electrode containing Cu elements sequentially arranged on the base substrate electrode, anti-oxidation pattern and passivation layer, the anti-oxidation pattern includes CuNx pattern, and the CuNx pattern is located on the surface of the source and drain containing Cu elements close to the passivation layer; wherein, the gate insulating layer covers the gate, the blocking pattern, containing The source electrode and drain electrode of Cu element and the anti-oxidation pattern are all arranged above the metal oxide semiconductor pattern, and the blocking pattern coincides with the projection of the source electrode and drain electrode containing Cu element and the anti-oxidation pattern on the substrate. And there is a channel region between the source and the drain.

In one possible implementation, the thickness of the CuNx pattern is smaller than the thickness of the barrier pattern.

In a possible implementation, the anti-oxidation pattern includes a protective pattern located between the CuNx pattern and the passivation layer, the protective pattern is used to prevent the oxidation of Cu elements contained in the source and drain oxidation, the protective pattern and the blocking pattern The projections on the base substrate coincide.

In a possible implementation manner, the material of the protection pattern includes at least one of Cr, W, Ti, Ta, and Mo.

In a possible implementation manner, the gate electrode includes Cu element, the base substrate includes a glass substrate and an adhesion layer deposited on the glass substrate, and the adhesion layer is close to the gate electrode and is used to increase the adhesion between the gate electrode and the base substrate.

In a possible implementation manner, the metal oxide semiconductor pattern includes a first semiconductor pattern and a second semiconductor pattern overlapping each other, and the conductivity of the first semiconductor pattern is higher than that of the second semiconductor pattern.

In a possible implementation manner, the oxygen content of the second semiconductor pattern is lower than that of the first semiconductor pattern.

In a possible implementation manner, the metal-oxide-semiconductor pattern located within the channel region is composed of the first semiconductor pattern.

In a possible implementation manner, the part of the passivation layer in contact with the channel region is silicon oxide.

A second aspect of the present invention provides a display panel including the above-mentioned array substrate.

This embodiment provides an array substrate, a display panel, and a method for fabricating the array substrate. The fabricating method for the array substrate includes: depositing a gate metal layer on a base substrate, and performing a first photolithography process, so as to form a first photolithography process on the base substrate. A gate and gate lines are formed thereon; a gate insulating layer, a metal oxide semiconductor layer, a barrier layer, and a source-drain metal layer containing Cu elements are sequentially deposited on the base substrate on which the gate and gate lines are formed, and An anti-oxidation layer containing a CuNx layer is formed on the source-drain metal layer containing Cu element; a second photolithography process is performed on the metal oxide semiconductor layer, the barrier layer, the source-drain metal layer containing Cu element, and the anti-oxidation layer, The metal oxide semiconductor layer is formed into a metal oxide semiconductor pattern, the barrier layer is formed into an anti-diffusion pattern between the metal oxide semiconductor pattern and the source and drain electrodes, and the source and drain metal layers containing Cu elements are formed into the source and drain electrodes pole, so that the anti-oxidation layer forms an anti-oxidation pattern. An anti-oxidation layer including a CuNx layer is formed on the surface of the source and drain metal layers containing Cu elements, so CuNx patterns are formed on the surfaces of the source and drain electrodes formed by etching. When the passivation layer of SiOx is used, CuNx can protect the source electrode and the drain electrode and prevent the source electrode and the drain electrode from being oxidized by the passivation layer containing SiOx. Therefore, peeling of the source electrode and the drain electrode can be prevented, and the reliability of the array substrate can be improved.

Description of drawings

In order to illustrate the technical solutions of the present invention or the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are of the present invention. For some embodiments of the present invention, for those of ordinary skill in the art, other drawings can also be obtained according to these drawings without any creative effort.

FIG. 1 is a schematic flowchart of a method for fabricating an array substrate according to Embodiment 1 of the present invention;

FIG. 2 is a schematic structural diagram of the array substrate in the first state in the manufacturing method of the array substrate provided in the first embodiment of the present invention;

FIG. 3 is another schematic structural diagram of the array substrate in the first state in the manufacturing method of the array substrate provided in the first embodiment of the present invention;

FIG. 4 is a schematic structural diagram of the array substrate in the second state in the manufacturing method of the array substrate provided in the first embodiment of the present invention;

FIG. 5 is another schematic structural diagram of the array substrate in the second state in the manufacturing method of the array substrate provided in the first embodiment of the present invention;

FIG. 6 is a schematic structural diagram of the array substrate in the third state in the manufacturing method of the array substrate provided in the first embodiment of the present invention;

FIG. 7 is another schematic structural diagram of the array substrate in the third state in the manufacturing method of the array substrate provided in the first embodiment of the present invention;

8 is a schematic structural diagram of the array substrate when the array substrate is in a fourth state in the manufacturing method of the array substrate provided in the first embodiment of the present invention;

FIG. 9 is a schematic structural diagram of the array substrate in the fifth state in the manufacturing method of the array substrate provided in the first embodiment of the present invention;

10 is a schematic structural diagram of the array substrate when the array substrate is in a sixth state in the method for fabricating the array substrate provided in the first embodiment of the present invention;

11 is a schematic structural diagram of the array substrate in the seventh state in the method for fabricating the array substrate provided in the first embodiment of the present invention;

12 is a schematic structural diagram of the array substrate in the eighth state in the manufacturing method of the array substrate provided in the first embodiment of the present invention;

13 is a schematic structural diagram of the final state of the array substrate in the method for fabricating the array substrate provided in Embodiment 1 of the present invention;

Fig. 14 is the top view of Fig. 13;

FIG. 15 is a schematic structural diagram of an array substrate according to Embodiment 2 of the present invention.

Reference number:

100-array substrate; 1-base substrate; 11-glass substrate; 12-attachment layer pattern; 2-gate; 3-gate insulating layer; 4-anti-oxidation layer; 41-anti-oxidation pattern; 43-channel region; 5-metal oxide semiconductor pattern; 5'-metal oxide semiconductor layer; 51-first semiconductor layer; 52-second semiconductor layer; 51'-first semiconductor pattern; 52'-second semiconductor pattern; 6 -blocking layer; 6'-blocking pattern; 7-source; 8-drain; 8'-source-drain metal layer containing Cu element; 80-CuNx layer; 80'-CuNx pattern; 81-protective layer; 81' -protection pattern; 82-scan line; 83-data line; 85-conductive via hole; 87-pixel electrode; 9-passivation layer; 90-first photoresist pattern; 91-photoresist completely reserved area; 92 - photoresist partially retained area; 93 - photoresist complete removal area; 94 - second photoresist pattern.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention. , not all examples. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

Example 1

FIG. 1 is a schematic flowchart of a method for fabricating an array substrate according to Embodiment 1 of the present invention. As shown in FIG. 1 , the method for fabricating an array substrate in this embodiment includes:

S10, depositing a gate metal layer on the base substrate, and performing a first photolithography process to form gate electrodes and gate lines on the base substrate;

的栅极金属层，并对栅极金属层进行第一次光刻工艺，以在阵列基板的开关区域形成栅极2和栅极线。FIG. 2 is a schematic structural diagram of the array substrate in the first state in the manufacturing method of the array substrate provided in the first embodiment of the present invention. As shown in FIG. 2 , first, the substrate substrate 1 is deposited sequentially by sputtering or thermal evaporation. The upper thickness is approx.

The gate metal layer is formed, and the first photolithography process is performed on the gate metal layer to form gate 2 and gate lines in the switching region of the array substrate.

In addition, it should be understood that, in practice, for the array substrate 100 used in the liquid crystal display panel, the array substrate 100 will include a plurality of sub-pixel regions defined by the scan lines 82 and the data lines 83 , and each sub-pixel region has a At least one thin film transistor device is provided. For the convenience of description, in the drawings of the present application, only a schematic diagram of the fabrication of one of the sub-pixel regions is drawn. It can be understood that the array substrate 100 in the present application includes a plurality of sub-pixel regions. Therefore, in the manufacturing process of the array substrate 100 of the present application, the formation of the gate electrode 2 and the gate line on the base substrate 1 specifically refers to the formation of the gate electrode 2 and the gate line in the area of the array substrate 100 corresponding to each sub-pixel area. The gate 2 and gate lines are formed. The same is true for the source electrode 7 , the drain electrode 8 , and the metal oxide semiconductor pattern 5 , and details are not repeated here.

For the above-mentioned gate metal layer, in the case of containing Cu element, it is easy to have poor adhesion between the gate electrode 2 and the base substrate 1. In order to avoid this situation, an adhesion can be provided under the gate metal layer layer, FIG. 3 is another schematic structural diagram of the array substrate in the first state in the manufacturing method of the array substrate provided in the first embodiment of the present invention.

的附着层以及厚度约为

的栅极金属层，并对附着层和栅极金属层进行第一次光刻工艺，以在阵列基板的开关区域形成栅极2和与栅极2重叠的附着层图形12。As shown in FIG. 3 , first, on the glass substrate 11 or quartz, the method of sputtering or thermal evaporation is used to sequentially deposit a thickness of about

The adhesion layer and thickness of approx.

The gate metal layer is formed, and the first photolithography process is performed on the adhesion layer and the gate metal layer to form a gate 2 and an adhesion layer pattern 12 overlapping with the gate 2 in the switching region of the array substrate.

It can be understood that the adhesion layer is on the side of the glass substrate close to the gate metal layer, for increasing the adhesion between the gate metal layer and the base substrate, and preventing the gate 2 from peeling off. The material of the adhesion layer may include at least one of Cr, W, Ti, Ta, and Mo, for example, the adhesion layer may be Mo alloy, Ti alloy, or the like.

Next, the gate insulating layer 3 is deposited on the array substrate in the first state. In the following introduction, the array substrate with the adhesion layer shown in FIG. 3 is used as an example to describe the subsequent steps. It can be understood that it is also possible to Subsequent processes are performed on the basis of the array substrate shown in FIG. 2 . Since the process is similar to that performed on the basis of FIG. 2 , details are not repeated here.

Specifically, the fabrication process of the array substrate further includes:

S20, sequentially depositing a gate insulating layer, a metal oxide semiconductor layer, a barrier layer, and a source-drain metal layer containing Cu element on the base substrate on which the gate electrode and the gate line are formed; and on the source-drain layer containing Cu element An anti-oxidation layer including a CuNx layer is formed on the metal layer. Preferably, the source/drain metal layer including Cu element may be subjected to plasma treatment to form a CuNx layer on the surface of the source/drain metal layer including Cu element.

的栅极绝缘层3，栅极绝缘层3可以选用氧化物、氮化物或者氧氮化合物，对应的反应气体可以为SiH₄、NH₃、N₂或SiH₂Cl₂、NH₃、N₂。4 is a schematic structural diagram of the array substrate in the second state in the manufacturing method of the array substrate provided in the first embodiment of the present invention. As shown in FIG. 4 , specifically, firstly, on the array substrate in the first state shown in FIG. 3 The thickness is continuously deposited by the plasma-enhanced chemical vapor deposition method of

The gate insulating layer 3 can be selected from oxides, nitrides or oxygen-nitrogen compounds, and the corresponding reactive gases can be SiH ₄ , NH ₃ , N ₂ or SiH ₂ Cl ₂ , NH ₃ , and N ₂ .

的金属氧化物半导体层5'，金属氧化物半导体层5'可以采用非晶IGZO、HIZO、IZO、a-InZnO、a-InZnO、ZnO:F、In₂O₃:Sn、In₂O₃:Mo、Cd₂SnO₄、ZnO:Al、TiO₂:Nb、Cd-Sn-O或其他金属氧化物制成。In addition, the gate insulating layer 3 is deposited by sputtering or thermal evaporation with a thickness of about

The metal oxide semiconductor layer 5', the metal oxide semiconductor layer 5' can use amorphous IGZO, HIZO, IZO, a-InZnO, a-InZnO, ZnO:F, In ₂ O ₃ :Sn, In ₂ O ₃ : Mo, Cd ₂ SnO ₄ , ZnO:Al, TiO ₂ :Nb, Cd-Sn-O or other metal oxides.

FIG. 5 is another schematic structural diagram of the array substrate in the second state in the manufacturing method of the array substrate provided in the first embodiment of the present invention. As shown in FIG. 5 , as a possible implementation manner, the metal oxide semiconductor layer 5 'Including but not limited to the above-mentioned one layer, and may also include two layers, for example, the metal oxide semiconductor layer 5' may include a first semiconductor layer 51 and a second semiconductor layer 52, and the conductivity of the first semiconductor layer 51 is higher than that of the first semiconductor layer 51. The conductivity of the second semiconductor layer 52 . The step of depositing the metal oxide semiconductor layer 5' may further include:

的第一半导体层51以及厚度为

的第二半导体层52。On the gate insulating layer 3, the thickness is continuously deposited by the sputtering method of

The first semiconductor layer 51 and the thickness are

the second semiconductor layer 52 .

Among them, the conductivity of each semiconductor layer can be effectively controlled by controlling the content of oxygen during deposition. The content of oxygen in the deposited semiconductor layer is high, and the conductivity of the formed semiconductor layer is good, close to the conductor; oxygen in the deposited semiconductor layer The content of the semiconductor layer is low, the conductivity of the formed semiconductor layer is poor, and it is a semiconductor. That is, the oxygen content of the second semiconductor layer 52 is lower than the oxygen content of the first semiconductor layer 51 .

In the embodiment of the present application, the conductivity of the first semiconductor layer 51 is higher than that of the second semiconductor layer 52, so that the first semiconductor layer 51 with higher conductivity is directly in contact with the gate insulating layer 3, so that the channel of the thin film transistor is The channels are formed in the first semiconductor layer 51 and the second semiconductor layer 52 to make the performance of the thin film transistor more stable. The second semiconductor layer 52 with lower conductivity is in direct contact with the source-drain metal layer, which can reduce the contact resistance between the metal-oxide-semiconductor layer 5' and the source-drain metal layer and increase the on-state current of the metal oxide thin film transistor.

Next, the barrier layer 6 is deposited on the array substrate in the second state. In the following introduction, the array substrate with two layers of semiconductor layers shown in FIG. 5 is used as an example to describe the subsequent process. Subsequent processes are performed on the basis of the array substrate shown in FIG. 4 , and since the process is similar to that performed on the basis of FIG. 5 , it will not be repeated here.

的阻挡层6，阻挡层6的材料可以包括Cr、W、Ti、Ta、Mo中的至少一者，例如阻挡层6可以为Mo合金、以及Ti合金等。阻挡层6可以阻止Cu元素扩散到金属氧化物半导体中，同时又可以增加源极7和漏极8中Cu元素与金属氧化物半导体层5'的附着力。FIG. 6 is a schematic structural diagram of the array substrate in the third state in the manufacturing method of the array substrate provided in the first embodiment of the present invention. As shown in FIG. 6, after the metal oxide semiconductor layer 5' is formed, the metal oxide semiconductor layer 5' is formed. Layer 5' is continuously deposited by sputtering or thermal evaporation to a thickness of approximately

The barrier layer 6, the material of the barrier layer 6 may include at least one of Cr, W, Ti, Ta, Mo, for example, the barrier layer 6 may be a Mo alloy, a Ti alloy, and the like. The barrier layer 6 can prevent the Cu element from diffusing into the metal oxide semiconductor, and at the same time can increase the adhesion of the Cu element in the source electrode 7 and the drain electrode 8 to the metal oxide semiconductor layer 5 ′.

的Cu金属作为含有Cu元素的源漏金属层8'，然后在有Cu元素的源漏金属层8'上形成防氧化层，例如可以对含有Cu元素的源漏金属层8'的表面进行等离子气体表面处理，使源漏金属层8'的靠近钝化层9的表面部分转化为CuNx层80。As shown in FIG. 6, after the barrier layer 6 is formed, it can be continuously deposited by sputtering or thermal evaporation to a thickness of about

The Cu metal is used as the source-drain metal layer 8' containing Cu element, and then an anti-oxidation layer is formed on the source-drain metal layer 8' containing Cu element, for example, the surface of the source-drain metal layer 8' containing Cu element can be plasma The gas surface treatment converts the surface portion of the source-drain metal layer 8 ′ close to the passivation layer 9 into the CuNx layer 80 .

Optionally, the above-mentioned surface treatment can be performed in dry etching equipment, for example, in dry etching equipment such as reactive ion etching, enhanced capacitively coupled plasma etching, and inductively coupled plasma etching, or in dry etching equipment. It is carried out in the equipment of bulk enhanced chemical vapor deposition, and the selection of process parameters is different in the surface treatment carried out in different equipment.

For example, the plasma gas for surface treatment can be N ₂ plasma, NH ₃ , or H ₂ , and different gases are used to treat the surface, resulting in different substances.

_N2 plasma treatment is performed in a dry etching equipment to generate CuNx, the corresponding radio frequency power is 15kW~35kW, the gas pressure is 100mT~1500mT, and the gas flow rate is 600~2500sccm; in a plasma-enhanced chemical vapor deposition equipment The N ₂ plasma treatment generates CuNx, the corresponding radio frequency power is 7kW-20kW, the gas pressure is 800mT-1500mT, and the gas flow rate is 8000-40000sccm.

In the above method, the CuNx layer 80 is formed on the surface of the source-drain metal layer 8 ′ containing Cu element. When the passivation layer 9 containing SiOx is deposited on the surface of the source electrode 7 and the drain electrode 8 in the subsequent process, CuNx can affect the source electrode. 7 and the drain 8 play a protective role to prevent Cu element in the source 7 and the drain 8 from being oxidized by the passivation layer 9 containing SiOx, so the reliability of the array substrate 100 can be improved.

例如，可以为

阻挡层6较厚，主要是防止Cu扩散，例如可以为

Further, in order to form a better pattern of the source electrode 7 and the drain electrode 8 during etching, the thickness of the barrier layer 6 may be larger than that of the CuNx layer 80 , that is, the thickness of the CuNx layer 80 may be thinner. The thickness of the protective layer 81 is

For example, it can be

The barrier layer 6 is thicker, mainly to prevent the diffusion of Cu, for example, it can be

FIG. 7 is another schematic structural diagram of the array substrate in the third state in the manufacturing method of the array substrate provided in the first embodiment of the present invention. As shown in FIG. 7 , as an optional implementation manner, the anti-oxidation layer may also be Including a protective layer 81 on the CuNx layer 80, the manufacturing method is that before the second photolithography process, further includes the step of depositing the protective layer 81 on the CuNx layer 80, and by forming the protective layer 81 on the CuNx layer 80, The oxidation resistance of the source electrode 7 and the drain electrode 8 can be further enhanced.

Optionally, the protective layer 81 is continuously deposited by sputtering or thermal evaporation, and the material of the protective layer 81 may include at least one of Cr, W, Ti, Ta, and Mo, for example, the protective layer 81 may be Mo alloy, Ti alloy, etc. . After being oxidized, at least one of Cr, W, Ti, Ta, and Mo can form a dense oxide film, which covers the surfaces of the source electrode 7 and the drain electrode 8 to prevent the Cu in the source electrode 7 and the drain electrode 8 from being oxidized.

的保护层81，可以有效阻止在沉积包含SiOx的钝化层9时，源极7和漏极8以及数据线83中的Cu元素发生氧化。Specifically, as shown in FIG. 7 , after the process of forming the CuNx layer 80 , the CuNx layer 80 is continuously deposited by sputtering or thermal evaporation to a thickness of about

The protective layer 81 can effectively prevent the Cu element in the source electrode 7 and the drain electrode 8 and the data line 83 from being oxidized when the passivation layer 9 containing SiOx is deposited.

The second photolithography is performed on the array substrate in the third state. The following process is described by taking the array substrate with the protective layer 81 formed in FIG. 7 as an example. The subsequent process is performed on the basis of the array substrate shown in FIG. 7 , since the process is similar to the subsequent process performed on the basis of FIG. 7 , and will not be repeated here.

Specifically, the fabrication process of the array substrate 100 further includes:

S30, performing a second photolithography process on the metal oxide semiconductor layer, the barrier layer, the source-drain metal layer containing Cu element, and the anti-oxidation layer, so that the metal oxide semiconductor layer is formed into a metal oxide semiconductor pattern, and the barrier layer is formed The anti-diffusion pattern located between the metal oxide semiconductor pattern and the source electrode and the drain electrode makes the source and drain metal layers containing Cu elements form the source electrode and the drain electrode, and the anti-oxidation layer forms an anti-oxidation pattern.

In the above method, the CuNx layer 80 as an anti-oxidation layer is formed on the surface of the source-drain metal layer 8' containing Cu element, so the CuNx pattern 80' is formed on the surface of the source electrode 7 and the drain electrode 8 formed by etching. When the passivation layer 9 containing SiOx is deposited on the surface of the source electrode 7 and the drain electrode 8 during the manufacturing process, CuNx can protect the source electrode 7 and the drain electrode 8 and prevent the source electrode 7 and the drain electrode 8 from being affected by the passivation layer containing SiOx. The chemical layer 9 is oxidized. Therefore, peeling of the source electrode 7 and the drain electrode 8 can be prevented, and the reliability of the array substrate 100 can be improved. Wherein, the second photolithography process may include a gray-tone mask process or a half-tone mask process. In this way, the metal oxide semiconductor pattern 5 , the source electrode 7 and the drain electrode 8 can be simultaneously formed through a single photolithography process. Therefore, compared with the conventional photolithography process in the prior art, one photolithography process is saved and the production efficiency is improved.

Specifically, FIG. 8 is a schematic structural diagram of the array substrate in the fourth state in the manufacturing method of the array substrate provided in the first embodiment of the present invention, and FIG. 9 is the array substrate in the fourth state in the manufacturing method of the array substrate provided in the first embodiment of the present invention. Schematic diagram of the structure in five states, FIG. 10 is a schematic diagram of the structure of the array substrate in the sixth state in the manufacturing method of the array substrate provided by Embodiment 1 of the present invention, and FIG. 11 is the manufacturing method of the array substrate provided by Embodiment 1 of the present invention. A schematic diagram of the structure of the array substrate when the array substrate is in the seventh state, FIG. 12 is a schematic diagram of the structure of the array substrate when the array substrate is in the eighth state in the manufacturing method of the array substrate provided by the first embodiment of the present invention, and FIG. 13 is the array substrate provided by the first embodiment of the present invention. A schematic structural diagram of the final state of the array substrate in the manufacturing method of FIG. 14 is a top view of FIG. 13 .

In the array substrate in the third state shown in FIG. 7, a photoresist is coated on the protective layer 81, and a first photoresist pattern 90 is formed after exposure and development, that is, the fourth state shown in FIG. 8 is formed. The array substrate, wherein the first photoresist pattern 90 includes a photoresist complete retention area 91 , a photoresist partial retention area 92 and a photoresist complete removal area 93 .

Among them, the photoresist completely reserved area 91 corresponds to the area of the source electrode 7, the drain electrode 8 and the data line 83; the photoresist partially reserved area 92 corresponds to the channel area between the source electrode 7 and the drain electrode 8, that is Corresponds to the channel region of the thin film transistor on the array substrate; the photoresist completely removed region 93 corresponds to the region on the photoresist except the photoresist completely reserved region 91 and the photoresist partially reserved region 92 .

For the array substrate in the fourth state as shown in FIG. 8 , using the first photoresist pattern 90 as a mask, the protective layer 81 , the source-drain metal layer 8 ′ formed with the CuNx layer 80 , the barrier layer 6 , and the metal In the oxide semiconductor layer 5 ′ (including the second semiconductor layer 52 and the first semiconductor layer 51 ), the part located in the photoresist completely removed region 93 is etched for the first time to form an array in the fifth state shown in FIG. 9 substrate.

For the array substrate in the fifth state shown in FIG. 9 , the above-mentioned first photoresist pattern 90 is ashed to remove the photoresist in the photoresist partially reserved area 92 and thin the photoresist in the photoresist completely reserved area 91 and form the array substrate in the sixth state shown in FIG. 10 , and then use the second photoresist pattern 94 after ashing the first photoresist pattern 90 as a mask to retain the part of the photoresist removed by ashing The portion corresponding to the region 92 is etched, that is, the protective layer 81, the CuNx layer 80, the source-drain metal layer, and the barrier layer 6 are etched away, and the portion corresponding to the region 92 is retained in the photoresist removed by ashing, thereby The channel region 43 of the TFT is formed. Then, the remaining photoresist is peeled off to form the array substrate in the seventh state shown in FIG. 11 .

In addition, a dry etching process can be used when forming the TFT channel region. This is because the dry etching process has a relatively high selection and can reduce the impact on the metal oxide semiconductor layer 5 ′ under the source electrode 7 and the drain electrode 8 . corrosion.

It can be understood that since the protective layer 81, the source-drain metal layer formed with the CuNx layer 80 and the barrier layer 6 are etched with the same mask, the formed protective pattern 81', CuNx pattern 80', source electrode 7. The projections of the drain 8 and the blocking pattern 6' on the base substrate coincide with each other.

In addition, after the second photolithography process in the above step S30, it may further include:

A passivation layer 9 is deposited on the gate insulating layer 3 on which the source electrode 7 , the drain electrode 8 and the metal oxide semiconductor pattern 5 are formed, and a third photolithography process is performed to locate the drain electrode 8 on the passivation layer 9 The upper area forms conductive vias 85;

A transparent conductive layer is deposited on the passivation layer 9 , and a fourth photolithography process is performed, so that the transparent conductive layer forms the pixel electrode 87 , and the pixel electrode 87 and the drain electrode 8 communicate with each other through the conductive via 85 .

的钝化层9，钝化层9可以选用氧化物、氮化物或者氧氮化合物，可以是单层，也可以是多层，硅的氧化物对应的反应气体可以为SiH₄、NH₃、N₂或SiH₂Cl₂、NH₃、N₂，通过一次普通的光刻工艺形成导电过孔85，并形成图12所示的第八状态。Specifically, for the array substrate in the seventh state shown in FIG. 11 , the thickness deposited by the plasma-enhanced chemical vapor deposition method is

The passivation layer 9, the passivation layer 9 can be selected from oxides, nitrides or oxygen-nitrogen compounds, which can be single-layer or multi-layer, and the reactive gases corresponding to silicon oxides can be SiH ₄ , NH ₃ , N ₂ or SiH ₂ Cl ₂ , NH ₃ , N ₂ , the conductive vias 85 are formed through a common photolithography process, and the eighth state shown in FIG. 12 is formed.

的透明导电层，透明导电层可以是ITO或者IZO，或者是其他的透明金属氧化物，然后通过一次普通的光刻工艺形成透明的像素电极87，以此形成图13、图14所示的阵列基板100的最终状态。For the array substrate in the eighth state shown in FIG. 12 , the thickness of the upper layer is continuously deposited by sputtering or thermal evaporation.

The transparent conductive layer can be ITO or IZO, or other transparent metal oxides, and then a transparent pixel electrode 87 is formed through an ordinary photolithography process to form the array shown in FIG. 13 and FIG. 14 The final state of the substrate 100 .

In the embodiment of the present application, in the second photolithography process in step S30, after the TFT channel region 43 is formed, it further includes:

The portion of the metal oxide semiconductor pattern 5 located in the TFT channel region 43 is treated with NO to repair the damage of the oxide semiconductor pattern during the etching process of the source electrode 7 and the drain electrode 8, thereby improving the TFT device. performance.

This embodiment provides an array substrate 100 , a display panel, and a method for fabricating the array substrate 100 , including: depositing a gate metal layer on a base substrate 1 , and performing a first photolithography process, so as to deposit a gate metal layer on the base substrate 1 . The gate 2 and the gate line are formed; the gate insulating layer 3, the metal oxide semiconductor layer 5', the barrier layer 6, and the Cu-containing element are sequentially deposited on the base substrate 1 formed with the gate 2 and the gate line. A source-drain metal layer 8', and an anti-oxidation layer containing a CuNx layer is formed on the source-drain metal layer 8' containing Cu elements, and the metal oxide semiconductor layer 5', the barrier layer 6, and the source-drain metal containing Cu elements are formed. The second photolithography process is performed on the layer 8' and the anti-oxidation layer, so that the metal oxide semiconductor layer 5' forms the metal oxide semiconductor pattern 5, and the barrier layer 6 is formed on the metal oxide semiconductor pattern 5 and the source electrode 7 and the drain electrode. The anti-diffusion pattern between the electrodes 8 forms the source electrode 7 and the drain electrode 8 in the source-drain metal layer 8' containing Cu element, and the anti-oxidation layer forms an anti-oxidation pattern. An anti-oxidation layer containing a CuNx layer 80 is formed on the surface of the source-drain metal layer 8' containing Cu elements, so a CuNx pattern 80' is formed on the surfaces of the source electrode 7 and the drain electrode 8 formed by etching. When the passivation layer 9 containing SiOx is deposited on the surface of the drain electrode 8 and the source electrode 7 and the drain electrode 8, CuNx can protect the source electrode 7 and the drain electrode 8 from being oxidized by the passivation layer 9 containing SiOx. Therefore, peeling of the source electrode 7 and the drain electrode 8 can be prevented, and the reliability of the array substrate 100 can be improved. In addition, the TFT is formed through two photolithography processes, which reduces the number of processes and reduces the cost.

Embodiment 2

FIG. 15 is a schematic structural diagram of an array substrate according to Embodiment 2 of the present invention. As shown in FIG. 15 , the present invention provides an array substrate 100 . The array substrate is formed by the manufacturing method of the array substrate described in Embodiment 1. The array substrate 100 includes : base substrate 1 and gate electrode 2, gate insulating layer 3, metal oxide semiconductor pattern 5, barrier pattern 6', source electrode 7 and drain electrode 8 containing Cu element, The oxidation pattern 41 and the passivation layer 9 , the anti-oxidation pattern 41 includes a CuNx pattern 80 ′, and the CuNx pattern 80 ′ is located on the surface of the source electrode 7 and the drain electrode 8 containing Cu elements close to the surface of the passivation layer 9 .

The gate insulating layer 3 covers the gate 2, the blocking pattern 6', the source electrode 7 and the drain electrode 8 containing Cu element, and the anti-oxidation pattern 41 are all arranged above the metal oxide semiconductor pattern 5, and the blocking pattern 6' , the source electrode 7 and the drain electrode 8 containing Cu element, and the projection of the anti-oxidation pattern 41 on the base substrate 1 coincide, and there is a channel region between the source electrode 7 and the drain electrode 8 .

In the above scheme, by forming the anti-oxidation pattern 41 including the CuNx pattern 80 ′ on the surface of the source electrode 7 and the drain electrode 8 close to the passivation layer 9 , in the passivation layer 9 on the surface of the source electrode 7 and the drain electrode 8 When SiOx is contained, CuNx can protect the source electrode 7 and the drain electrode 8, preventing the source electrode 7 and the drain electrode 8 from being oxidized by the passivation layer 9 containing SiOx, so it can prevent the source electrode 7 and the drain electrode 8 from peeling off, The reliability of the array substrate 100 is improved.

Specifically, the base substrate 1 in the present application can be directly a glass substrate 11 , and the gate electrode 2 is directly deposited on the base substrate 1 . In some other examples, for example, in the case where the gate electrode 2 includes Cu element, the base substrate 1 may also include a glass substrate 11 and an adhesion layer (the adhesion layer pattern 12 ) deposited on the glass substrate 11, and the adhesion layer is close to the The gate 2 is arranged and used to increase the adhesion between the gate 2 and the base substrate 1 . Since the adhesion between the gate electrode 2 and the glass substrate 11 is increased, the gate electrode 2 can also be prevented from peeling off to a certain extent.

主要用于增加栅极2中Cu和衬底基板1的附着力。In the embodiment of the present application, the material of the adhesion layer may include at least one of Cr (chromium element), W (tungsten element), Ti (titanium element), Ta (tantalum element), and Mo (molybdenum element). The layer can be Mo alloy, Ti alloy, etc., and the thickness of the adhesion layer is about

It is mainly used to increase the adhesion between Cu in the gate 2 and the base substrate 1 .

栅绝缘层3可以选用氧化物、氮化物或者氧氮化合物，对应的反应气体可以为SiH₄、NH₃、N₂或SiH₂Cl₂、NH₃、N₂。In the embodiment of the present application, the gate electrode 2 may include Cu element, and the thickness of the gate electrode 2 is about

The gate insulating layer 3 can be selected from oxides, nitrides or oxygen-nitrogen compounds, and the corresponding reactive gases can be SiH ₄ , NH ₃ , N ₂ or SiH ₂ Cl ₂ , NH ₃ , and N ₂ .

In addition, the metal oxide semiconductor pattern 5 may be amorphous IGZO, and the metal oxide semiconductor layer 5 may be made of amorphous IGZO, HIZO, IZO, a-InZnO, a-InZnO, ZnO:F, In ₂ O ₃ :Sn, In ₂ O ₃ :Mo, Cd ₂ SnO ₄ , ZnO:Al, TiO ₂ :Nb, Cd-Sn-O or other metal oxides.

此外，阻挡图形6'的材料可以包括Cr、W、Ti、Ta、Mo中的至少一者，例如，阻挡图形6'也可以为Mo合金、Ti合金等。阻挡图形6'用作源极7和漏极8中的Cu元素的防扩散层，可以防止源极7和漏极8中的Cu元素扩散到金属氧化物半导体图形5中，同时又可以增加源极7和漏极8中Cu元素与金属氧化物半导体图形5的附着力，减少源极7和漏极8剥落情况的发生。Optionally, the thickness of the blocking pattern 6' is

In addition, the material of the barrier pattern 6' may include at least one of Cr, W, Ti, Ta, and Mo. For example, the barrier pattern 6' may also be Mo alloy, Ti alloy, or the like. The blocking pattern 6' serves as an anti-diffusion layer for the Cu element in the source electrode 7 and the drain electrode 8, which can prevent the Cu element in the source electrode 7 and the drain electrode 8 from diffusing into the metal oxide semiconductor pattern 5, and can increase the source The adhesion between the Cu element in the electrode 7 and the drain 8 and the metal oxide semiconductor pattern 5 reduces the occurrence of peeling of the source 7 and the drain 8.

进一步的，为了防止源极7和漏极8中的Cu元素被氧化，可以在源极7和漏极8的靠近钝化层9的表面形成CuNx图形80'。In addition, both the source electrode 7 and the drain electrode 8 may contain Cu element, or one of them may contain Cu element. For example, the thickness of source 7 and drain 8 can be

Further, in order to prevent the Cu element in the source electrode 7 and the drain electrode 8 from being oxidized, a CuNx pattern 80 ′ may be formed on the surface of the source electrode 7 and the drain electrode 8 close to the passivation layer 9 .

The CuNx pattern 80 ′ can be formed by surface-treating the surfaces of the source electrode 7 and the drain electrode 8 . The plasma gas used in the surface treatment process can be N ₂ plasma, NH ₃ , or H ₂ plasma. It can be understood that when different gases are used to treat the surface, the source electrode 7 or the drain electrode 8 The layers of substances generated on the surface are different.

In addition, the above-mentioned surface treatment can be realized by different equipment. For example, N ₂ plasma treatment is performed in a dry etching equipment to generate CuNx, the corresponding radio frequency power is 15KW~35KW, the air pressure is 100mT~1500mT, and the gas flow rate is 600～2500sccm; N ₂ plasma treatment is performed in PECVD (Plasma Enhanced Chemical Vapor Deposition) equipment to generate CuNx, the corresponding radio frequency power is 7KW～20KW, the air pressure is 800mT～1500mT, and the gas flow rate is 8000～40000sccm.

In addition, optionally, the thickness of the CuNx pattern 80' may be smaller than the thickness of the barrier pattern 6'. By making the thickness of the CuNx pattern 80' thinner, it is favorable for the source electrode 7 and the drain electrode 8 to form a better pattern during etching.

且钝化层9可以选用氧化物、氮化物或者氧氮化合物，可以是单层也可以是多层，硅的氧化物对应的反应气体可以为SiH₄，N₂O；氮化物或者氧氮化合物对应气体是SiH₄、NH₃、N₂或SiH₂Cl₂、NH₃、N₂。可以理解的是，现有技术中，钝化层9一般选用氮化硅等，而金属氧化物薄膜晶体管特性对氮元素很敏感，甚至会使金属氧化物薄膜晶体管失去特性。因此，至少需要使钝化层9中与TFT沟道区域相接触的部分为硅的氧化物，以用来提升TFT的稳定性。In the embodiment of the present application, the thickness of the passivation layer 9 is

And the passivation layer 9 can be selected from oxides, nitrides or oxygen-nitrogen compounds, which can be single-layer or multi-layer, and the reaction gases corresponding to silicon oxides can be SiH ₄ , N ₂ O; nitrides or oxygen-nitrogen compounds The corresponding gases are SiH ₄ , NH ₃ , N ₂ or SiH ₂ Cl ₂ , NH ₃ , N ₂ . It can be understood that, in the prior art, the passivation layer 9 is generally made of silicon nitride or the like, and the characteristics of metal oxide thin film transistors are very sensitive to nitrogen elements, and even the characteristics of metal oxide thin film transistors may be lost. Therefore, at least the part of the passivation layer 9 in contact with the TFT channel region needs to be made of silicon oxide, so as to improve the stability of the TFT.

像素电极87可以为透明导电薄膜，透明导电薄膜可以是氧化铟锡ITO或者氧化铟锌IZO，或者其他的透明金属氧化物。In addition, a pixel electrode 87 is also provided on the passivation layer 9, and the thickness of the pixel electrode 87 is

The pixel electrode 87 may be a transparent conductive film, and the transparent conductive film may be indium tin oxide ITO or indium zinc oxide IZO, or other transparent metal oxides.

For the above-mentioned layers, the gate insulating layer 3 covers the entire layer of the base substrate 1, and covers the gate 2, and the barrier pattern 6', the source electrode 7 and the drain electrode 8 containing Cu element, and the anti-oxidation pattern 41 are all arranged on the Above the metal oxide semiconductor pattern 5 . The projections of the barrier pattern 6' and the source electrode 7 and the drain electrode 8 containing Cu elements on the base substrate 1 are coincident, which means that the barrier pattern 6', the source electrode 7 and the drain electrode 8 can be etched at the same time in the same process. Formed, the channel region between the source electrode 7 and the drain electrode 8 exposes part of the metal oxide semiconductor pattern 5 and is in contact with the passivation layer 9 .

In this embodiment of the present application, the metal oxide semiconductor pattern 5 includes, but is not limited to, one layer, and may also be formed of two layers. For example, in a TFT device using back-channel etching, in order to prevent the metal oxide semiconductor pattern 5 from being damaged by the etching medium in the etching process of the source electrode 7 and the drain electrode 8, the metal oxide semiconductor pattern 5 may include each other. The first semiconductor pattern 51' and the second semiconductor pattern 52' are overlapped, and the conductivity of the first semiconductor pattern 51' is higher than that of the second semiconductor pattern 52'.

By making the metal oxide semiconductor pattern 5 include the first semiconductor pattern 51' with higher conductivity and the second semiconductor pattern 52' with lower conductivity, the second semiconductor pattern 52' with lower conductivity is directly connected to the source-drain metal layer. Contact can reduce the contact resistance between the metal oxide semiconductor pattern 5 and the source electrode 7 and the drain electrode 8, and increase the on-state current of the metal oxide thin film transistor; and the first semiconductor pattern 51' with higher conductivity is directly insulated from the gate. Layer 3 is in contact to form the channel of the thin film transistor, which can make the performance of the thin film transistor more stable.

第二半导体图形52'的厚度也可以为

In the above solution, optionally, the thickness of the first semiconductor pattern 51' may be

The thickness of the second semiconductor pattern 52' may also be

The conductivity of each semiconductor pattern can be controlled according to the oxygen content in the semiconductor pattern. For example, the oxygen content of the second semiconductor pattern 52' can be lower than that of the first semiconductor pattern 51', so that the oxygen content of the second semiconductor pattern 52' can be lower than that of the first semiconductor pattern 51'. The conductivity of the second semiconductor pattern 52' is lower than that of the first semiconductor pattern 51'. In addition, the electrical conductivity of the first semiconductor pattern 51 ′ is relatively high, so the electrical conductivity is poor, and the first semiconductor pattern 51 ′ can be regarded as a conductor. The conductivity of the second semiconductor pattern 52' is relatively low, and can be regarded as a semiconductor.

In this embodiment of the present application, in order to further improve the oxidation resistance of Cu in the source electrode 7 and the drain electrode 8 , the oxidation prevention pattern 41 may further include a protection pattern 81 ′ located between the CuNx pattern 80 ′ and the passivation layer 9 , here , the protection pattern 81' is used to prevent oxidation of the Cu element contained in the source electrode 7 and the drain electrode 8, and the projections of the protection pattern 81' and the blocking pattern 6' on the base substrate 1 overlap, that is, the protection pattern 81', the blocking pattern 6', the source electrode 7 and the drain electrode 8 can be formed by the same etching process in the same process.

Optionally, the material of the protection pattern 81' may include at least one of Cr, W, Ti, Ta, and Mo, and at least one of Cr, W, Ti, Ta, and Mo may form a dense oxide film after being oxidized , which coats the surface of the source electrode 7 and the drain electrode 8 to prevent the Cu in the source electrode 7 and the drain electrode 8 from being oxidized. In addition, the thickness of the protective pattern 81' may be

It should be understood that although the embodiments of the present application take the oxidation resistance of Cu in the source electrode 7 and the drain electrode 8 as an example for description, in the actual manufacturing process of the array substrate 100 , the scan line 82 (gate line) and the gate 2 is formed at the same time as the gate 2 in the same process, and the data line 83 (the trace of the source 7 or the drain 8) and the source 7 or the drain 8 are formed at the same time as the source 7 or the drain 8 in the same process . Therefore, the anti-oxidation of the scan lines 82 and the data lines 83 can also be used to generate CuNx patterns 80 ′ on the surfaces of the source electrodes 7 and the drain electrodes 8 near the passivation layer 9 , or further generate a protection pattern 81 ′ on the CuNx patterns 80 ′ However, the steps and processes of the formation are similar to those of the source electrode 7 and the drain electrode 8 , which will not be repeated here.

In addition, in practice, the array substrate 100 will include a plurality of sub-pixel regions defined by the scan lines 82 and the data lines 83, and each sub-pixel region is provided with a thin film transistor device. For the convenience of description, the accompanying drawings of the present application , only a schematic diagram of one of the sub-pixel regions is drawn. It can be understood that the array substrate 100 in this application includes a plurality of sub-pixel regions. Therefore, in the manufacturing process of the array substrate 100 in this application, the mentioned Forming the gate 2 and the gate line on the base substrate 1 specifically refers to forming the gate 2 and the gate line in the region of the array substrate 100 corresponding to each sub-pixel region. The case of the source electrode 7 , the drain electrode 8 , and the metal oxide semiconductor pattern 5 is similar to this, and will not be repeated here.

In the embodiment of the present application, the array substrate 100 includes: a base substrate 1 , a gate electrode 2 , a gate insulating layer 3 , a metal oxide semiconductor pattern 5 , a blocking pattern 6 ′, and a Cu element are sequentially arranged on the base substrate 1 . The source electrode 7 and the drain electrode 8, the anti-oxidation pattern and the passivation layer 9, the anti-oxidation pattern includes a CuNx pattern, and the CuNx pattern is located on the surface of the source electrode 7 and the drain electrode 8 containing the Cu element near the passivation layer 9; The electrode insulating layer 3 covers the gate electrode 2, the blocking pattern 6', the source electrode 7 and the drain electrode 8 containing Cu element, and the anti-oxidation pattern 41 are all arranged above the metal oxide semiconductor pattern 5, and the blocking pattern 6' and the Cu element containing The source electrode 7 and the drain electrode 8 of the element and the projections of the anti-oxidation pattern on the base substrate 1 overlap, and there is a channel region between the source electrode 7 and the drain electrode 8 . By forming CuNx patterns 80 ′ on the surfaces of the source electrode 7 and the drain electrode 8 close to the passivation layer 9 , the passivation layer 9 on the surface of the source electrode 7 and the drain electrode 8 contains SiOx , and CuNx can affect the source electrode 7 and the drain electrode 8 . The electrode 8 plays a protective role to prevent the source electrode 7 and the drain electrode 8 from being oxidized by the passivation layer 9 containing SiOx, thus preventing the source electrode 7 and the drain electrode 8 from peeling off and improving the reliability of the array substrate 100 .

Embodiment 3

This embodiment provides a display panel, including the array substrate 100 in the second embodiment, wherein the specific structure and function of the array substrate 100 have been described in detail in the foregoing second embodiment, and thus will not be repeated here.

The display panel may be a liquid crystal display panel. In this case, the display panel includes a color filter substrate, a liquid crystal layer, and the array substrate 100 described in Embodiment 2. The liquid crystal layer is sandwiched between the color filter substrate and the array substrate 100 .

The display panel may also be an organic light emitting diode display panel. In this case, the display panel includes the array substrate 100 described in Embodiment 2, an encapsulation layer and an organic layer, wherein the organic layer is sandwiched between the array substrate 100 and the encapsulation layer.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, but not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions described in the foregoing embodiments can still be modified, or some or all of the technical features thereof can be equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the embodiments of the present invention. scope.

Claims (10)

1. A manufacturing method of an array substrate is characterized by comprising the following steps:

depositing a grid metal layer on a substrate base plate, and carrying out a first photoetching process to form a grid and a grid line on the substrate base plate;

sequentially depositing a gate insulating layer, a metal oxide semiconductor layer, a barrier layer and a source drain metal layer containing a Cu element on the substrate base plate on which the gate and the gate line are formed, and forming an anti-oxidation layer containing a CuNx layer on the source drain metal layer containing the Cu element;

and carrying out a second photoetching process on the metal oxide semiconductor layer, the barrier layer, the source and drain metal layers containing the Cu element and the anti-oxidation layer, so that the metal oxide semiconductor layer forms a metal oxide semiconductor pattern, the barrier layer forms an anti-diffusion pattern positioned between the metal oxide semiconductor pattern and the source and drain electrodes, the source and drain metal layers containing the Cu element form the source and drain electrodes, and the anti-oxidation layer forms the anti-oxidation pattern.

2. The method for manufacturing the array substrate according to claim 1, wherein the forming of the oxidation prevention layer including the CuNx layer on the source drain metal layer containing the Cu element specifically includes:

and carrying out plasma treatment on the source and drain metal layer containing the Cu element so as to form the CuNx layer on the surface of the source and drain metal layer containing the Cu element.

3. The method for manufacturing the array substrate according to claim 2, wherein the oxidation preventing layer further comprises a protective layer for preventing oxidation of Cu in the source/drain metal layer, and before the second photolithography process, the method further comprises a step of depositing the protective layer on the CuNx layer.

4. The method of claim 3, wherein the material of the passivation layer comprises at least one of Cr, W, Ti, Ta, and Mo.

5. The method for manufacturing the array substrate according to any one of claims 1 to 4, wherein the second photolithography process comprises a gray tone mask process or a halftone mask process.

6. The method for manufacturing an array substrate according to any one of claims 1 to 4,

in the second photolithography process, after the forming of the source and the drain, the method further includes:

and carrying out primary treatment on the part of the metal oxide semiconductor pattern, which is positioned in the channel region, by using NO so as to repair the damage of the metal oxide semiconductor pattern in the etching process of the source electrode and the drain electrode.

7. The method for manufacturing the array substrate according to any one of claims 1 to 4, wherein the gate comprises Cu, and the method for forming the substrate comprises: and depositing an adhesion layer before depositing the gate metal layer on the substrate base plate, wherein the adhesion layer is in contact with the gate metal layer and is used for increasing the adhesion between the gate metal layer and the substrate base plate.

8. The method for manufacturing the array substrate according to any one of claims 1 to 4, wherein the metal oxide semiconductor layer comprises a first semiconductor layer and a second semiconductor layer, and the first semiconductor layer has a higher conductivity than the second semiconductor layer;

the method for sequentially depositing the gate insulating layer, the metal oxide semiconductor layer, the barrier layer and the source drain metal layer containing the Cu element on the substrate base plate with the gate comprises the following steps:

and sequentially depositing a grid electrode insulating layer, a first semiconductor layer, a second semiconductor layer, a barrier layer and a source drain metal layer containing Cu element on the substrate base plate on which the grid electrode is formed.

9. An array substrate, comprising: the anti-oxidation graph comprises a CuNx graph, and the CuNx graph is positioned on the surface, close to the passivation layer, of the source electrode and the drain electrode containing the Cu element;

the gate insulating layer covers the gate, the blocking pattern, the source electrode and the drain electrode containing the Cu element and the anti-oxidation pattern are arranged above the metal oxide semiconductor pattern, projections of the blocking pattern, the source electrode and the drain electrode containing the Cu element and the anti-oxidation pattern on the substrate are overlapped, and a channel region is arranged between the source electrode and the drain electrode.

10. A display panel comprising the array substrate according to claim 9.

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