CN111403266B - Epitaxial filling method of groove - Google Patents
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- CN111403266B CN111403266B CN202010326164.9A CN202010326164A CN111403266B CN 111403266 B CN111403266 B CN 111403266B CN 202010326164 A CN202010326164 A CN 202010326164A CN 111403266 B CN111403266 B CN 111403266B
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- 238000001259 photo etching Methods 0.000 claims abstract description 3
- 150000004767 nitrides Chemical class 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
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- 239000002019 doping agent Substances 0.000 description 2
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Abstract
The invention discloses an epitaxial filling method of a groove, which comprises the following steps: step one, forming a hard mask layer on the surface of a semiconductor substrate; step two, defining a forming area of the groove by photoetching and etching the hard mask layer; etching the semiconductor substrate by taking the hard mask layer as a mask to form the groove; fourthly, transversely reducing the transverse size of the hard mask layer of each platform area from two sides to the middle; and step five, selectively epitaxially growing a first epitaxial layer to completely fill the groove, and reducing the transverse size of the hard mask layer in the step four to reduce the stress of the step epitaxial layer and reduce or eliminate the stress defect. The invention can increase the process window, is beneficial to reducing the size of the device, can reduce the filling difficulty and can increase the productivity.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for filling a trench with an epitaxy.
Background
Fig. 1A to fig. 1F are schematic views of a device structure in each step of an epitaxial filling method for a first trench in the prior art; the existing first method for filling the trenches by epitaxy includes the following steps:
step one, as shown in fig. 1A, a semiconductor substrate 101 is provided, and a hard mask layer 103 is formed on a surface of the semiconductor substrate 101.
Typically, a second epitaxial layer 102 is also formed on the surface of the semiconductor substrate 101, and a subsequent trench 104 is formed in the semiconductor substrate 101.
The semiconductor substrate 101 is a silicon substrate. The second epitaxial layer 102 is a silicon epitaxial layer; the subsequently formed first epitaxial layer 106 is a silicon epitaxial layer.
The hard mask layer 103 is formed by stacking a first oxide layer 1031, a second nitride layer 1032, and a third oxide layer 1033.
Step two, as shown in fig. 1B, defining a formation region of the trench 104 by photolithography, etching the hard mask layer 103 to remove the hard mask layer 103 in the formation region of the trench 104 and to retain the hard mask layer 103 in the platform region between the trenches 104.
And step three, as shown in fig. 1B, etching the semiconductor substrate 101 with the hard mask layer 103 as a mask to form the trench 104.
The semiconductor substrate 101 is formed with a plurality of trenches 104, the trenches 104 and the land regions are alternately arranged, and a step (Pitch) is a sum of a width of one of the trenches 104 and a width of an adjacent land region.
In general, the third oxide layer 1033 serves as an etching stop layer when the trench 104 is formed, and the thickness of the third oxide layer 1033 is such that a part of the thickness remains after the trench 104 is formed by etching.
As shown in fig. 1C, after the etching process of the trench 104 is completed, the remaining third oxide layer 1033 is removed.
After removing the third oxide layer 1033, the method further comprises the steps of:
as shown in fig. 1C, a sacrificial oxide layer 5 is formed on the inner side surface of the trench 104;
as shown in fig. 1D, the sacrificial oxide layer 5 is then removed. During the process of removing the sacrificial oxide layer 5, a certain lateral etching may be performed on the first oxide layer 1031 at the bottom of the second nitride layer 1032 and an undercut (undercut) structure may be formed.
Thereafter, as shown in fig. 1E, the second nitride layer 1032 is removed. The remaining first oxide layer 1031 serves as the hard mask layer 103 in a subsequent process.
Step four, as shown in fig. 1F, selectively epitaxially growing a first epitaxial layer 106 to completely fill the trench 104; in each of the mesa regions, the first epitaxial layer 106 may further extend to the surface of the hard mask layer 103, and the first epitaxial layer 106 extending to the surface of the hard mask layer 103 is a stepped epitaxial layer, which may generate stress in the first epitaxial layer 106 and easily form stress defects, mainly because the bottom structures of the stepped epitaxial layer and the first epitaxial layer 106 in other regions are different, and the lattice structure of the stepped epitaxial layer when formed on the hard mask layer 103 is easily different from the lattice structure of the first epitaxial layer 106 in other regions, so that stress and defects are easily generated.
In fig. 1F, the first epitaxial layer 106 formed in the trench 104 on both sides of the mesa region does not laterally contact the top of the hard mask layer 103, i.e., the first oxide layer 1031. The formation region of the step epitaxial layer is shown by a dashed box 106a, and the spacing region between two adjacent first epitaxial layers 106 on top of the mesa region is shown by a dashed box 107.
As shown in fig. 3A, which is a side view of the corresponding device of fig. 1F, with the view angle of fig. 3A perpendicular to the cross-section of fig. 1F, it can be seen that a stress defect occurs in the dashed circle 108.
Fig. 3B is also a side view of the device corresponding to fig. 1F, the viewing angle of fig. 3B is at an angle to the sectional vertical line of fig. 1F, and fig. 3B also shows that the thickness of the step-epitaxial layer on top of the first oxide layer 1031 is 1.79 μm.
In general, with the dashed box 107, the hard mask layer 103 does not affect the thickness of the step epitaxial layer, and the stress caused by the step epitaxial layer does not increase significantly. As the size of the device is continuously reduced, the size of the mesa region is also continuously reduced, which is easy to make the step epitaxial layer extended from two adjacent trenches on the mesa region contact, and this situation corresponds to the second method, as shown in fig. 2, is a schematic view of the device structure after the trenches are filled by the epitaxial filling method of the second trench; the difference from the first method in the prior art is that, in the second method in step four, after the selective epitaxial growth is completed, the first epitaxial layer 106 completely fills the trenches 104, and the step epitaxial layers on both sides of the mesa region are in contact with each other, so that the first epitaxial layers 106 in all the trenches 104 are connected to form an integral structure; the formation region of the step epitaxial layer shown in fig. 2 is indicated by a dashed box corresponding to reference numeral 106 b. After the first epitaxial layer 106 on the top of the mesa region is contacted, the epitaxial layer on the top of the first oxide layer 1031 directly grows on the epitaxial layer on the bottom, which greatly accelerates the growth speed of the epitaxial layer on the top of the first oxide layer 1031, so that the thickness of the step epitaxial layer on the top of the first oxide layer 1031 is increased, the accumulated stress of the step epitaxial layer also increases, that is, the thicker the step epitaxial layer is, the larger the volume of the step epitaxial layer which can exert a stress action on the first epitaxial layer 106 outside the step epitaxial layer, that is, in other regions is, and finally, the accumulated stress on the first epitaxial layer 106 in other regions is also larger, and finally, the stress of the step epitaxial layer can spread in the whole first epitaxial layer 106, and finally, the device failure is caused.
As shown in fig. 4A, which is a side view of the device corresponding to fig. 2, the viewing angle of fig. 4A is at an angle to the sectional vertical line of fig. 2, it can be seen that the step epitaxial layers 106a between adjacent trenches 104 will contact, and in fig. 4A, it is also shown that a void 19 is also formed in the region of the contact location.
Fig. 4B is an enlarged photograph of fig. 4A, and fig. 4B also shows that the thickness of the step epitaxial layer on top of the first oxide layer 1031 is 2123nm, i.e., 2.123 μm, and that the thickness of the step epitaxial layer in fig. 4B is increased as compared to fig. 3B, which increases stress and increases defects generated by the stress.
As can be seen from the comparison of the two methods, the second conventional method generates more stress and stress defects, so the width of the hard mask layer 103 on the mesa region is usually increased as much as possible in the conventional improved method, so as to prevent the step epitaxial layers on both sides of the mesa region from merging, i.e., to avoid the second conventional method, thereby directly implementing the first conventional method. However, the maximum width of the hard mask layer 103 is determined by the Pitch of the Cell structure (Cell) and the size of the trench 104, and it is only possible to control the undercut in the process as much as possible, thereby reducing the loss of the hard mask layer length. Experiments have shown that this approach is helpful. However, as Pitch continues to shrink, the size of the hard mask layer itself is also decreasing significantly. This approach has limited room for improvement.
Disclosure of Invention
The invention aims to provide an epitaxial filling method of a groove, which can reduce the stress of an epitaxial layer for filling the groove and the defects caused by the stress.
In order to solve the technical problem, the epitaxial filling method of the trench provided by the invention comprises the following steps:
step one, providing a semiconductor substrate, and forming a hard mask layer on the surface of the semiconductor substrate.
And step two, defining a forming area of the groove by photoetching, etching the hard mask layer to remove the hard mask layer in the forming area of the groove and reserve the hard mask layer in a platform area between the grooves.
And step three, etching the semiconductor substrate by taking the hard mask layer as a mask to form the groove.
And fourthly, laterally reducing the lateral dimension of the hard mask layer of each platform area from two sides to the middle and exposing the surface of the corresponding semiconductor substrate.
Step five, selectively epitaxially growing a first epitaxial layer to completely fill the groove, wherein the first epitaxial layer grows on the surface of the semiconductor substrate corresponding to the inner side surface of the groove and the surface of the semiconductor substrate exposed in the platform region at the same time; in each of the mesa regions, the first epitaxial layer may further extend to the surface of the hard mask layer, the first epitaxial layer extending to the surface of the hard mask layer is a step epitaxial layer, the step epitaxial layer may generate stress in the first epitaxial layer, the smaller the lateral dimension of the hard mask layer is, the smaller the stress generated by the step epitaxial layer is, the fewer stress defects are generated, and in the fourth step, the lateral dimension of the hard mask layer is reduced to reduce or eliminate the stress defects below a process requirement value.
The further improvement is that the method also comprises the following steps:
and step six, grinding the first epitaxial layer by adopting a chemical mechanical grinding process with the hard mask layer as a stop layer.
And seventhly, removing the hard mask layer.
In a further improvement, the minimum lateral dimension of the hard mask layer in step four is also required to meet the requirement as a stop layer for the cmp process.
In a further improvement, a plurality of trenches are formed in the same semiconductor substrate, the trenches and the mesa regions are alternately arranged, and a step is performed by a sum of a width of one trench and a width of an adjacent mesa region, wherein in step four, a lateral dimension of the hard mask layer on each mesa region is reduced to 5% to 80% of the step.
In a further improvement, in step four, the lateral dimension of the hard mask layer on each of the mesa regions is reduced to 30% of the step.
In a further improvement, a second epitaxial layer is also formed on the surface of the semiconductor substrate, and the trench is formed in the semiconductor substrate.
In a further improvement, the semiconductor substrate is a silicon substrate, and the second epitaxial layer is a silicon epitaxial layer.
In a further improvement, the first epitaxial layer is a silicon epitaxial layer.
In a further improvement, the epitaxial filling method of the trench is used for forming a super junction, the first epitaxial layer has a second conductive type doping, the second epitaxial layer has a first conductive type doping, a second conductive type column is formed by the first epitaxial layer filled in the trench, a first conductive type column is formed by the second epitaxial layer between the trenches, and the first conductive type column and the second conductive type column are alternately arranged to form the super junction.
The further improvement is that in the first step, the hard mask layer is formed by overlapping a first oxide layer, a second nitride layer and a third oxide layer.
And the third oxide layer is used as an etching barrier layer when the trench is formed in the third step, the thickness of the third oxide layer meets the requirement that a part of thickness still remains after the trench is formed by etching, and the remaining third oxide layer is removed after the etching process of the trench in the third step is completed.
In a further improvement, after removing the third oxide layer, the method further includes a step of removing the sacrificial oxide layer after forming the sacrificial oxide layer on the inner side surface of the trench.
A further improvement is that, in the fourth step, the reduction of the lateral dimension of the hard mask layer is realized by the following steps:
and carrying out wet etching on the first oxide layer by taking the second nitride layer as a mask to reduce the lateral dimension of the first oxide layer to a required value.
And removing the second nitride layer, and taking the residual first oxidation layer as the hard mask layer with the reduced lateral dimension.
The further improvement is that the depth of the groove is 1-100 microns, and the thickness of the second epitaxial layer is larger than the depth of the groove; the opening width of the groove is 0.1-20 microns.
In a further improvement, in the first step, the first oxide layer has a thickness of
The thickness of the second nitride layer is
The thickness of the third oxidation layer is 0.5-3 microns.
In a further improvement, in the fifth step, the selective epitaxial growth fills the trench by etching while growing.
The invention aims at the technical problem that the epitaxial layer extending to the hard mask layer in the epitaxial filling process of the groove, namely the step epitaxial layer, can generate larger stress on the whole first epitaxial layer and further can generate stress defects.
Compared with the prior art, the method is realized by not increasing the width of the hard mask layer in the platform area, but reducing the width of the hard mask layer in the platform area, so that the process window can be greatly increased, the limitation of continuous reduction of the size of the device is avoided, and the size reduction of the device is facilitated.
In addition, the process of filling the groove by adopting the selective epitaxial growth process is a process of growing and etching simultaneously, and after the transverse dimension of the hard mask layer is reduced, the etching of the opening at the top of the groove in the groove filling process is facilitated, and the sealing at the top of the groove can be well prevented, so the invention can also reduce the process difficulty, finally reduce the filling time and increase the productivity.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIGS. 1A-1F are schematic diagrams of device structures in steps of a conventional first trench epitaxial filling method;
FIG. 2 is a schematic diagram of a device structure after trench filling according to a second conventional trench epitaxial filling method;
FIGS. 3A-3B are photographs of a device after trench filling formed by a first prior art method;
FIGS. 4A-4B are photographs of a device after trench filling formed by a second prior art method;
FIG. 5 is a flow chart of a method for epitaxial filling of a trench in accordance with an embodiment of the present invention;
FIGS. 6A-6H are schematic device structures at various steps of a method for epitaxial trench filling according to an embodiment of the present invention;
fig. 7A-7B are photographs of devices after trench filling formed by a method in accordance with an embodiment of the present invention.
Detailed Description
Fig. 5 is a flowchart illustrating a method for epitaxially filling a trench according to an embodiment of the present invention; fig. 6A to 6H are schematic views of device structures in the steps of the method for filling trenches by epitaxy according to the embodiment of the invention; the epitaxial filling method of the groove comprises the following steps:
step one, as shown in fig. 6A, providing a semiconductor substrate 1, and forming a hard mask layer 3 on a surface of the semiconductor substrate 1.
In the embodiment of the present invention, a second epitaxial layer 2 is further formed on the surface of the semiconductor substrate 1, and a subsequent trench 4 is formed in the semiconductor substrate 1.
Typically, the semiconductor substrate 1 is a silicon substrate. The second epitaxial layer 2 is a silicon epitaxial layer; the first epitaxial layer 6 formed subsequently is a silicon epitaxial layer.
The hard mask layer 3 is formed by overlapping a first oxide layer 31, a second nitride layer 32 and a third oxide layer 33.
Step two, as shown in fig. 6B, defining a formation region of the trench 4 by photolithography, etching the hard mask layer 3 to remove the hard mask layer 3 in the formation region of the trench 4 and to retain the hard mask layer 3 in the platform region between the trenches 4.
And step three, as shown in fig. 6B, etching the semiconductor substrate 1 by using the hard mask layer 3 as a mask to form the trench 4.
A plurality of trenches 4 are formed in the same semiconductor substrate 1, the trenches 4 and the mesa regions are alternately arranged, and the sum of the width of one trench 4 and the width of an adjacent mesa region is used as a step.
As shown in fig. 6B, the top width of the mesa region is L1, and the width of the hard mask layer 3 remaining on the top of the mesa region is also L1.
In the embodiment of the present invention, the third oxide layer 33 is used as an etching blocking layer when the trench 4 is formed, and the thickness of the third oxide layer 33 is such that a part of the thickness remains after the trench 4 is formed by etching.
As shown in fig. 6C, after the etching process of the trench 4 is completed, the remaining third oxide layer 33 is removed.
After removing the third oxide layer 33, the method further comprises the steps of:
as shown in fig. 6C, a sacrificial oxide layer 5 is formed on the inner side surface of the trench 4;
as shown in fig. 6D, the sacrificial oxide layer 5 is then removed.
And fourthly, laterally reducing the lateral dimension of the hard mask layer 3 of each platform area from two sides to the middle and exposing the corresponding surface of the semiconductor substrate 1.
In an embodiment of the present invention, the lateral dimension of the hard mask layer 3 on each of the mesa regions is reduced to 5% to 80% of the step. Preferably, the lateral dimension of the hard mask layer 3 on each mesa region is reduced to 30% of the step.
The minimum value of the lateral dimension of the hard mask layer 3 in step four also requires that it meets the requirements as a stop layer for the chemical mechanical polishing process.
The reduction of the lateral dimension of the hard mask layer 3 is realized by the following steps:
as shown in fig. 6E, the first oxide layer 31 is wet etched using the second nitride layer 32 as a mask to reduce the lateral dimension of the first oxide layer 31 to a desired value, where in fig. 6E, the reduced lateral dimension of the first oxide layer 31 is L2.
As shown in fig. 6F, the second nitride layer 32 is removed, and the remaining first oxide layer 31 is used as the hard mask layer 3 with a reduced lateral dimension.
Step five, as shown in fig. 6G, selectively epitaxially growing a first epitaxial layer 6 to completely fill the trench 4, wherein the first epitaxial layer 6 is simultaneously grown on the surface of the semiconductor substrate 1 corresponding to the inner side surface of the trench 4 and on the surface of the semiconductor substrate 1 exposed by the mesa region; in each mesa region, the first epitaxial layer 6 may further extend to the surface of the hard mask layer 3, the first epitaxial layer 6 extending to the surface of the hard mask layer 3 is a step epitaxial layer, the step epitaxial layer may generate stress in the first epitaxial layer 6, the smaller the lateral dimension of the hard mask layer 3 is, the smaller the stress generated by the step epitaxial layer is, the fewer stress defects are generated, and in the fourth step, the lateral dimension of the hard mask layer 3 is reduced to reduce or eliminate the stress defects below a process requirement value.
The selective epitaxial growth fills the trench 4 in an etching-while-growing manner. As shown in fig. 6F, after the lateral size of the first oxide layer 31 is reduced, the area of the region of the second epitaxial layer 2 etched by HCl is increased, so that a seal can be prevented from being formed at the top of the trench 4, and the difficulty of the trench filling process can be reduced.
As shown in fig. 6G, the first epitaxial layer 6 extends to the entire mesa region, and the first epitaxial layer 6 on the mesa region is shown by a dashed box 7; the step epitaxial layer on the surface of the hard mask layer 3, i.e. the remaining first oxide layer 31, is shown by the dashed box 8. Since there is a difference in lattice structure between the first epitaxial layer 6 formed directly on the surface of the second epitaxial layer 2 and the first epitaxial layer 6, i.e., the step epitaxial layer, formed on the surface of the first oxide layer 31, stress is generated, the embodiment of the present invention can reduce the lateral size of the step epitaxial layer by reducing the lateral size of the region shown by the dashed line frame 7, so as to reduce the stress generated by the step epitaxial layer; furthermore, through the adjustment of the transverse size of the step epitaxial layer, stress defects caused by the stress generated by the step epitaxial layer can be reduced or eliminated. As can be seen from a comparison between fig. 6G and fig. 2, if the widths of the mesa regions are equal, the width of the region indicated by the dashed line box 8 in fig. 6G is smaller than the width of the region indicated by the dashed line box 106b in fig. 2, so that the width of the step epitaxial layer is reduced, only a partial region of the first epitaxial layer 6 on the entire flat region corresponding to the dashed line box 7 in fig. 6G is the step epitaxial layer with a difference in lattice structure, and the entire mesa region corresponding to the dashed line box 106b in fig. 2 is the step epitaxial layer, so that the lateral width of the step epitaxial layer in the embodiment of the present invention is greatly reduced, and finally, the accumulated stress is also greatly reduced, so that the corresponding stress defect can be reduced.
Further comprising the steps of:
sixthly, as shown in fig. 6H, the first epitaxial layer 6 is polished by using a chemical mechanical polishing process with the hard mask layer 3 as a stop layer.
Step seven, as shown in fig. 6H, the hard mask layer 3 is removed.
In the method of the embodiment of the present invention, the epitaxial filling method of the trench 4 is used to form a super junction, the first epitaxial layer 6 has a second conductivity type dopant, the second epitaxial layer 2 has a first conductivity type dopant, the first epitaxial layer 6 filled in the trench 4 forms a second conductivity type column, the second epitaxial layer 2 between the trenches 4 forms a first conductivity type column, and the first conductivity type column and the second conductivity type column are alternately arranged to form the super junction.
To illustrate the method of the embodiment of the present invention in more detail, the following is described with more specific parameters:
the depth of the grooves 4 is 1 to 100 microns, typically 40 microns.
The thickness of the second epitaxial layer 2 is greater than the depth of the trenches 4.
The opening width of the groove 4 is 0.1-20 micrometers, and the typical value is 4 micrometers; a typical value for the spacing between the trenches 4, i.e. L1, is 5 microns.
The first oxide layer 31Has a thickness of
The second nitride layer 32 has a thickness of
The thickness of the third oxide layer 33 is 0.5 to 3 micrometers.
The thickness of the sacrificial oxide layer 5 is
Is typically given a value of
The embodiment of the invention aims at the technical problem that the epitaxial layer extending to the hard mask layer 3 in the epitaxial filling process of the groove 4, namely the step epitaxial layer, generates large stress on the whole first epitaxial layer 6 and thus stress defects, after the etching of the groove 4 is completed and before the selective epitaxial growth of the first epitaxial layer 6, the transverse size of the hard mask layer 3 in the platform region is reduced, so that the transverse size of the step epitaxial layer on the surface of the hard mask layer 3 can be reduced, the stress generated due to the larger transverse size of the step epitaxial layer is also larger, the stress can be reduced by reducing the transverse size of the step epitaxial layer, and finally the stress defects generated due to the stress can be reduced.
In addition, the process of filling the groove 4 by adopting the selective epitaxial growth process is a process of growing and etching simultaneously, and after the transverse size of the hard mask layer 3 is reduced, the etching of the opening at the top of the groove 4 in the process of filling the groove 4 is facilitated, and the top of the groove 4 can be well prevented from being sealed, so the embodiment of the invention can also reduce the process difficulty, finally reduce the filling time and increase the productivity.
FIG. 7A shows a photo of a device after trench filling formed by a method according to an embodiment of the present invention; fig. 7B is an enlarged photograph of fig. 7A at the step epitaxial layer, and it can be seen that the reduction of the lateral dimension of the step epitaxial layer on top of the first oxide layer 31 is well achieved in the embodiment of the present invention as shown by the dashed box 8, so that no stress defect occurs. In the embodiment of the present invention, since the lateral dimension of the first oxide layer 31 is inherently small, the first epitaxial layer 6 between the adjacent trenches 4 is allowed to be fully merged at the top of the first oxide layer 31, and the thickness of the first epitaxial layer 6 on the top of the first oxide layer 31 is 3.21 μm as shown in fig. 7B.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (15)
1. An epitaxial filling method of a groove is characterized by comprising the following steps:
providing a semiconductor substrate, and forming a hard mask layer on the surface of the semiconductor substrate;
step two, defining a forming area of a groove by photoetching, and etching the hard mask layer to remove the hard mask layer in the forming area of the groove and reserve the hard mask layer in a platform area between the grooves;
etching the semiconductor substrate by taking the hard mask layer as a mask to form the groove;
fourthly, transversely reducing the transverse size of the hard mask layer of each platform area from two sides to the middle and exposing the surface of the corresponding semiconductor substrate;
step five, selectively epitaxially growing a first epitaxial layer to completely fill the groove, wherein the first epitaxial layer grows on the surface of the semiconductor substrate corresponding to the inner side surface of the groove and the surface of the semiconductor substrate exposed in the platform region at the same time; in each of the mesa regions, the first epitaxial layer may further extend to the surface of the hard mask layer, the first epitaxial layer extending to the surface of the hard mask layer is a step epitaxial layer, the step epitaxial layer may generate stress in the first epitaxial layer, the smaller the lateral dimension of the hard mask layer is, the smaller the stress generated by the step epitaxial layer is, the fewer stress defects are generated, and in the fourth step, the lateral dimension of the hard mask layer is reduced to reduce or eliminate the stress defects below a process requirement value.
2. A method of epitaxial filling of a trench according to claim 1 further comprising the step of:
step six, grinding the first epitaxial layer by adopting a chemical mechanical grinding process with the hard mask layer as a stop layer;
and seventhly, removing the hard mask layer.
3. A method of epitaxial filling of a trench as claimed in claim 2 wherein: the minimum value of the lateral dimension of the hard mask layer in step four is also required to meet the requirements as a stop layer for the chemical mechanical polishing process.
4. A method of epitaxial filling of a trench as claimed in claim 1 or 3 wherein: and in step four, the lateral dimension of the hard mask layer on each mesa region is reduced to 5% -80% of the step.
5. A method of epitaxial filling of a trench as claimed in claim 4 wherein: in step four, the lateral dimension of the hard mask layer on each mesa region is reduced to 30% of the step.
6. A method of epitaxial filling of a trench as claimed in claim 2 wherein: a second epitaxial layer is also formed on the surface of the semiconductor substrate, and the trench is formed in the semiconductor substrate.
7. A method of epitaxial filling of a trench as claimed in claim 6 wherein: the semiconductor substrate is a silicon substrate, and the second epitaxial layer is a silicon epitaxial layer.
8. A method of epitaxial filling of a trench as claimed in claim 7 wherein: the first epitaxial layer is a silicon epitaxial layer.
9. A method of epitaxial filling of a trench as claimed in claim 8 wherein: the epitaxial filling method of the groove is used for forming the super junction, the first epitaxial layer is doped with the second conduction type, the second epitaxial layer is doped with the first conduction type, the first epitaxial layer filled in the groove forms a second conduction type column, the second epitaxial layer between the grooves forms a first conduction type column, and the first conduction type column and the second conduction type column are alternately arranged to form the super junction.
10. A method of epitaxial filling of a trench as claimed in claim 8 or 9 wherein: the hard mask layer in the first step is formed by overlapping a first oxide layer, a second nitride layer and a third oxide layer;
and the third oxide layer is used as an etching barrier layer when the trench is formed in the third step, the thickness of the third oxide layer meets the requirement that a part of thickness still remains after the trench is formed by etching, and the remaining third oxide layer is removed after the etching process of the trench in the third step is completed.
11. A method of epitaxial filling of a trench as claimed in claim 10 wherein: and after removing the third oxide layer, the method further comprises the step of removing the sacrificial oxide layer after forming the sacrificial oxide layer on the inner side surface of the groove.
12. A method of epitaxial filling of a trench as claimed in claim 10 wherein: in the fourth step, the reduction of the lateral dimension of the hard mask layer is realized by adopting the following steps:
taking the second nitride layer as a mask, and carrying out wet etching on the first oxide layer to reduce the lateral dimension of the first oxide layer to a required value;
and removing the second nitride layer, and taking the residual first oxidation layer as the hard mask layer with the reduced lateral dimension.
13. A method of epitaxial filling of a trench as claimed in claim 12 wherein: the depth of the groove is 1-100 microns, and the thickness of the second epitaxial layer is larger than the depth of the groove; the opening width of the groove is 0.1-20 microns.
14. A method of epitaxial filling of a trench as claimed in claim 13 wherein: in the first step, the thickness of the first oxide layer is
The second nitride layer has a thickness of
The thickness of the third oxidation layer is 0.5-3 microns.
15. A method of epitaxial filling of a trench as claimed in claim 1 wherein: and step five, filling the groove by adopting a mode of etching while growing in the selective epitaxial growth.
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