CN111384931A - Delay circuit, method, delay chain and chip - Google Patents
Delay circuit, method, delay chain and chip Download PDFInfo
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- CN111384931A CN111384931A CN201811615768.4A CN201811615768A CN111384931A CN 111384931 A CN111384931 A CN 111384931A CN 201811615768 A CN201811615768 A CN 201811615768A CN 111384931 A CN111384931 A CN 111384931A
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- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
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Abstract
The embodiment of the invention provides a delay circuit, a method, a delay chain and a chip, wherein the delay circuit comprises: the device comprises a signal receiving module, an RS triggering module, a burr eliminating module and a delay module. According to the embodiment of the invention, the enabling signal is processed by the signal receiving module to obtain the first output signal and the second output signal which are used as the input of the RS trigger module, the third output signal and the fourth output signal are obtained through the trigger logic of the RS trigger module, then the fifth output signal is obtained by delaying the third output signal by the burr eliminating module, the fifth output signal is delayed from the fourth output signal, the phenomenon that the fifth output signal is changed into high level earlier than the fourth output signal is avoided, and burrs cannot be generated in the delay module because the fifth output signal is changed into high level earlier than the fourth output signal.
Description
Technical Field
The present invention relates to the field of circuit technologies, and in particular, to a delay circuit, a delay method, a delay chain, and a chip.
Background
Delay circuits are widely used in integrated circuits, and the delay circuits can delay input signals to a certain extent so as to meet the working requirements of various components in the integrated circuits. With the development of delay circuits, digital delay chains (dcdlls) are increasingly used, which are key components of circuits such as ADPLLs (all-digital PLLs), ADDLLs (all-digital DLLs), and SSCGs (spread-spectrum clock generators).
A prior art delay circuit may typically comprise N identical delay cells, N being a natural number, referred to as an N-bit delay chain. As shown in fig. 1, the delay circuit includes 2-bit delay cells, the input terminal is a, the output terminal is bo, en is a control signal, and the outputs ao and b of the last stage delay cell are to be shorted. When en is 0, the signal only passes through the delay unit of the stage and does not pass back, as shown in fig. 1, when en [0:1] is 00, the signal flow is a broken line shown as 11; when en is 1, the signal is passed back through the delaycell of this stage, as shown in fig. 1, and when en [0:1] is 10, the signal flow is a broken line as shown by 12.
However, due to the delay circuit design problems of the prior art, glitches may be generated at the output terminal. Specifically, in fig. 1, when a is high and the input change of en <0> is 0 → 1, the change of the node H is 1 → 0, the change of the node I is 1 → 0, and the change of the node L is 0 → 1. The change of the node I is later than the change of the node L, so that when the node L and the node I are both 1, a low-level glitch is generated at the output terminal bo. The timing of node H, I, L and output bo is shown in FIG. 2. So that the circuit sensitive to the burr can not work normally after the delay circuit in the prior art is adopted.
Disclosure of Invention
The embodiment of the invention provides a delay circuit, a method, a delay chain and a chip, which are used for solving the problem that burrs are generated in the code changing process of the delay circuit.
In a first aspect, the present invention provides a delay circuit, comprising:
the signal receiving module is used for receiving an enable signal and obtaining a first output signal and a second output signal according to the enable signal;
the RS trigger module is used for receiving the first output signal and the second output signal and obtaining a third output signal and a fourth output signal according to the first output signal and the second output signal;
the burr eliminating module is used for receiving the third output signal, delaying the third output signal and outputting a fifth output signal;
a delay module, the delay module comprising: the delay circuit comprises a fourth output signal receiving end for receiving the fourth output signal, a fifth output signal receiving end for receiving the fifth output signal, a first-stage connection input end for receiving the first signal, a second-stage connection input end for receiving the second signal, a first-stage connection output end for outputting the delay output signal of the delay circuit, and a second-stage connection output end for outputting the circuit output signal of the delay circuit.
In a second aspect, the present invention provides a delay method applied to any of the above delay circuits, the method comprising:
receiving an enable signal, and obtaining a first output signal and a second output signal according to the enable signal;
obtaining a third output signal and a fourth output signal according to the first output signal and the second output signal;
outputting a fifth output signal after delaying the third output signal;
and outputting a delay output signal and a circuit output signal of the delay circuit according to the fourth output signal, the fifth output signal, the first signal and the second signal.
In a third aspect, an embodiment of the present invention provides a delay chain, where the delay chain includes any one of the delay circuits.
In a fourth aspect, an embodiment of the present invention provides a chip, where the chip includes any one of the delay circuits.
Compared with the prior art, the invention has the following advantages:
in the delay circuit provided in the embodiment of the present invention, after the enable signal is processed by the signal receiving module, the first output signal and the second output signal that are input by the RS trigger module are obtained, the third output signal and the fourth output signal are obtained through the trigger logic of the RS trigger module, and then the fifth output signal is obtained by delaying the third output signal by the glitch elimination module, so that the fifth output signal is delayed from the fourth output signal, and a phenomenon that the fifth output signal changes to a high level earlier than the fourth output signal is avoided, so that glitches are not generated in the delay module because the fifth output signal changes to a high level earlier than the fourth output signal, and the delay circuit in the embodiment of the present invention can be applied to any circuit that needs to be delayed.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.
Fig. 1 is a circuit diagram of a delay circuit provided in the prior art;
FIG. 2 is a timing diagram of a delay circuit provided in the prior art;
FIG. 3 is a circuit diagram of a delay circuit according to an embodiment of the present invention;
FIG. 4 is a detailed circuit diagram of a delay circuit according to an embodiment of the present invention;
fig. 5 is a flowchart illustrating steps of a delay method according to an embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Example one
The embodiment of the invention provides a delay circuit. Fig. 3 shows a circuit schematic diagram of the delay circuit provided by the embodiment of the invention.
As shown in fig. 3, the delay circuit may include:
the signal receiving module 100 is configured to receive an enable signal, and obtain a first output signal and a second output signal according to the enable signal. In a specific application, as shown in fig. 3, the signal receiving module 100 may include an enable signal receiving end 101, and the signal receiving module 100 may receive an enable signal by enabling the signal receiving end 101, where the enable signal may specifically be a high level signal or a low level signal. The second output signal may be consistent with the enable signal, that is, the enable signal is passed through in the signal receiving module 100 and then output as the second output signal.
And an RS triggering module 200, configured to receive the first output signal and the second output signal, and obtain a third output signal and a fourth output signal according to the first output signal and the second output signal. In a specific application, as shown in fig. 3, two signal output ends of the signal receiving module 100 may be respectively connected to two input ends of the RS triggering module 200, so that the RS triggering module 200 may receive the first output signal and the second output signal, and output a third output signal and a fourth output signal at two output ends of the RS triggering module 200 through the RS triggering logic. Wherein the fourth output signal may be directly output to the delay module 400, and the third output signal may be: the delay circuit receives a signal from low to high when the valid enable signal starts to work. It is understood that if the third output signal is directly coupled to the delay module 400, a glitch may occur in the delay module 400, such as occurring from low to high and then from high to low as in the prior art. Therefore, the third output signal is a signal that needs to be delayed, and specifically, the third output signal can be delayed by the spur cancellation module 300.
And the spur cancellation module 300 is configured to receive the third output signal, delay the third output signal, and output a fifth output signal. In a specific application, as shown in fig. 3, an input end of the spur cancellation module 300 may be connected to an end of the RS trigger module 200, where the end outputs the third output signal, so that the spur cancellation module 300 may receive the third output signal, perform delay processing on the third output signal, and output a fifth output signal at an output end of the spur cancellation module 300, where the fifth output signal is delayed compared to the fourth output signal.
The delay module 400 is configured to receive the fourth output signal, the fifth output signal, the first signal and the second signal, and output a delay output signal and a circuit output signal of the delay circuit. In a specific application, as shown in fig. 3, the delay module 400 further includes: a fourth output signal receiving terminal for receiving the fourth output signal, a fifth output signal receiving terminal for receiving the fifth output signal; a fifth output signal receiving terminal may be connected to the output terminal of the spur cancellation module 300, and a fourth output signal receiving terminal may be connected to the fourth output signal output terminal of the RS trigger module 200, so that the delay module 400 may receive the fourth output signal and the fifth output signal; the delay module 400 further comprises: a first stage input terminal 401 for receiving a first signal, a second stage input terminal 402 for receiving a second signal, a first stage output terminal 403 for outputting a delayed output signal of the delay circuit, and a second stage output terminal 404 for outputting a circuit output signal of the delay circuit.
In a specific application, when the delay circuit is used independently, the first signal may be a preset input signal, that is, an original signal to be delayed, and the first-stage connection input terminal 401 may be connected to the preset input signal; the delayed output signal output by the first cascade output terminal 403 may be used as a second signal, the first cascade output terminal 403 is connected to the second cascade input terminal 402, and the enable signal received by the signal receiving module 100 may be a control signal for controlling the delay circuit to implement a first-stage delay on the preset input signal.
When the delay circuit is connected to the delay chain, the delay chain may include a plurality of cascaded delay circuits, and then a first-stage connection input terminal of a first-stage delay circuit of the delay chain may receive a preset input signal, and a first-stage connection output terminal of a higher-stage delay circuit is connected to a first-stage connection input terminal of a lower-stage delay circuit, and a second-stage connection output terminal of the lower-stage delay circuit is connected to a second-stage connection input terminal of the higher-stage delay circuit; the first cascade output of the last delay circuit is connected to the second cascade input of the last delay circuit, and by providing an adaptive enable signal (control signal) to each delay circuit in the delay chain, a selectable delay of a predetermined input signal can be achieved, for example, one delay circuit delay can be selected in the delay chain, or a plurality of delay circuit delays can be selected in the delay chain.
In the embodiment of the present invention, the working process of the delay circuit in fig. 3 is as follows: when the delay circuit receives the enable signal, the enable signal is processed by the signal receiving module 100 to obtain a first output signal and a second output signal which are input by the RS trigger module 200, a third output signal and a fourth output signal are obtained through the trigger logic of the RS trigger module 200, and then the third output signal is delayed by the glitch elimination module 300 to obtain a fifth output signal, which is delayed from the fourth output signal, so that the occurrence of the phenomenon that the fifth output signal changes to a high level earlier than the fourth output signal is avoided, and glitches in the delay module 400 cannot occur because the fifth output signal changes to a high level earlier than the fourth output signal, so that the delay circuit of the embodiment of the present invention can be applied to any circuit requiring delay.
Preferably, as shown in fig. 4, a specific circuit diagram of a delay chain according to an embodiment of the present invention is shown, and as shown in fig. 4, the delay chain may include two delay circuits, in the delay circuit on the left:
the spur elimination module 300 includes:
a first stage NAND gate and a second stage NAND gate; two input ends of the first-stage NAND gate respectively receive the third output signal and a preset high-level signal; two input ends of the second-stage NAND gate respectively receive the output signal of the first-stage NAND gate and the preset high-level signal; and the output end of the second-stage NAND gate outputs the fifth output signal.
The signal receiving module 100 includes a not gate; the input end of the NOT gate is used for receiving the enabling signal; the output end of the NOT gate is connected with the first input end of the RS trigger module and is used for outputting a first output signal to the RS trigger module; and the input end of the NOT gate is connected with the second input end of the RS trigger module and is used for outputting a second output signal to the RS trigger module.
The delay module 400 includes a first nand gate, a second nand gate, and a third nand gate; two input ends of the first NAND gate respectively receive the fourth output signal and the first signal; the output end of the first NAND gate outputs a delay output signal of the delay circuit; two input ends of the second nand gate respectively receive the fifth output signal and the first signal; two input ends of the third NAND gate respectively receive the output signal of the second NAND gate and the second signal; and the output end of the third NAND gate outputs a circuit output signal of the delay circuit.
The RS trigger module 200 includes: a fourth NAND gate and a fifth NAND gate;
two input ends of the fourth NAND gate respectively receive the first output signal and the output signal of the fifth NAND gate; the output end of the fourth NAND gate outputs the third output signal; two input ends of the fifth NAND gate respectively receive the second output signal and the output signal of the fourth NAND gate; and the output end of the fifth NAND gate outputs the fourth output signal.
In the embodiment of the present invention, as shown in fig. 4, in the delay circuit on the left, the signal receiving module 100 may include an inverter N1, where N1 may be an inverter in a specific application; the RS flip-flop module 200 may include a nand gate N2 and a nand gate N3, where an output of N2 is one of inputs of N3, and an output of N3 is one of inputs of N2, thereby constituting the RS flip-flop module 200; the glitch removal module 300 may include nand gates N4 and N5, one of the inputs of N4 and N5 being both high, so that the outputs of N4 and N5 may be determined by the output of N2, and the delay module 400 may include nand gates N6, N7 and N8.
In a specific application, as shown in fig. 4, when the left delay circuit operates independently, the enable signal of the enable signal receiving terminal 101 may be connected to the input terminal of N1, and after inverting through N1, a signal inverted to the enable signal may be obtained, and the enable signal (the second output signal) and the signal inverted to the enable signal (the first output signal) are used as the inputs of the RS flip-flop module, specifically, as shown in fig. 4, the output terminal of N1 is connected to one of the input terminals of N2, the enable signal receiving terminal 101 is connected to one of the input terminals of N3, and through RS flip-flop logic of N2 and N3, the third output signal may be output at the output terminal of N2, and the fourth output signal may be output at the output terminal of N3; the output end of the N2 is connected with one input end of the N4, and the output end of the N4 is cascaded with one input end of the N5, so that the third output signal can realize two gate delays after passing through the N4 and the N5; an output end of N5 is connected to one of input ends of N7, another input end of N7 is a first-stage connection input end 401, a preset input signal is connected, an output end of N7 is connected to one of input ends of N8, another input end of N8 is a second-stage connection input end 402, an output end of N8 is a circuit signal output end 404 of the left delay circuit, an output end of N3 is connected to one of input ends of N6, another input end of N6 is the first-stage connection input end 401, a preset input signal is connected, and an output end of N6 is a delay signal output end 403 of the left delay circuit.
When the left delay circuit is connected to the delay chain as one of the delay circuits, as shown in fig. 4, the left delay circuit may be referred to as an upper stage delay circuit, and the right delay circuit may be referred to as a lower stage delay circuit. In the delay chain, the first cascade output end of a higher-level delay circuit is connected with the first cascade input end of a lower-level delay circuit, and the second cascade output end of the lower-level delay circuit is connected with the second cascade input end of the higher-level delay circuit.
In the right delay circuit of the embodiment of the present invention, which has the same or similar modules and connections as the left delay circuit, as shown in fig. 4, the right delay circuit may include an not gate N9, and nand gates N10, N11, N12, N13, N14, N15, and N16, signal inputs of the right delay circuit are connected to the input terminal of N9 and the input terminal of N11, an output terminal of N9 is connected to one input terminal of N10, another input terminal of N10 is connected to the output terminal of N11, another input terminal of N11 is connected to the output terminal of N10, an output terminal of N10 is further connected to one input terminal of N12, another input terminal of N12 is connected to a high level, an output terminal of N12 is connected to one input terminal of N13, another input terminal of N13 is connected to a high level, an output terminal of N13 is connected to one input terminal of N15, another input terminal of N15 is connected to the upper-stage signal output terminal of the delay circuit, the output end of N15 is connected with one input end of N16, the other input end of N16 is connected with the circuit signal output end of the lower-level delay circuit, the output end of N16 is the circuit signal output end of the right-side delay circuit, the output end of N11 is connected with one input end of N14, the other input end of N14 is connected with the delay signal output end of the upper-level delay circuit, and the output end of N14 is the delay signal output end of the right-side delay circuit.
In a specific application, taking the right delay circuit as a final stage delay circuit as an example, the first cascade output terminal of the right delay circuit is connected to the second cascade input terminal of the right delay circuit, the delay chain includes two delay circuits as shown in fig. 4, the output terminal of N6 is connected to one of the input terminals of N14 and one of the input terminals of N15, the output terminal of N16 is connected to one of the input terminals of N8, the output terminal of N14 is connected to one of the input terminals of N16, and the output of N8 is an output signal of the delay chain.
In conjunction with eight nodes labeled a, B, C, D, E, F, seln, selp in fig. 4, the delay chain operation process of fig. 4 is illustrated as follows:
as shown in fig. 4, in the delay circuit according to the embodiment of the present invention, when EN is 0, the fourth output signal at the output terminal of N3 is high, and the output of N6 is determined by the signal received by the first stage input terminal 401, so that the signal received by the first stage input terminal 401 can be transmitted to the next stage; when EN is 1, the third output signal at the output end of N2 is at high level, so that the fourth output signal at the output end of N3 is at low level, and no matter what signal the first-stage connection terminal 401 receives, the output of N6 is at high level, and therefore, the signal received by the first-stage connection terminal 401 cannot be transmitted to the next stage; that is, in the delay circuit according to the embodiment of the present invention, the enable signal EN is active at a low level.
When the left delay circuit needs to be connected into the circuit, EN of the left delay circuit is changed from 1 to 0, the seln point passes through the delay of the one-stage NAND gate and is changed from 0 to 1, and the NAND gate which transmits to the next stage is opened. The signal passes to node F through 3 stages of nand gates, the 3 stages being the nand gates after seln, and two nand gates corresponding to the paths of the E nodes of the right delay circuit, i.e., N6, N15, N16. That is, the delay of 4 nand gates in total is required from the time EN changes from 1 to 0 to the time node F changes, and the time node F changes from 1 to 0 or keeps 1.
From EN changing from 1 to 0 to node selp changing to 1, four nand gate delays are passed, specifically, EN changing from 1 to 0, the output of N1 is 1, the change of N2 is determined by the output of N3, EN changing from 1 to 0, the output of N3 changing from 1 to 0, and N3 changing first, so the 4 nand gates are N2, N3, N4, N5. So, changing from EN to node E changes node E from 0 to 1 or remains 1 through a total of 5 nand gates' delays N2, N3, N4, N5 and N7.
Specifically, the level at point a coincides with the enable signal EN, and the level at point D coincides with the point seln. When EN is 1, inversion B is 0, D is 0, C is 1 via N1; when EN changes from 1 to 0, B changes from 0 to 1, the output of N3 changes from 0 to 1 at point D first, then the output of N2 changes from 1 to 0 at point C, and selp changes from 1 to 0. That is, when EN changes from 1 to 0, selp changes from 1 to 0 and seln changes from 0 to 1. When EN changes from 1 to 0, if the input of the upper stage delay signal receiving terminal 401 is high, F point is equal to the output of N6 and is changed from 1 to 0, and E point is equal to the output of N7 and is changed from 0 to 1; when EN changes from 1 to 0, F is equal to the output of N6 and is a hold 1, and E is equal to the output of N7 and is a hold 1, when the input to the upper stage delay signal receiving terminal 401 is low. Moreover, the change from EN to node F requires a delay of 4 nand gates, and node F changes from 1 to 0 or remains 1.
It can be understood that, even if the node F changes from 1 to 0 and the node E changes from 0 to 1, no glitch will be generated because, in the embodiment of the present invention, after EN changes, the point F changes through 4 nand gate delays and the point E changes through 5 nand gate delays, so that the node F changes from 1 to 0 first.
Similarly, when the left delay circuit does not need to be accessed to the circuit, EN changes from 0 to 1, and node selp changes from 0 to 1 through the delay of the 1-stage not gate plus the 3-stage nand gate. The node seln changes from 1 to 0 through the delay of the 1-stage not gate and the 2-stage not gate. Therefore, when the node E changes from EN to E, the node E changes from 1 to 0 or keeps 1 after the delay of 4 NAND gates and 1-stage NOT gates; the change from EN to F requires 5 NAND gates plus 1 NOT gate delay, the node F changes from 0 to 1 or keeps 1, and the high-low signal also occurs first, so no glitch is generated.
The enable signal EN can be generated by a control module in specific application, and the enable signal of at least one delay circuit is controlled to be at a high level or a low level according to the requirements of actual application scenes, so that the access or the closing of the delay circuit is controlled, and the effect of flexibly controlling the delay time or the phase is achieved.
In specific application, the not gate and the nand gate of the embodiment of the invention can be set up through logic control, or through circuit components such as a diode, a triode, a transistor and the like, and the embodiment of the invention is not particularly limited to this.
In summary, in the embodiments of the present invention, the RS flip-flop module and the glitch elimination module are adopted in the delay circuit, and the glitch elimination module causes signals in two input ends to occur first from high to low and then from low to high in the nand gate that outputs signals from the output unit of the delay module, thereby preventing the glitch from occurring. In addition, the delay circuit of the embodiment of the invention is a glitch-free delay chain which can be used at high frequency and low frequency, and the occupied area of the delay circuit is far smaller than that of the delay chain in the prior art when the delay circuit is used for a chip.
Example two
Referring to fig. 5, a flowchart of steps of a delay method according to an embodiment of the present invention is shown, where the delay method may be applied to any of the delay circuits, and the method specifically includes:
step 501: receiving an enable signal, and obtaining a first output signal and a second output signal according to the enable signal;
step 502: obtaining a third output signal and a fourth output signal according to the first output signal and the second output signal;
step 503: outputting a fifth output signal after delaying the third output signal;
step 504: and outputting a delay output signal and a circuit output signal of the delay circuit according to the fourth output signal, the fifth output signal, the first signal and the second signal.
In addition, an embodiment of the present invention further provides a delay chain, which includes a plurality of the above delay circuits. Wherein the plurality of delay circuits are connected in cascade; the first cascade output end of the upper stage delay circuit is connected with the first cascade input end of the lower stage delay circuit; the second cascade output end of the lower stage delay circuit is connected with the second cascade input end of the upper stage delay circuit; the first-stage connection input end of the first-stage delay circuit is used for receiving a preset input signal; and the first cascade output end of the final-stage delay circuit is connected with the second cascade input end of the final-stage delay circuit.
In addition, the embodiment of the invention also provides a chip which comprises any one of the delay circuits.
Preferably, the chip further comprises: and the enabling signal generating circuit is used for generating the enabling signal.
In summary, in the delay circuit provided in the embodiment of the present invention, after the enable signal is processed by the signal receiving module, the first output signal and the second output signal that are input by the RS trigger module are obtained, the third output signal and the fourth output signal are obtained through the trigger logic of the RS trigger module, and then the fifth output signal is obtained by delaying the third output signal by the glitch elimination module, so that the fifth output signal is delayed from the fourth output signal, and a phenomenon that the fifth output signal changes to a high level earlier than the fourth output signal is avoided, so that glitches are not generated in the delay module because the fifth output signal changes to a high level earlier than the fourth output signal, and the delay circuit in the embodiment of the present invention can be applied to any circuit that needs to be delayed.
It should be noted that, similar or related descriptions are already provided in the implementation process of the second embodiment, and are not repeated here to avoid repetition.
It should be understood that the above description is only exemplary of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present invention, and all such changes or substitutions are intended to be covered by the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
It should be noted that modifications and adaptations may occur to those skilled in the art without departing from the principles of the present invention and should be considered within the scope of the present invention.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.
The delay circuit, the method, the delay chain and the chip provided by the invention are described in detail, and the principle and the implementation mode of the invention are explained by applying specific examples, and the description of the embodiments is only used for helping to understand the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (10)
1. A delay circuit, characterized in that the delay circuit comprises:
the signal receiving module is used for receiving an enable signal and obtaining a first output signal and a second output signal according to the enable signal;
the RS trigger module is used for receiving the first output signal and the second output signal and obtaining a third output signal and a fourth output signal according to the first output signal and the second output signal;
the burr eliminating module is used for receiving the third output signal, delaying the third output signal and outputting a fifth output signal;
a delay module, the delay module comprising: the delay circuit comprises a fourth output signal receiving end for receiving the fourth output signal, a fifth output signal receiving end for receiving the fifth output signal, a first-stage connection input end for receiving the first signal, a second-stage connection input end for receiving the second signal, a first-stage connection output end for outputting the delay output signal of the delay circuit, and a second-stage connection output end for outputting the circuit output signal of the delay circuit.
2. The delay circuit of claim 1, wherein the spur cancellation module comprises:
a first stage NAND gate and a second stage NAND gate;
two input ends of the first-stage NAND gate respectively receive the third output signal and a preset high-level signal;
two input ends of the second-stage NAND gate respectively receive the output signal of the first-stage NAND gate and the preset high-level signal;
and the output end of the second-stage NAND gate outputs the fifth output signal.
3. The delay circuit of claim 2, wherein the signal receiving module comprises a not gate;
the input end of the NOT gate is used for receiving the enabling signal;
the output end of the NOT gate is connected with the first input end of the RS trigger module and is used for outputting the first output signal to the RS trigger module;
and the input end of the NOT gate is connected with the second input end of the RS trigger module and is used for outputting the second output signal to the RS trigger module.
4. The delay circuit of claim 2, wherein the delay module comprises a first nand gate, a second nand gate, a third nand gate;
two input ends of the first NAND gate respectively receive the fourth output signal and the first signal;
the output end of the first NAND gate outputs a delay output signal of the delay circuit;
two input ends of the second nand gate respectively receive the fifth output signal and the first signal;
two input ends of the third NAND gate respectively receive the output signal of the second NAND gate and the second signal;
and the output end of the third NAND gate outputs a circuit output signal of the delay circuit.
5. The delay circuit of any one of claims 1 to 4, wherein the RS trigger module comprises: a fourth NAND gate and a fifth NAND gate;
two input ends of the fourth NAND gate respectively receive the first output signal and the output signal of the fifth NAND gate;
the output end of the fourth NAND gate outputs the third output signal;
two input ends of the fifth NAND gate respectively receive the second output signal and the output signal of the fourth NAND gate;
and the output end of the fifth NAND gate outputs the fourth output signal.
6. The delay circuit of claim 3, wherein the NOT gate comprises an inverter.
7. A delay method applied to the delay circuit according to any one of claims 1 to 5, the method comprising:
receiving an enable signal, and obtaining a first output signal and a second output signal according to the enable signal;
obtaining a third output signal and a fourth output signal according to the first output signal and the second output signal;
outputting a fifth output signal after delaying the third output signal;
and outputting the delay output signal and the circuit output signal of the delay circuit according to the fourth output signal, the fifth output signal, the first signal and the second signal.
8. A delay chain comprising a plurality of delay circuits as claimed in any one of claims 1 to 6; the plurality of delay circuits are connected in cascade;
the first cascade output end of the upper stage delay circuit is connected with the first cascade input end of the lower stage delay circuit; and is
The second cascade output end of the lower stage delay circuit is connected with the second cascade input end of the upper stage delay circuit;
the first-stage connection input end of the first-stage delay circuit is used for receiving a preset input signal;
and the first cascade output end of the final-stage delay circuit is connected with the second cascade input end of the final-stage delay circuit.
9. A chip comprising the delay circuit of any one of claims 1 to 6.
10. The chip of claim 9, wherein the chip further comprises: and the enabling signal generating circuit is used for generating the enabling signal.
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