CN111355487B - A clock generating circuit and a clock generator - Google Patents
A clock generating circuit and a clock generator Download PDFInfo
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- CN111355487B CN111355487B CN202010161599.2A CN202010161599A CN111355487B CN 111355487 B CN111355487 B CN 111355487B CN 202010161599 A CN202010161599 A CN 202010161599A CN 111355487 B CN111355487 B CN 111355487B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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Abstract
本发明提供一种时钟生成电路和生成器，首先对第一信号按照参考信号进行相位采样，再进行低通滤波，提取出低频的时钟相位信号；同时对第二信号按照参考信号进行相位采样，再进行带通滤波，提取出中频的时钟相位信号。然后叠加合成低通滤波器输出的时钟相位信号和带通滤波器输出的时钟相位信号，再通过锁相环对合成后的信号进行平滑处理，输出缓变的时钟信号。最后参照长期频率稳定信号对锁相环输出的时钟信号进行相位调整，通过增减相位使得其相位与长期频率稳定信号的相位一致，从而输出高稳时钟信号。本实施例提供的电路实现简单，需要增加元件较少，硬件体积小，成本低。
The present invention provides a clock generation circuit and generator. First, the first signal is phase sampled according to a reference signal, and then low-pass filtered to extract a low-frequency clock phase signal; at the same time, the second signal is phase sampled according to the reference signal, and then band-pass filtered to extract an intermediate-frequency clock phase signal. Then, the clock phase signal output by the low-pass filter and the clock phase signal output by the band-pass filter are superimposed and synthesized, and then the synthesized signal is smoothed by a phase-locked loop to output a slowly varying clock signal. Finally, the phase of the clock signal output by the phase-locked loop is adjusted with reference to a long-term frequency stable signal, and its phase is made consistent with the phase of the long-term frequency stable signal by increasing or decreasing the phase, thereby outputting a high-stability clock signal. The circuit provided in this embodiment is simple to implement, requires fewer components to be added, has a small hardware volume, and is low in cost.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a clock generation circuit and a clock generator.
Background
The 5G communication has a faster data transmission rate, a lower response delay and a higher throughput, which are one of the development trends of future network communication, and currently operators and equipment providers are deploying 5G communication networks with tight drums and are gradually commercialized. In a 5G communication network, accurate and stable clocks are required in many links to ensure efficient and high-quality communication of the network.
In the prior art, the high-stability clock is mainly generated by (1) directly generating through an atomic clock, and the realization mode has the highest stability, but is large in size and high in cost. (2) Long-term frequency stability is provided by the GPS signal and short-term frequency stability and low jitter is provided by the OCXO signal. This implementation is highly stable, but is bulky and costly.
Accordingly, there is a need for a low cost clock generator for those skilled in the art.
Disclosure of Invention
In view of the above, the embodiments of the present invention provide a clock generating circuit and a clock generator with low cost.
In order to achieve the above object, the embodiment of the present invention provides the following technical solutions:
a clock generation circuit, comprising:
The device comprises a first phase sampler, a second phase sampler, a low-pass filter, a band-pass filter, a synthesized signal generator, a phase-locked loop and a phase adjuster;
The input end of the first phase sampler is used for acquiring a first signal with preset frequency, and phase sampling is carried out on the first signal based on a reference signal;
The input end of the second phase sampler is used for acquiring a second signal with preset frequency, and the second signal is subjected to phase sampling based on a reference signal;
The input end of the low-pass filter is connected with the output end of the first phase sampler and is used for carrying out low-pass filtering on the sampling signal of the first phase sampler;
The input end of the band-pass filter is connected with the output end of the second phase sampler and is used for carrying out band-pass filtering on the sampling signal of the second phase sampler;
The input end of the synthesized signal generator is connected with the output end of the low-pass filter and the output end of the band-pass filter, and is used for integrating the low-pass filtered phase sampling signal and the band-pass filtered phase sampling signal to obtain a clock phase signal;
The input end of the phase-locked loop is connected with the output end of the synthesized signal generator and is used for acquiring and processing the clock phase signal and outputting a clock signal;
the first input end of the phase adjuster is used for acquiring the first signal, and the second input end of the phase adjuster is connected with the output end of the phase-locked loop and used for adjusting the phase of the clock signal output by the phase-locked loop based on the phase of the first signal so that the phase of the clock signal output by the phase-locked loop is consistent with the phase of the first signal.
Optionally, in the clock generating circuit, the first signal is a GPS signal, the second signal is a TCXO signal, and the reference signal is an XO signal.
Optionally, in the clock generating circuit, the reference signal is a reference signal with a jitter value smaller than a preset value.
Optionally, in the clock generating circuit, the preset value is not greater than 100fs RMS.
A clock generator, a clock generation circuit as claimed in any one of the preceding claims.
According to the scheme provided by the embodiment of the invention, the clock generation circuit firstly performs phase sampling on the first signal according to the reference signal, then performs low-pass filtering to extract a low-frequency clock phase signal, and simultaneously performs phase sampling on the second signal according to the reference signal, and then performs band-pass filtering to extract an intermediate-frequency clock phase signal. And then, superposing and synthesizing the clock phase signal output by the low-pass filter and the clock phase signal output by the band-pass filter, and smoothing the synthesized signal through a phase-locked loop to output a slowly-changed clock signal. Finally, the phase of the clock signal output by the phase-locked loop is adjusted by referring to the long-term frequency stable signal, and the phase of the clock signal is consistent with the phase of the long-term frequency stable signal by increasing or decreasing the phase, so that a high-stability clock signal is output. The circuit provided by the embodiment is simple to realize, fewer elements need to be added, the hardware size is small, and the cost is low.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a clock generating circuit according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to the appended drawings.
Example 1:
referring to fig. 1, fig. 1 is a schematic diagram of a clock generating circuit according to an embodiment of the present application.
In the technical solution disclosed in the embodiment of the present application, the clock generation circuit described with reference to fig. 1 includes:
A first phase sampler 100, a second phase sampler 200, a low-pass filter 300, a band-pass filter 400, a composite signal generator 500, a phase-locked loop 600 and a phase adjuster 700;
The input end of the first phase sampler is configured to obtain a first signal with a preset frequency, and perform phase sampling on the first signal based on a reference signal to obtain a signal V1, that is, when the first phase sampler detects that a set time arrives in each period of the reference signal, the first signal is sampled, where the set time may refer to a rising edge, a falling edge or other time of the reference signal, and in this scheme, the first signal may refer to a long-term frequency stable signal, and a type of the long-term frequency stable signal may be selected by a user according to a user requirement, for example, in this scheme, the first signal may be a GPS (Global Positioning System ) signal. The reference signal may be a low jitter signal, for example, an XO signal (oscillation signal) having a jitter value smaller than a preset value, where the magnitude of the preset value may be selected according to the user's requirement, for example, in this embodiment, the preset value is not greater than 100fs RMS. .
The input end of the second phase sampler is configured to obtain a second signal with a preset frequency, and phase sample the second signal based on a reference signal to obtain a signal V 3, that is, when the second phase sampler detects that a set time arrives in each period of the reference signal, the second signal is sampled, where the set time may refer to a rising edge, a falling edge or other time of the reference signal, and in this scheme, the second signal may refer to a short-term frequency stable signal, where a type of the second signal may be selected by a user according to a user requirement, for example, in this scheme, the second signal may be a TCXO (Temperature Compensate X' al) Oscillator, and a temperature compensated quartz crystal resonator) signal.
The input end of the low-pass filter 300 is connected to the output end of the first phase sampler 100, and is configured to perform low-pass filtering on the sampling signal V 1 of the first phase sampler 100 to obtain a signal V 2, that is, the first phase collector sends the collected first signal to the low-pass filter 300, the low-pass filter 300 performs low-pass filtering on the sampling signal and then outputs a signal V 2, and the V2 is a low-frequency clock phase signal;
The input end of the band-pass filter 400 is connected to the output end of the second phase sampler 200, and is configured to band-pass filter the sampled signal of the second phase sampler 200, that is, the second phase sampler 200 sends the collected second signal to the band-pass filter 400, the band-pass filter 400 band-pass filters the sampled signal to output a signal V 4, and V 4 is an intermediate frequency clock phase signal.
The input end of the synthesized signal generator 500 is connected to the output end of the low-pass filter 300 and the output end of the band-pass filter 400, and is configured to integrate the low-pass filtered phase sampling signal and the band-pass filtered phase sampling signal to obtain a clock phase signal V 5, that is, after the synthesized signal generator obtains the low-frequency clock phase signal V 2 and the intermediate-frequency clock phase signal V 4, the synthesized signal generator superimposes the two signals and outputs a clock phase signal V 5;
The input end of the phase-locked loop 600 is connected to the output end of the synthesized signal generator 500, and is used for obtaining and processing the clock phase signal, that is, after the clock phase signal V 5 is smoothed, a slowly varying clock signal V 6 is output;
The first input end of the phase adjuster 700 is configured to obtain the first signal, the second input end of the phase adjuster is connected to the output end of the phase-locked loop, and is configured to adjust the phase of the clock signal output by the phase-locked loop based on the phase of the first signal, so that the phase of the clock signal output by the phase-locked loop is consistent with the phase of the first signal, and output an adjusted clock signal, and the adjusted clock signal is used as a high-stability clock signal.
It will be appreciated that in the above scheme, signal V 2 is a low frequency, long term frequency stable, low jitter clock phase signal and signal V 4 is an intermediate frequency, short term frequency stable, low jitter clock phase signal. V 2 and V 4 are superimposed by the synthetic signal generator 500 such that the synthesized clock signal V 5 is a low intermediate frequency, long and short term frequency stable, low jitter clock phase signal.
The GPS signal is used as a first signal to generate the high-stability clock signal so as to ensure the long-term frequency stability of the high-stability clock signal, the TCXO signal is used as a second signal to generate the high-stability clock signal so as to ensure the short-term frequency stability of the high-stability clock signal, and the high-stability clock signal is generated through the XO signal with low jitter so as to ensure that the generated clock signal has both the long-term frequency stability and the short-term frequency stability and has high stability.
The clock generation circuit provided by the embodiment firstly performs phase sampling on a long-term frequency stable signal GPS signal according to a reference signal, then performs low-pass filtering to extract a low-frequency clock phase signal, and simultaneously performs phase sampling on a short-term frequency stable signal TCXO signal according to the reference signal, and then performs band-pass filtering to extract an intermediate-frequency clock phase signal. And then, superposing and synthesizing the clock phase signal output by the low-pass filter and the clock phase signal output by the band-pass filter, and smoothing the synthesized signal through a phase-locked loop to output a slowly-changed clock signal. Finally, the phase of the clock signal output by the phase-locked loop is adjusted by referring to the long-term frequency stable signal, and the phase of the clock signal is consistent with the phase of the long-term frequency stable signal by increasing or decreasing the phase, so that a high-stability clock signal is output. The circuit provided by the embodiment is simple to realize, fewer elements need to be added, the hardware size is small, and the cost is low.
Corresponding to the circuit, the application also discloses a clock generator, which can be applied with the clock generating circuit according to any one of the embodiments of the application.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (5)
1. A clock generation circuit, comprising:
The device comprises a first phase sampler, a second phase sampler, a low-pass filter, a band-pass filter, a synthesized signal generator, a phase-locked loop and a phase adjuster;
The input end of the first phase sampler is used for acquiring a first signal with preset frequency, and phase sampling is carried out on the first signal based on a reference signal;
The input end of the second phase sampler is used for acquiring a second signal with preset frequency, and the second signal is subjected to phase sampling based on a reference signal;
The input end of the low-pass filter is connected with the output end of the first phase sampler and is used for carrying out low-pass filtering on the sampling signal of the first phase sampler;
The input end of the band-pass filter is connected with the output end of the second phase sampler and is used for carrying out band-pass filtering on the sampling signal of the second phase sampler;
The input end of the synthesized signal generator is connected with the output end of the low-pass filter and the output end of the band-pass filter, and is used for integrating the low-pass filtered phase sampling signal and the band-pass filtered phase sampling signal to obtain a clock phase signal;
The input end of the phase-locked loop is connected with the output end of the synthesized signal generator and is used for acquiring and processing the clock phase signal and outputting a clock signal;
The first input end of the phase adjuster is used for acquiring the first signal, the second input end of the phase adjuster is connected with the output end of the phase-locked loop and is used for adjusting the phase of the clock signal output by the phase-locked loop based on the phase of the first signal so that the phase of the clock signal output by the phase-locked loop is consistent with the phase of the first signal;
the first signal is a GPS signal, and the second signal is a TCXO signal.
2. The clock generation circuit of claim 1, comprising:
the reference signal is an XO signal.
3. The clock generation circuit of claim 1, wherein the reference signal is a reference signal having a jitter value less than a preset value.
4. The clock generation circuit of claim 1, wherein the preset value is not greater than 100fs RMS.
5. A clock generator comprising the clock generation circuit of any one of claims 1-4.
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| AUPR048500A0 (en) * | 2000-10-02 | 2000-10-26 | Nec Australia Pty Ltd | Radio frequency communications |
| US8446223B2 (en) * | 2009-05-22 | 2013-05-21 | CSR Technology, Inc. | Systems and methods for calibrating real time clock |
| JP5434301B2 (en) * | 2009-06-26 | 2014-03-05 | ソニー株式会社 | Signal receiving apparatus, signal receiving apparatus control method, and computer program |
| CN102780555B (en) * | 2011-05-13 | 2017-09-29 | 中兴通讯股份有限公司 | Clock synchronizing method and device in communication system |
| CN102315927A (en) * | 2011-06-30 | 2012-01-11 | 大唐移动通信设备有限公司 | Clock synchronization device and method |
| CN107026615B (en) * | 2017-03-07 | 2020-05-19 | 四川海格恒通专网科技有限公司 | Two-point modulation circuit and working method thereof |
| CN109768798B (en) * | 2017-11-10 | 2023-09-19 | 新港海岸(北京)科技有限公司 | System and method for maintaining low jitter low temperature drift clock in fault-preserving operation |
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