[ background of the invention ]
Organic Light Emitting Diode (OLED) is the mainstream technology of displays such as mobile phones, televisions, and computers. Compared with the traditional liquid crystal display, the OLED has the advantages of low energy consumption, low cost, self-luminescence, wide viewing angle, high corresponding speed and the like. Therefore, OLEDs are becoming mainstream display technologies.
Since OLEDs are current driven, a stable current is required to control their light emission. The driving current of the OLED is unstable due to manufacturing process limitations, device aging, and circuit design. The driving current of the OLED is determined by the power voltage and the data voltage, and when the power voltage is large, a large voltage drop occurs on a signal line for transmitting the power voltage, which causes the driving current to be unstable, thereby causing non-uniformity of brightness. Taking a mainstream driving circuit of an OLED as an example, a conventional mainstream driving circuit is 7T1C, and when a voltage drop of a power supply voltage on a signal line for transmitting the power supply voltage is 0.3V, a variation of a driving current is reduced by 70%.
[ application contents ]
In view of the above, embodiments of the present disclosure provide a pixel driving circuit, an organic light emitting display panel and a display device to solve the above problems.
In a first aspect, an embodiment of the present application provides a pixel driving circuit, including: the light-emitting display device comprises a light-emitting display module for performing light-emitting display and a light-emitting driving module for generating light-emitting driving current. The light-emitting driving module comprises a first control end, a first input end connected with a power supply voltage signal line and a first output end connected with the light-emitting display module. The pixel driving circuit further comprises a first initialization module for initializing the first control end, a first capacitor, a power supply voltage writing module for writing power supply voltage into the first control end, and a light-emitting voltage writing module for storing data voltage into the first capacitor. The first initialization module is electrically connected with the first control end. The first capacitor comprises a first polar plate and a second polar plate, and the first polar plate is electrically connected with the first control end. The power voltage writing module comprises a second input end and a second output end, the second input end is electrically connected with the first output end, and the second output end is electrically connected with the first polar plate. The luminous voltage writing module is connected with the second plate.
In one implementation manner of the first aspect, the light emitting driving module includes a first transistor, a gate of the first transistor is connected to the first control terminal, a source of the first transistor is connected to the first input terminal, and a drain of the first transistor is connected to the first output terminal.
In one implementation manner of the first aspect, the first initialization module includes a second transistor, a source of the second transistor is connected to the initial signal line, and a drain of the second transistor is connected to the first control terminal. In the initialization stage, the second transistor is turned on, the initial signal line transmits the reference voltage, and the second transistor transmits the reference voltage to the first control terminal.
In one implementation form of the first aspect, the second transistor includes a metal oxide active layer.
In one implementation form of the first aspect, the power supply voltage writing module includes a third transistor, a source of the third transistor is connected to the second input terminal, and a drain of the third transistor is connected to the second output terminal. In the stage of storing the power supply voltage, the third transistor is turned on, and the third transistor writes the power supply voltage into the first control end.
In one implementation form of the first aspect, the third transistor includes a metal oxide active layer.
In one implementation manner of the first aspect, the light emitting voltage writing module includes a fourth transistor, a source of the fourth transistor is connected to the data voltage line, and a drain of the fourth transistor is connected to the second plate. In the power voltage storage phase, the fourth transistor is turned on, the data voltage line transfers the data voltage, and the fourth transistor transfers the data voltage to the second plate. In a data signal writing phase, the fourth transistor is turned on, the data voltage line transmits the reference voltage, and the fourth transistor transmits the reference voltage to the second plate.
In one implementation manner of the first aspect, the light emitting display module includes a fifth transistor and an organic light emitting diode, a source of the fifth transistor is connected to the first output terminal, and a drain of the fifth transistor is connected to an anode of the organic light emitting diode. In the light emitting stage, the fifth transistor is turned on, and the fifth transistor transmits a light emitting driving current to the anode of the organic light emitting diode.
In one implementation manner of the first aspect, the pixel driving circuit further includes a second initialization module, where the second initialization module includes a sixth transistor, a source of the sixth transistor is connected to the initial signal line, and a drain of the sixth transistor is connected to an anode of the organic light emitting diode. In the initialization phase, the sixth transistor is turned on, and the sixth transistor transmits the reference voltage to the anode of the organic light emitting diode.
In one implementation of the first aspect, the initial signal line is multiplexed with the data voltage line.
In an implementation manner of the first aspect, the pixel driving circuit further includes a second capacitor, where the second capacitor includes a third plate and a fourth plate, the third plate is connected to the power supply voltage signal line, and the fourth plate is connected to the second plate.
In a second aspect, an embodiment of the present application provides an organic light emitting display panel, including the pixel driving circuit provided in the first aspect, where the pixel driving circuit is arranged in one-to-one correspondence with the pixel units.
In a third aspect, embodiments of the present application provide an organic light emitting display device including the organic light emitting display panel as provided in the second aspect.
The pixel drive circuit, the organic light-emitting display panel and the organic light-emitting display device eliminate the influence of the voltage drop of the power voltage on the power voltage signal line on the light-emitting drive current and the influence of the threshold voltage of the drive transistor on the light-emitting drive current, so that the pixel drive circuit has stable light-emitting drive current, and the display effect is ensured.
[ detailed description ] embodiments
For better understanding of the technical solutions of the present application, the following detailed descriptions of the embodiments of the present application are provided with reference to the accompanying drawings.
It should be understood that the embodiments described are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the examples of this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
In the description herein, it is to be understood that the terms "substantially", "approximately", "about", "substantially", and the like, as used in the claims and the examples herein, are intended to be generally accepted as not being precise, within the scope of reasonable process operation or tolerance.
It should be understood that although the terms first, second, third, etc. may be used to describe transistors in the embodiments of the present application, the transistors should not be limited to these terms. These terms are only used to distinguish transistors from one another. For example, the first transistor may also be referred to as a second transistor, and similarly, the second transistor may also be referred to as a first transistor without departing from the scope of embodiments of the present application.
The applicant provides a solution to the problems of the prior art through intensive research.
Fig. 1 is a schematic diagram of a pixel driving circuit according to an embodiment of the present disclosure, and as shown IN fig. 1, the pixel driving circuit according to the embodiment of the present disclosure includes a light emitting display module 00 for performing light emitting display and a light emitting driving module 01 for generating a light emitting driving current, where the light emitting driving module 01 includes a first control terminal CR1, a first input terminal IN1 and a first output terminal OUT1, the first input terminal IN1 is connected to a power voltage signal line PVDD, and the first output terminal OUT1 is connected to the light emitting display module 00. The light emitting driving module 01 generates a light emitting driving current at a light emitting stage and transmits the light emitting driving current to the light emitting display module 00 to drive the light emitting display module 00 to operate so as to perform light emitting display.
The pixel driving circuit provided by the embodiment of the application further includes a first initialization module 02, and the first initialization module 02 is electrically connected to the first control terminal CR1 of the light-emitting driving module 01, and is configured to initialize the first control terminal CR1 of the light-emitting driving module 01.
The pixel driving circuit provided by the embodiment of the application further includes a first capacitor C1, and the first capacitor C1 includes a first plate and a second plate, wherein the first plate is electrically connected to the first control terminal CR1 of the light emitting driving module 01.
The pixel driving circuit provided IN the embodiment of the application further includes a power voltage writing module 03, the power voltage writing module 03 includes a second input terminal IN2 and a second output terminal OUT2, the second input terminal IN2 is electrically connected to the first output terminal OUT1, and the second output terminal OUT2 is electrically connected to the first plate of the first capacitor C1. The power voltage writing module 03 is configured to write a power voltage into the first control terminal CR1 of the light emitting driving module 01, specifically, the power voltage on the power voltage signal line PVDD is written into the first control terminal CR1 of the light emitting driving module 01 through the power voltage writing module 03.
The pixel driving circuit provided by the embodiment of the application further includes a light-emitting voltage writing module 04, and the light-emitting voltage writing module 04 is connected to the second plate of the first capacitor C1, and is configured to store the data voltage in the first capacitor C1.
That is, in the pixel driving circuit provided in the embodiment of the present application, the first capacitor C1 is disposed at the first control terminal CR1 of the light emitting driving module 01, and specifically, the first plate of the first capacitor C1 is connected to the first control terminal CR1 of the light emitting driving module 01. In addition, the second output terminal OUT2 of the power voltage writing module 01 is connected to the first control terminal CR1 of the light emitting driving module 01, and the first plate of the first capacitor C1 is connected to the second output terminal OUT2 of the power voltage writing module 03. That is, the first plate of the first capacitor C1 is connected to the second output terminal OUT2 of the power voltage writing module 03, and the second plate of the first capacitor C1 is connected to the light-emitting voltage writing module 04.
Before the light emitting period, the first capacitor C1 may store the power voltage and the data voltage; IN the light emitting phase, the first input terminal IN1 of the light emitting driving module 01 receives a power voltage. The light-emitting driving current generated by the light-emitting driving module 01 is controlled by the voltage difference between the first input terminal IN1 and the first control terminal CR1, and since the first capacitor C1 stores the power voltage before the light-emitting stage, the voltage difference between the first input terminal IN1 and the first control terminal CR1 of the light-emitting driving module 01 does not contain the power voltage during the light-emitting stage, thereby eliminating the influence of the power voltage on the light-emitting driving current, ensuring that the light-emitting display module can accept the stable light-emitting driving current, and improving the stability of the display brightness.
Referring to fig. 2, fig. 2 is a schematic diagram of another pixel driving circuit according to an embodiment of the present disclosure, as shown IN fig. 2, the light emitting driving module 01 includes a first transistor T1, a gate of the first transistor T1 is connected to a first control terminal CR1, a source of the first transistor T1 is connected to a first input terminal IN1, and a drain of the first transistor T1 is connected to a first output terminal OUT 1.
The first initialization module 02 includes a second transistor T2, a source of the second transistor T2 is connected to the initial signal line REF, and a drain of the second transistor T2 is connected to the first control terminal CR1 of the light emitting driving module 01. In the initialization phase, the second transistor T2 is turned on, the initial signal line REF transmits the reference voltage Vref, and the second transistor T2 transmits the reference voltage Vref to the first control terminal CR1 of the light emitting driving module 01. That is, the source of the second transistor T2 is connected to the initial signal line REF, and the drain of the second transistor T2 is connected to the gate of the first transistor T1. In the initialization stage, the second transistor T2 is turned on, receives the reference voltage Vref transmitted by the initial signal line REF, and transmits the reference voltage Vref to the gate of the first transistor T1, thereby initializing the second transistor T2.
The power voltage writing module 03 includes a third transistor T3, a source of the third transistor T3 is connected to the second input terminal IN2, and a drain of the third transistor T3 is connected to the second output terminal OUT 2. In the power voltage storing phase, the third transistor T3 is turned on, and the third transistor T3 writes the power voltage into the first control terminal CR1 of the light emitting driving module 01. That is, the source of the third transistor T3 is connected to the first output terminal OUT1 of the first transistor T1, and the drain of the third transistor T3 is connected to the first control terminal CR1 of the first transistor T1. In the stage of storing the power voltage, the power voltage signal line PVDD transmits the power voltage VDD, and the first transistor T1 is taken as a P-type transistor for illustration, and the power voltage VDD is greater than the reference voltage Vref, so that the voltage difference between the source and the gate of the first transistor T1 is greater than 0, at this time, the first transistor T1 is turned on, and the power voltage VDD continuously charges the gate of the first transistor T1. And during the power voltage storing phase, the third transistor T3 is turned on, and the power voltage reaches the gate of the first transistor T1 through the turned-on first transistor T1 and the turned-on third transistor T3. Due to the existence of the transistor threshold voltage, when the voltage of the gate of the first transistor T1 is VDD- | Vth |, the first transistor T1 starts to turn off, at which time the power supply voltage storage phase ends.
The light emitting voltage writing module 04 includes a fourth transistor T4, a source of the fourth transistor T4 is connected to the Data voltage line Data, and a drain of the fourth transistor T4 is connected to the second plate of the first capacitor C1. In the power voltage storage phase, the fourth transistor T4 is turned on, the Data voltage line Data transfers the Data voltage Vdata, and the fourth transistor T4 transfers the Data voltage Vdata to the second plate of the first capacitor C1; in the Data signal writing phase, the fourth transistor T4 is turned on, the Data voltage line Data transfers the reference voltage Vref, and the fourth transistor T4 transfers the reference voltage Vref to the second plate of the first capacitor C1. That is, the fourth transistor T4 may be used to store the data voltage Vdata to the first capacitor C1 during the power voltage storage phase, and the fourth transistor T4 may also be used to transmit the reference voltage Vref to the second plate of the first capacitor C1 during the data signal writing phase. Note that the data voltage line that transmits the data voltage Vdata in the power supply voltage storage phase may be different from the signal line that transmits the reference voltage Vref in the data signal writing phase.
The light emitting display module 00 includes a fifth transistor T5 and an organic light emitting diode OLED, wherein a source of the fifth transistor T5 is connected to the first output terminal OUT1 of the light emitting driving module 01, and a drain of the fifth transistor T5 is connected to an anode of the organic light emitting diode OLED. In the light emitting period, the fifth transistor T5 is turned on, and the fifth transistor T5 transmits the light emitting driving current generated by the light emitting driving module 01 to the anode of the organic light emitting diode OLED, so as to cause the organic light emitting diode OLED to emit light. That is, the source of the fifth transistor T5 is connected to the drain of the first transistor T1, and the drain of the fifth transistor T5 is connected to the anode of the organic light emitting diode OLED. In the light emitting period, the fifth transistor T5 is turned on for transmitting the light emitting driving current generated by the first transistor T1 to the anode of the organic light emitting diode OLED, and the organic light emitting diode OLED is activated to emit light.
Fig. 3 is a timing diagram of a pixel driving circuit according to an embodiment of the present disclosure, and the following system description is provided with reference to fig. 2 and fig. 3 to explain an operation principle of the pixel driving circuit. The pixel driving circuit provided by the embodiment of the application is used for organic light emitting display, and during the working period of the organic light emitting display, the working period of the pixel driving circuit comprises a plurality of cycles, and each cycle comprises an initialization phase t1, a power supply voltage storage phase t2, a data signal writing phase t3 and a light emitting phase t4 which are sequentially performed. Note that, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all P-type transistors, which will be described below as an example. Of course, any one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may be an N-type transistor.
Referring to fig. 2, a gate of the second transistor T2 is connected to the first signal line S1, a gate of the third transistor T3 is connected to the second signal line S2, a gate of the fourth transistor T4 is connected to the third signal line S3, and a gate of the fifth transistor T5 is connected to the emission control signal line EM.
In the initialization stage T1, the first signal line S1 receives a turn-on signal, i.e., a low level signal, and the second transistor T2 is turned on; the second signal line S2, the third signal line S3, and the emission control signal line EM receive an off signal, i.e., a high level signal or no signal, and the third transistor T3, the fourth transistor T4, and the fifth transistor are turned off. Meanwhile, the reference voltage Vref, Vref transmitted by the initial signal line REF is a low level signal, and the reference voltage Vref reaches the gate of the first transistor T1 through the turned-on second transistor T2, so that the first transistor T1 is controlled to be turned on, and the initialization of the light emitting driving module 01 is completed. Since the gate of the first transistor T1 is connected to the first plate of the first capacitor C1, in the initialization phase, the gate of the first transistor T1 is at the same level as the reference voltage Vref, i.e., the node N1 between the first transistor T1 and the first capacitor C1 is at the reference voltage Vref, wherein the potential of the first node N1 is equal to the gate of the first transistor T1.
In the power voltage storing period T2, the second signal line S2 receives a turn-on signal, i.e., a low level signal, and the third transistor T3 is turned on;the first signal line S1 and the emission control signal line EM receive an off signal, i.e., a high level signal or no signal, and the second transistor T2 and the fifth transistor T5 are turned off. Meanwhile, the power supply voltage signal line PVDD transmits the power supply voltage VDD. At the beginning point of the power voltage storage period T2, the gate potential of the first transistor T1 is the reference voltage Vref, the source potential of the first transistor T1 is the power voltage VDD, the potential difference between the source and the gate of the first transistor T1 is (VDD-Vref), and the potential difference between the source and the gate of the first transistor T1 is greater than 0, so that the first transistor T1 is turned on, and the power voltage VDD is transmitted to the gate of the first transistor T1 through the turned-on source and drain of the first transistor T1 and the turned-on third transistor T3, so that the gate potential of the first transistor T1 gradually increases. When the gate potential of the first transistor T1 is equal to (VDD- | Vth |), the first transistor T1 starts to turn off, and at this time, due to the presence of the first capacitor C1, the gate potential of the first transistor T1 is maintained at (VDD- | Vth |), that is, the potential of the first node N1 is VN1VDD- | Vth |, where Vth is the threshold voltage of the first transistor T1.
In one embodiment of the present application, during the power voltage storing period T2, the third signal line S3 also receives a turn-on signal, i.e., a low level signal, and the fourth transistor T4 is turned on. Meanwhile, the Data voltage line Data transfers the Data voltage Vdata, which is transferred to the first plate of the first capacitor C1 through the turned-on fourth transistor T4, that is, the potential of the second node N2 between the fourth transistor T4 and the first capacitor C1 is VN2Vdata, the potential of the second node N2 is the same as the potential of the second plate of the first capacitor C1.
That is, during the power voltage storage period t2, the writing of the power voltage into the first node N1 and the writing of the data voltage Vdata into the second node N2 can be performed simultaneously, and the voltage difference between the first node N1 and the second node N2 is VN2-VN1Vdata-VDD + | Vth |. In addition, the writing of the power voltage VDD to the first node N1 and the writing of the data voltage Vdata to the second node N2 may be performed sequentially in a time-sharing manner.
In the data signal write phase t3, the third signal line S3 receives the turn-on signal, i.e. the low level signal, and the fourth crystalThe tube T4 is open; the first signal line S1, the second signal line S2, and the emission control signal line EM receive an off signal, i.e., a high level signal or no signal, and the second transistor T2, the third transistor T3, and the fifth transistor T5 are turned off. While the source of the fourth transistor T4 receives the reference voltage Vref, which reaches the second plate of the first capacitor C1 through the turned-on fourth transistor T4, i.e., the potential V of the second node N2N2Vref. At this time, V is due to the presence of the first capacitance C1N2-VN1Vdata-VDD + | Vth |, i.e. VN1=VN2-Vdata+VDD-|Vth|=Vref-Vdata+VDD-|Vth|。
It should be noted that the source of the fourth transistor T4 receives the data voltage Vdata during the power voltage storing period T2 and the reference voltage Vref during the data signal writing period T3. Accordingly, the source of the fourth transistor T4 may be connected to a Data voltage line Data transmitting the Data voltage Vdata and a signal line transmitting the reference voltage Vref, respectively; or a data voltage line can be connected to transmit the data voltage Vdata and the reference voltage Vref in a time-sharing manner. In addition, in the data signal writing phase T3, the source of the fourth transistor T4 may receive the reference voltage Vref, or may be other signal voltages as long as the required light emitting driving current can be generated in cooperation with the data voltage.
In the light-emitting period T4, the light-emitting control signal line EM receives a turn-on signal, i.e., a low level signal, and the fourth transistor T4 is turned on; the first signal line S1, the second signal line S2, and the third signal line S3 receive an off signal, i.e., a high level signal or no signal, and the second transistor T2, the third transistor T3, and the fourth transistor T4 are turned off. Meanwhile, the power voltage signal line PVDD transmits the power voltage VDD, i.e., the source potential of the first transistor T1 is the power voltage VDD, and at this time, the voltage difference between the source and the gate of the first transistor T1 is VSG=VDD-|Vth|-VN1VDD- | Vth | - (Vref-Vdata + VDD- | Vth |) ═ Vdata-Vref. That is, in the light emitting period T4, the voltage difference between the source and the gate of the first transistor T1 is independent of the power voltage VDD and the threshold voltage | Vth | of the first transistor T1, and the voltage drop of the power voltage VDD on the power voltage signal line PVDD to the light emitting driving circuit is eliminatedThe influence of the current and the influence of the threshold voltage | Vth | of the first transistor T1 on the light emitting driving current, so that the pixel driving circuit has a stable light emitting driving current, and the display effect is ensured.
Fig. 4 is a schematic diagram of another pixel driving circuit provided in an embodiment of the present application, and as shown in fig. 4, the pixel driving circuit further includes a second initialization module 06, where the second initialization module 06 includes a sixth transistor T6, a source of the sixth transistor T6 is connected to the initial signal line REF, and a drain of the sixth transistor is connected to an anode of the organic light emitting diode OLED. In the initialization phase, the sixth transistor T6 is turned on, and the sixth transistor T6 transmits the reference voltage Vref to the anode of the organic light emitting diode OLED to initialize the organic light emitting diode OLED. That is, in the initialization stage, the reference voltage Vref reaches the anode of the organic light emitting diode OLED through the turned-on sixth transistor T6, and the initialization of the organic light emitting diode OLED is completed.
Further, the gate of the sixth transistor T6 and the gate of the second transistor T2 may both be connected to the first signal line S1, so that in the initialization stage T1, it may be ensured that the second transistor T2 and the sixth transistor T6 are turned on simultaneously, and the gate of the first transistor T1 and the anode of the organic light emitting diode OLED are initialized simultaneously.
With continued reference to fig. 4, since the initialization phase t1 receives the reference voltage Vref and the Data signal writing phase t3 receives the Data voltage Vdata in a time-sharing manner, the initial signal line REF and the Data voltage line Data can be multiplexed, and the signal line transmits the reference voltage Vref during the initialization phase t1 and transmits the Data voltage Vdata during the power voltage storing phase t 2. At this time, it is preferable that the source of the fourth transistor T4 is connected to only the Data voltage line Data, and the source of the fourth transistor T4 receives the reference voltage Vref during the Data signal writing phase T3, so that the signal of the Data voltage line Data is easily controlled.
With reference to fig. 4, the pixel driving circuit according to the embodiment of the present disclosure further includes a second capacitor C2, the second capacitor C2 includes a third plate and a fourth plate, the third plate is connected to the power voltage signal line PVDD, and the fourth plate is connected to the second plate of the first capacitor C1. That is, the second capacitor C2 is disposed between the second node N2 and the power supply voltage signal line PVDD, and may be used to stabilize the potential of the second node N2, i.e., the potential of the first plate of the first capacitor C1.
Fig. 5 is a schematic diagram of another pixel driving circuit according to an embodiment of the present disclosure, and fig. 6 is a timing diagram of another pixel driving circuit according to an embodiment of the present disclosure. As can be seen from the above analysis, in the light emitting period T4, the second transistor T2 and the third transistor T3 are both turned off, and the second transistor T2 and the third transistor T3 are both connected to the gate of the first transistor T1. In the light emitting period T4, in order to prevent the second transistor T2 and the third transistor T3 from generating leakage current and thus affecting the gate potential of the first transistor T1, the active layers of the second transistor T2 and the third transistor T3 may be disposed as metal oxide active layers, and the active layers of the first transistor T1, the fourth transistor T4 and the fifth transistor T5 may be low temperature polysilicon or a-Si. Meanwhile, the second transistor T2 and the third transistor T3 may be N-type transistors, and the first transistor T1, the fourth transistor T4 and the fifth transistor T5 may be P-type transistors.
Also, when the pixel driving circuit includes the second initializing module 06, i.e., includes the sixth transistor T6, the sixth transistor T6 is also turned off during the light emitting period T4, and the drain electrode of the sixth transistor T6 is connected to the anode electrode of the organic light emitting diode OLED. In the light emitting period T4, in order to prevent the sixth transistor T6 from generating a leakage current and thus affecting the anode potential of the organic light emitting diode OLED, the active layer of the sixth transistor T6 may be set as a metal oxide active layer, and meanwhile, the sixth transistor T6 may also be an N-type transistor.
Referring to fig. 6, since the second transistor T2, the third transistor T3 and/or the sixth transistor T6 are N-type transistors, at the initial stage T1, the first signal line S1 transmits a turn-on signal, i.e., a high level signal, to control the second transistor T2 and/or the sixth transistor T6 to turn on, thereby completing the initialization of the gate of the first transistor T1 and/or the anode of the organic light emitting diode OLED. During the power voltage storing period T2, the second signal line S2 transmits a turn-on signal, i.e., a high level signal, to control the third transistor T3 to turn on, thereby completing the writing of the power voltage VDD into the gate of the first transistor T1.
Fig. 7 is a schematic view of an organic light emitting display panel according to an embodiment of the present disclosure, and as shown in fig. 7, the organic light emitting display panel according to the embodiment of the present disclosure includes a plurality of pixel units P, where each pixel unit P corresponds to one pixel driving circuit. And the organic light emitting diode OLED and each transistor in the pixel driving circuit are located in different film layers, wherein the fifth transistor T5 is electrically connected with the organic light emitting diode OLED through a via hole.
In the organic light emitting display panel provided by the embodiment of the application, the light emitting driving current in the pixel driving circuit is not affected by the voltage drop of the power voltage on the signal line, so that the organic light emitting display panel has stable light emitting driving current, excellent display effect and higher light emitting uniformity.
Fig. 8 is a schematic view of an organic light emitting display device according to an embodiment of the present disclosure, and as shown in fig. 8, the organic light emitting display device according to the embodiment of the present disclosure may be a mobile phone, and the organic light emitting display device according to the embodiment of the present disclosure may also be a display device such as a computer or a television. The organic light-emitting display device provided by the embodiment of the application comprises the organic light-emitting display panel provided by the embodiment of the application. The organic light emitting display device includes a display area AA in which a pixel driving circuit is disposed, and a non-display area BB disposed at a periphery of the display area AA.
In the organic light emitting display device provided by the embodiment of the application, the light emitting driving current in the pixel driving circuit is not affected by the voltage drop of the power voltage on the signal line, so that the organic light emitting display device has stable light emitting driving current, excellent display effect and higher light emitting uniformity.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.