CN111351973B

CN111351973B - Current measuring circuit

Info

Publication number: CN111351973B
Application number: CN201911316061.8A
Authority: CN
Inventors: 纳迪姆·赫拉特; 菲利普·戈里斯; 克里斯托弗·特龙·恩戈
Original assignee: Qorvo US Inc
Current assignee: Qorvo US Inc
Priority date: 2018-12-20
Filing date: 2019-12-19
Publication date: 2023-07-28
Anticipated expiration: 2039-12-19
Also published as: CN111351973A

Abstract

A current measurement circuit is provided. The current measurement circuit is configured to receive a sense current proportional to the target current to continuously charge the capacitor to a sense voltage. The current measurement circuit is configured to determine whether the sense voltage reaches a predetermined voltage threshold and to reduce the sense voltage below the predetermined voltage threshold in response to the sense voltage reaching the predetermined voltage threshold. The current measurement circuit counts each occurrence of the sensed voltage reaching the predetermined voltage threshold and quantifies current based on a total number of the sensed voltage reaching the predetermined voltage threshold over a predetermined measurement period. By incorporating the current measurement circuit into an electronic device, monitoring can be accurately performed and thereby help optimize power consumption and battery life of the electronic device.

Description

Current measuring circuit

RELATED APPLICATIONS

The present application claims priority from U.S. provisional patent application serial No. 62/782,908 filed on 12/20 of 2018, the entire contents of which are incorporated herein by reference.

Technical Field

The technology of the present disclosure relates generally to measuring current in an electronic device.

Background

Mobile communication devices have become increasingly popular in today's society. The popularity of these mobile communication devices is driven to some extent by the variety of functions now implemented on such devices. The increase in processing power in such devices means that mobile communication devices have evolved from pure communication tools to complex mobile multimedia centers capable of enhancing user experience.

Redefined user experience requires wireless communication technologies such as Long Term Evolution (LTE) and fifth generation new radio (5G-NR) to provide higher data rates. To achieve higher data rates in mobile communication devices, complex Power Amplifiers (PAs) may be employed to increase the output power of Radio Frequency (RF) signals transmitted by the mobile communication device (e.g., to maintain sufficient energy per bit). However, an increase in RF signal output power may result in an increase in power consumption and heat dissipation of the mobile communication device, thereby compromising overall performance and user experience.

It should be noted that mobile communication devices are typically powered by batteries having limited capacity. In this regard, the power consumption and battery life of a mobile communication device may have a direct impact on the overall user experience. As such, it may be desirable to obtain accurate current consumption measurements in a mobile communication device to help optimize power consumption and battery life of the mobile communication device.

Disclosure of Invention

Embodiments of the present disclosure relate to a current measurement circuit. The current measurement circuit is configured to receive a sense current proportional to the target current. The capacitor in the current measurement circuit is continuously charged by the sense current to generate a sense voltage. Thus, the current can be quantified based on the change in the sensed voltage over a predetermined measurement period. In examples discussed herein, the current measurement circuit is configured to determine whether the sense voltage reaches a predetermined voltage threshold and to reduce the sense voltage below the predetermined voltage threshold in response to the sense voltage reaching the predetermined voltage threshold. Thus, the sensing voltage varies in a zigzag manner in a predetermined measurement period. The current measurement circuit is configured to count each occurrence of the sensed voltage reaching a predetermined voltage threshold and to quantify the current based on a total number of sensed voltages reaching the predetermined voltage threshold over a predetermined measurement period. By incorporating the current measurement circuit into the electronic device, monitoring can be accurately performed and thus help optimize power consumption and battery life of the electronic device.

In one aspect, a current measurement circuit is provided. The current measurement circuit includes a sense current input configured to receive a sense current proportional to a current to be measured. The current measurement circuit also includes a clock input configured to receive a clock signal including a plurality of clock cycles. The current measurement circuit further includes a capacitor coupled to the sense current input and configured to generate a sense voltage corresponding to the sense current. The current measurement circuit further includes a determination circuit coupled to the capacitor. The determination circuit is configured to determine whether the sensing voltage reaches a predetermined voltage threshold. The determination circuit is further configured to count each occurrence of the sense voltage reaching a predetermined voltage threshold for a predetermined measurement time period corresponding to a defined number of clock cycles. The determination circuit is further configured to reduce the sensing voltage below the predetermined voltage threshold each time the sensing voltage reaches the predetermined voltage threshold. The determination circuit is further configured to quantify the current based on a total number of occurrences of the sensed voltage reaching the predetermined voltage threshold within the predetermined measurement period.

Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.

Drawings

The accompanying drawings incorporated in and forming a part of the specification illustrate several aspects of the present disclosure and, together with the description, serve to explain the principles of the disclosure.

FIG. 1 is a schematic diagram of a conventional current measurement circuit configured to measure current;

FIG. 2 is a schematic diagram of a current measurement circuit configured in accordance with an embodiment of the present disclosure for measuring current in a predetermined measurement period;

FIG. 3 is a graphical diagram providing an exemplary graphical illustration of the current measurement circuit of FIG. 2 configured to quantify a current;

FIG. 4 is a schematic diagram of an exemplary current measurement circuit configured to measure an average value of the current in FIG. 2 over an extended measurement period longer than a predetermined measurement period;

FIG. 5 is a graphical illustration providing an exemplary graphical illustration of the current measurement circuit of FIG. 4 configured in accordance with one embodiment of the present disclosure for quantifying current over an extended predetermined measurement period;

FIG. 6 is a graphical illustration providing an exemplary graphical illustration of the current measurement circuit of FIG. 4 configured in accordance with another embodiment of the present disclosure for quantifying current over an extended predetermined measurement period; and

fig. 7 is a schematic diagram of an exemplary power measurement circuit incorporating the current measurement circuit of fig. 4.

Detailed Description

The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly extending onto" another element, there are no intervening elements present. Also, it will be understood that when an element such as a layer, region or substrate is referred to as being "over" or extending "onto" another element, it can be directly over or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

Relative terms such as "below … …" or "above … …" or "up" or "down" or "horizontal" or "vertical" may be used herein to describe one element, layer or region's relationship to another element, layer or region as illustrated in the figures. It should be understood that these terms, as discussed above, are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and/or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Embodiments of the present disclosure relate to a current measurement circuit. The current measurement circuit is configured to receive a sense current proportional to the target current. The capacitor in the current measurement circuit is continuously charged by the sense current to generate a sense voltage. Accordingly, the current can be quantified based on the change in the sensed voltage over a predetermined measurement period. In examples discussed herein, the current measurement circuit is configured to determine whether the sense voltage reaches a predetermined voltage threshold and to reduce the sense voltage below the predetermined voltage threshold in response to the sense voltage reaching the predetermined voltage threshold. Thus, the sensing voltage varies in a zigzag manner in a predetermined measurement period. The current measurement circuit is configured to count each occurrence of the sensed voltage reaching a predetermined voltage threshold and to quantify the current based on a total number of sensed voltages reaching the predetermined voltage threshold over a predetermined measurement period. By incorporating the electrical measurement circuit into the electronic device, monitoring can be accurately performed and thus help optimize power consumption and battery life of the electronic device.

Before discussing the current measurement circuit of the present disclosure, a brief overview of a conventional current measurement circuit is first provided with reference to fig. 1 to help understand conventional current measurement mechanisms and problems associated with conventional current measurement mechanisms. A discussion of specific exemplary aspects of the current measurement circuit of the present disclosure is then initiated with reference to fig. 2.

In this regard, FIG. 1 is a schematic diagram configured to measure a current I _{Capacitor with a capacitor body} A schematic diagram of a conventional current measurement circuit 10. The conventional current measurement circuit 10 includes a capacitor 12 as a capacitance C0 and configured to be driven by a current I _{Capacitor with a capacitor body} Continuous charging to generate voltage V _{Capacitor with a capacitor body} . Current I _{Capacitor with a capacitor body} Capacitance C0 and voltage V _{Capacitor with a capacitor body} The relationship between them is well known and can be expressed as the following equation (equation 1).

I _{Capacitor with a capacitor body} ＝C0*(ΔV _{Capacitor with a capacitor body} Δt) (equation 1)

As shown in the above equation (equation 1)By measuring the voltage V over a period of time (Deltat) _{Capacitor with a capacitor body} Variation of (DeltaV) _{Capacitor with a capacitor body} ) To quantify the current I _{Capacitor with a capacitor body} . Accordingly, the conventional current measurement circuit 10 may include a current calculator 14 to quantify the current I based on the above equation (equation 1) _{Capacitor with a capacitor body} 。

When the conventional current measurement circuit 10 is used to measure a current I in an electronic device (e.g., a smart phone) _{Capacitor with a capacitor body} At this time, the capacitor 12 needs to be small (e.g., c0=50pf) due to space limitations of the electronic device. Thus, the voltage is changed by DeltaV _{Capacitor with a capacitor body} May be quite large during the time period (Δt). For example, if the time period (Δt) is 128 μs, and the current I _{Capacitor with a capacitor body} 0.08mA, voltage change DeltaV _{Capacitor with a capacitor body} May be as high as 205V, which may cause potential damage to the electronic device. As such, it may be desirable to create a new current measurement mechanism to accurately measure current I in an electronic device without causing damage to the electronic device _{Capacitor with a capacitor body} 。

In this regard, FIG. 2 is a diagram configured in accordance with an embodiment of the present disclosure for use in a predetermined measurement period T _{Measurement of} In measuring current I _{Actual practice is that of} A schematic diagram of the current measurement circuit 16. And directly measuring current I _{Actual practice is that of} Instead, the current measurement circuit 16 is configured to instead measure the sum current I _{Actual practice is that of} Proportional correlated sense current I _Sensing As shown in the following equation (equation 2).

I _Sensing ＝I _{Actual practice is that of} /C _{Ratio of} (equation 2)

In the above equation (equation 2), C _{Ratio of} (C _{Ratio of} >1) Representing the current I _{Actual practice is that of} And sense current I _Sensing The ratio of the two. By measuring a small sense current I _Sensing It is possible to construct the current measurement circuit 16 with fewer and/or smaller components (e.g., transistors) to help reduce the footprint of the current measurement circuit 16.

The current measurement circuit 16 includes a capacitor 18 having a capacitance C0. Sense current I _Sensing Continuously charging capacitor 18 to produce a senseMeasuring voltage V _{Capacitor with a capacitor body} . Thus, the determination circuit 20 may be coupled to the capacitor 18 in the current measurement circuit 16 to measure the sense voltage V _{Capacitor with a capacitor body} And quantizes the sense current I according to equation (equation 1) _Sensing And further quantizes the current I based on equation (equation 2) _{Actual practice is that of} 。

And the voltage V across the capacitor 12 in figure 1 _{Capacitor with a capacitor body} In contrast to conventional current measurement circuit 10, which may reach an unpredictable level, current measurement circuit 16 is configured to sense voltage V across capacitor 18 _{Capacitor with a capacitor body} Is capped based on a predetermined voltage threshold V ₁ Accurately measuring sense current I at the same time at a predetermined level of (a) _Sensing . In this regard, the current measurement circuit 16 is superior to the conventional current measurement circuit 10 in terms of practicality, reliability, and durability.

The current measurement circuit 16 may include a circuit configured to receive a sense current I _Sensing And a clock input 24 configured to receive a clock signal Clk corresponding to a plurality of clock cycles 26. Each clock cycle 26 has a corresponding clock duration T _Clock . The current measurement circuit 16 may also include a circuit configured to receive a predetermined voltage threshold V ₁ Is provided for the voltage input 28 of the circuit. The current measurement circuit 16 may also receive a control signal 30 configured to control the current measurement circuit 16 to start/stop measuring the sense current I _Sensing 。

The determination circuit 20 is coupled to the capacitor 18. The determination circuit 20 is configured to determine the measurement period by _{Measurement of} Upper measurement of sense voltage V _{Capacitor with a capacitor body} To quantify the sense voltage I _Sensing . Predetermined measurement period T _{Measurement of} May be configured to include a defined number of clock cycles 26. For example, the corresponding clock duration T of the clock signal Clk _Clock May be 0.5 mus and a predetermined measurement period T _{Measurement of} May be configured (e.g., via control signal 30) to include 256 clock cycles. Thus, a predetermined measurement period T _{Measurement of} May have a duration of 128 mus (256 x 0.5 mus). Thus, the determination circuit 20 may be configured to accurately determine the predetermined measurement based on the clock signal ClkPeriod T _{Measurement of} 。

In a non-limiting example, the determination circuit 20 includes a voltage comparator 32, a counter 34, a reference current generator 36, and a calculation circuit 38. The voltage comparator 32 may be directly coupled to the capacitor 18 and the reference current generator 36 may be coupled to the capacitor 18 via a switch SW. Counter 34 may be coupled to voltage comparator 32 and clock input 24. The calculation circuit 38 may be coupled to the counter 34 and the clock input 24.

The voltage comparator 32 is configured to measure the voltage of the capacitor in a predetermined measurement period T _{Measurement of} Will sense voltage V _{Capacitor with a capacitor body} With a predetermined voltage threshold value V ₁ A comparison is made. Each time sense voltage V _{Capacitor with a capacitor body} Reaching a predetermined voltage threshold V ₁ (e.g., V _{Capacitor with a capacitor body} ≥V ₁ ) The voltage comparator 32 generates an indication signal 40 to increment the counter 34 by one (1). Indication signal 40 may also cause counter 34 to generate signal 42 to close switch SW at the same time or after incrementing counter 34 by 1, thereby coupling reference current generator 36 to capacitor 18. Thus, the reference current generator 36 may generate an edge relative to the sense current I _Sensing Reference current I flowing in opposite directions _{Reference to} . In this regard, reference current I _{Reference to} May be coupled to sense current I at input 44 of capacitor 18 _Sensing Combine to produce a combined current I _{Sum total} (I _{Sum total} ＝I _Sensing - I _{Reference to} ). In a non-limiting example, reference current I _{Reference to} Equal to the sense current I _Sensing . Thus, the combined current I _{Sum total} Can be zero to enable the sensing voltage V _{Capacitor with a capacitor body} Reduced to a predetermined voltage threshold V ₁ The following is given.

In a non-limiting example, the counter 34 may be configured to count the time duration T of the corresponding clock _Clock Thereafter, the switch SW is opened to remove the reference current I _{Reference to} . In this way, the capacitor 18 again passes the sense current I _Sensing Charging to sense voltage V _{Capacitor with a capacitor body} Toward a predetermined voltage threshold V ₁ And (3) increasing. In this regard, during a predetermined measurement period T _{Measurement of} In this, the sensing voltage is repeatedly increased and decreased in a zigzag manner. During a predetermined measuring period T _{Measurement of} At the end, the counter 34 may already sense the voltage V for each occurrence _{Capacitor with a capacitor body} Reaching a predetermined voltage threshold V ₁ Recording to generate a sensing voltage V _{Capacitor with a capacitor body} Reaching a predetermined voltage threshold V ₁ Is referred to as "total number N" hereinafter for brevity _Counting "). In a non-limiting example, counter 34 may generate binary word 46 to digitally quantize total number N _Counting And stores binary word 46 in register 48.

In a non-limiting example, binary word 46 may have a defined number of bits L. Thus, binary word 46 may also be referred to as an L-bit binary word. In this regard, the total number N that may be stored in the binary word 46 without causing overflow of the binary word 46 _Counting Is the maximum value of (hereinafter referred to as "N" for simplicity _{Maximum value} ") is 2 ^L . For example, if the binary word is an 8-bit binary word (l=8), the binary word 46 may be stored without causing overflowed N _{Maximum value} 256 (2) ⁸ )。

Let N be _{Maximum value} Corresponding to the total number N _Counting Maximum value of (1), N _{Maximum value} Also corresponding to current I _{Actual practice is that of} Full scale (maximum level) of (hereinafter referred to as "MAX (I) _{Actual practice is that of} ) "). Therefore, the current I can be calculated based on the following equation (equation 3) _{Actual practice is that of} Full scale division into multiple bitwise units I _{Unit (B)} 。

I _{Unit (B)} ＝MAX(I _{Actual practice is that of} )/N _{Maximum value} ＝MAX(I _{Actual practice is that of} )/2 ^L (equation 3)

In this regard, the total number N in the binary word 46 _Counting Each of which corresponds to a current I _{Actual practice is that of} Is according to bit unit I of (2) _{Unit (B)} . Thus, it can be based on the total number N _Counting And per bit unit I _{Unit (B)} To quantify the sense current I _Sensing And current I _{Actual practice is that of} As shown in the following equations (equations 4.1 and 4.2).

I _Sensing ＝N _Counting *I _{Unit (B)} /C _{Ratio of} (equation 4.1)

I _{Actual practice is that of} ＝N _Counting *I _{Unit (B)} (equation 4.2)

In addition, N _{Maximum value} Can be used for determining the time period T of the predetermined measurement _{Measurement of} A defined number of clock cycles 26, which can be expressed in terms of the following equation (equation 5). In this regard, once the number of bits L defined in the binary word 46 is determined, N is also determined _{Maximum value} 、I _{Unit (B)} And T _{Measurement of} 。

T _{Measurement of} ＝N _{Maximum value} *T _Clock ＝2 ^L *T _Clock (equation 5)

FIG. 3 is a graphical diagram 50 providing an exemplary graphical illustration of the current measurement circuit 16 of FIG. 2 configured to measure current during a predetermined measurement period T _{Measurement of} Inner pair current I _{Actual practice is that of} Quantization is performed. The elements in fig. 2 are referenced in conjunction with the elements in fig. 3 and will not be repeated here.

At time t ₀ Where it corresponds to a predetermined measurement period T _{Measurement of} Is to sense the voltage V _{Capacitor with a capacitor body} May be at an initial voltage level V ₀ . At time t ₁ The capacitor 18 is driven by the sense current I _Sensing Charging to sense voltage V _{Capacitor with a capacitor body} Up to a predetermined voltage threshold V ₁ . In a non-limiting example, the predetermined voltage threshold V ₁ It may also be determined based on the following equation (equation 6).

V ₁ ＝V ₀ +(N _{Maximum value} *I _{Unit (B)} *T _Clock )/(C0*C _{Ratio of} ) (equation 6)

When sensing voltage V _{Capacitor with a capacitor body} Reaching a predetermined voltage threshold V ₁ At this time, the counter 34 is triggered to increment the binary word 46 by 1. Simultaneously or subsequently, switch SW is closed to couple reference current generator 36 to capacitor 18 to generate reference current I _{Reference to} . As previously described, reference current I _{Reference to} Edge versus sense current I _Sensing To cancel sense current I _Sensing . In a non-limiting exampleIn (1) reference current I _{Reference to} Can be determined based on the following equation (equation 7).

I _{Reference to} ＝N _{Maximum value} *I _{Unit (B)} /C _{Ratio of} (equation 7)

Thus, at time t ₂ At the sense voltage V _{Capacitor with a capacitor body} Can be from a predetermined voltage threshold V ₁ Reduced to an intermediate voltage level V ₂ (V ₀ <V ₂ <V ₁ ). In a non-limiting example, time t ₁ And t ₂ The duration in between may be equal to the respective clock cycle duration T of each of the clock cycles 26 _Clock And an intermediate voltage level V ₂ Can be determined based on the following equation (equation 8).

V ₂ ＝V ₀ +(N _Counting *I _{Unit (B)} *T _Clock )/(C0*C _{Ratio of} ) (equation 8)

Therefore, based on the above equations (equations 6 and 8), the predetermined voltage threshold V ₁ And an intermediate voltage level V ₂ The difference between them can be expressed by the following equation (equation 9).

V ₁ -V ₂ ＝(N _{Maximum value} -N _Counting )*I _{Unit (B)} *T _Clock /(C0*C _{Ratio of} ) (equation 9)

At time t ₂ At this point, counter 34 may cause switch SW to open to remove reference current I _{Reference to} . Thus, the voltage V is sensed _{Capacitor with a capacitor body} Start to go again towards the predetermined voltage threshold V ₁ Rising. In this regard, the voltage V is sensed _{Capacitor with a capacitor body} Is configured to be in a predetermined measurement period T _{Measurement of} Is increased and decreased in a zigzag manner, and the counter 34 is configured to sense the voltage V for each occurrence _{Capacitor with a capacitor body} Reaching a predetermined voltage threshold V ₁ Counting is performed. At the end of the predetermined measurement period (e.g., at time t _x Where) the counter 34 has generated the sense voltage V _{Capacitor with a capacitor body} Reaching a predetermined voltage threshold V ₁ Total number (N) _Counting ). Thus, the calculation circuit 38 may quantify the sense current I based on equations (equations 4.1 and 4.2), respectively _Sensing And current I _{Actual practice is that of} 。

Graph 50 shows that current measurement circuit 16 of FIG. 2 may be operated for a predetermined measurement period T _{Measurement of} Internal accurate quantization of current I _{Actual practice is that of} . However, in some cases it may also be desirable to measure the period T more than a predetermined _{Measurement of} Quantification of current I over longer extended measurement periods _{Actual practice is that of} Average value of (2). In this regard, FIG. 4 is a schematic diagram of an exemplary current measurement circuit 52, the current measurement circuit 52 configured to measure current during a period T that is greater than a predetermined measurement period _{Measurement of} Longer extended measurement period T _{Measurement-extension} Upper quantization of current I in fig. 2 _{Actual practice is that of} Average value of (for simplicity, hereinafter referred to as "average current I _{Average of} "). Common elements between fig. 2 and 4 are shown with common element numbers, and will not be repeated here.

The current measurement circuit 52 includes a determination circuit 54, the determination circuit 54 including a voltage comparator 32, a counter 34, and a reference current generator 36. The voltage comparator 32 is configured to sense the voltage V _{Capacitor with a capacitor body} With a predetermined voltage threshold V ₁ Comparison is performed to determine the sensed voltage V _{Capacitor with a capacitor body} Whether or not a predetermined voltage threshold V is reached ₁ . Each time sense voltage V _{Capacitor with a capacitor body} Reaching a predetermined voltage threshold V ₁ At this point, the counter 34 will increment by 1. In this regard, in extending the measurement period T _{Measurement-extension} At the end, the counter 34 will have sensed the voltage V for each occurrence _{Capacitor with a capacitor body} Reaching a predetermined voltage threshold V ₁ Counting to generate a total number N _Counting 。

The determination circuit 54 includes a second counter 56 and a latch 58. The determination circuit 54 may also include a divider 60. The second counter 56 is configured to count the clock cycles 26 to generate a count of the number of clock cycles in the extended measurement period T _{Measurement-extension} The total number of clock cycles 26 occurring therein (hereinafter referred to as "total number T" for simplicity _Counting "). The latches 58 may be configured to latch a total T _Counting So that the divider 60 sums up the N _Counting Divided by the total number T _Counting (N _Counting /T _Counting ). The determination circuit 54 may also include a calculation circuit 62 configured to be based on the total number N _Counting Sum total T _Counting To quantify the extended measurement period T _{Measurement-extension} Average current I in _{Average of} . In a non-limiting example, the average current I _{Average of} Can be determined based on the following equation (equation 10).

I _{Average of} ＝(N _Counting /T _Counting )*(N _{Maximum value} *I _{Unit (B)} /C _{Ratio of} ) (equation 10)

FIG. 5 is a block diagram providing a method for extending a predetermined measurement period T, configured in accordance with one embodiment of the present disclosure _{Measurement-extension} Internal quantization current I _{Actual practice is that of} Is illustrated in the exemplary graphical illustration of the current measurement circuit 52 of fig. 4, is graphical diagram 64. The elements in fig. 4 are referenced in conjunction with the elements in fig. 5 and will not be repeated here.

In a non-limiting example, the measurement period T is extended _{Measurement-extension} Comprising an integer number of predetermined measuring periods T _{Measurement-1} To T _{measurement-M} . As described above, the measurement period T is prolonged _{Measurement-extension} Is also latched at the total number T _Counting Where it is located. Thus, the measurement period T is prolonged _{Measurement-extension} Can be expressed as the following equation (equation 11).

Every predetermined measurement period T _{Measurement-1} To T _{measurement-M} All have a corresponding duration T _{Measurement-i} (1.ltoreq.i.ltoreq.M) which can be expressed according to the following equation (equation 12).

T _{Measurement-i} ＝N _Maximum-i *T _Clock (1. Ltoreq.i.ltoreq.M) (equation 12)

In the above equation (equation 12), N _Maximum-i Equivalent to N as described previously _{Maximum value} . It should be noted that during a predetermined measurement period T _{Measurement-1} To T _{measurement-M} Each duration T of (a) _{Measurement-i} (1.ltoreq.i.ltoreq.M)) may be the same or different. Corresponding toThe counter 34 is configured to be set up as described above in fig. 2 and 3 for each predetermined measurement period T _{Measurement-1} To T _{measurement-M} In which the sense voltage reaches a predetermined voltage threshold V for each occurrence ₁ Counting to generate a plurality of total numbers N _Count-1 To N _count-M . Assume sense current I _Sensing During a predetermined measuring period T _{Measurement-1} To T _{measurement-M} The total number N may be the same or different _Count-1 To N _count-M Or may be the same or different. In the present example, the total number N _Counting Is the total number N _Count-1 To N _count-M Sum of (2)

It should be noted that due to inactivity (e.g., shut down) of the device in which the current measurement circuit 52 is provided, during the predetermined measurement period T _{Measurement-1} To T _{measurement-M} During one or more of (a) sensing current I _Sensing May become zero. In this regard, the current measurement circuit 52 may be configured to exit the extended measurement period T (e.g., via the control signal 30) _{Measurement-extension} Or temporarily suspend lengthening the measurement period T _{Measurement-extension} Until the current I is sensed _Sensing Become available again.

In a non-limiting example, the predetermined measurement period T _{Measurement-1} To T _{measurement-M} May be separately associated with a plurality of Orthogonal Frequency Division Multiplexing (OFDM) symbols/slots S ₁ To S _M Alignment. It should be noted that in advanced wireless communication systems such as the fifth generation new radio (5G-NR), the current I _{Actual practice is that of} May vary from one OFDM symbol/slot to another OFDM symbol/slot. As such, the current measurement circuit 52 may be capable of measuring across OFDM symbols/slots S ₁ To S _M Average current I of (2) _{Average of} . It should be appreciated that even if the measurement period T is prolonged _{Measurement-extension} The current measurement circuit 52 is also capable of being based on the total number N, not aligned with the corresponding boundary of the OFDM symbol/slot _Counting Total T _Counting And equation (et al 10) to measure across multipleAverage current I of OFDM symbol/slot _{Average of} 。

Referring again to FIG. 4, and is latched at total T _Counting Conversely, latch 58 may be configured to latch for a selected number of clock cycles 2 ^k (2k≥N _{Maximum value} ). In this regard, FIG. 6 is a block diagram providing a method for extending a predetermined measurement period T configured in accordance with another embodiment of the present disclosure _{Measurement-extension} Internal quantization current I _{Actual practice is that of} Is illustrated graphically 66 of the exemplary graphical illustration of current measurement circuit 52 of fig. 4. The elements in fig. 4 are referenced in conjunction with the elements in fig. 6 and will not be repeated here.

As shown in graph 66, the measurement period T is extended _{Measurement-extension} During a predetermined measuring period T _{measurement-M} Ending in the middle of (a). Thus, the measurement period T is prolonged _{Measurement-extension} Comprising a non-integer number of predetermined measuring periods T _{Measurement-1} To T _{measurement-M} . Thus, the measurement period T is prolonged _{Measurement-extension} The duration of (2) depends on the selected number of clock cycles, 2k, as shown in the following equation (equation 13).

T _{Measurement-extension} ＝2 ^k *T _Clock (equation 13)

The counter 34 is configured to sense the voltage V for each occurrence _{Capacitor with a capacitor body} Reaching the predetermined voltage threshold counts until the latch 58 latches a selected number 2 of clock cycles ^k . Accordingly, divider 60 sums up N _Counting Divided by a selected number of clock cycles 2 ^k (N _Counting /2 ^k ). In a non-limiting example, divider 60 may be implemented by simply summing the total number N _Counting Shift k bits right to shift the total number N _Counting Divided by a selected number of clock cycles 2 ^k . Thus, the average current I _{Average of} The determination may be based on the following equation (equation 14)

I _{Average of} ＝(N _Counting /2 ^k )*(N _{Maximum value} *I _{Unit (B)} /C _{Ratio of} ) (equation 14)

It should be noted that when measuring the current I _{Actual practice is that of} The current measurement circuit 16 and the current measurement circuit of fig. 2The current measurement circuits 52 of fig. 4 may each draw a small amount of current. However, when the current I is not measured _{Actual practice is that of} When electrical measurement circuit 16 and current measurement circuit 52 may not draw any current. Thus, by respectively at the predetermined measuring period T _{Measurement of} And extending the measurement period T _{Measurement-extension} External switching off of the electrical measurement circuit 16 and the current measurement circuit 52 (e.g., via the control signal 30) minimizes the measurement current I measured therein _{Actual practice is that of} The efficiency of the electronic device is deteriorated.

The current measurement circuit 52 of fig. 4 may be provided in a power measurement circuit to extend the measurement period T _{Measurement-extension} The average power is measured. In this regard, fig. 7 is a schematic diagram of an exemplary power measurement circuit 68 incorporating the current measurement circuit 52 of fig. 4.

The power measurement circuit 68 includes a power calculation circuit 70. The power calculation circuit 70 is configured to receive the average current I measured by the current measurement circuit 52 described above _{Average of} . The power calculation circuit 70 may also receive a voltage input V _{Battery cell} . Thus, the power calculation circuit 70 can be based on the average current I _{Average of} And a voltage input V _bat To measure average power P _{Average of} 。

Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims

1. A current measurement circuit, comprising:

a sense current input configured to receive a sense current that is less than a current to be measured;

a clock input configured to receive a clock signal comprising a plurality of clock cycles;

a capacitor coupled to the sense current input and configured to generate a sense voltage corresponding to the sense current; and

a determination circuit coupled to the capacitor and configured to:

determining whether the sensing voltage reaches a predetermined voltage threshold;

counting each occurrence of the sense voltage reaching the predetermined voltage threshold for a predetermined measurement period corresponding to a defined number of the plurality of clock cycles;

reducing the sensing voltage below the predetermined voltage threshold upon each occurrence of the sensing voltage reaching the predetermined voltage threshold; and

the current is quantified in accordance with a total number of occurrences of the sensed voltage reaching the predetermined voltage threshold and a ratio of the current to the sensed current within the predetermined measurement period.

2. The current measurement circuit of claim 1, wherein the determination circuit comprises:

a voltage comparator configured to compare the sensing voltage with the predetermined voltage threshold to determine whether the sensing voltage reaches the predetermined voltage threshold;

a counter configured to:

counting each occurrence of the sensed voltage reaching the predetermined voltage threshold for the predetermined measurement period; and

storing the total number of occurrences that the sense voltage reaches the predetermined voltage threshold;

a reference current generator configured to generate a reference current flowing in an opposite direction with respect to the sense current in response to the sense voltage reaching the predetermined voltage threshold; and

a computing circuit configured to quantify the current based on the total number of occurrences that the sense voltage reaches the predetermined voltage threshold and the defined number of the plurality of clock cycles.

3. The current measurement circuit of claim 2, wherein the determination circuit is further configured to combine the reference current with the sense current for a clock cycle duration of the clock signal to reduce the sense voltage below the predetermined voltage threshold.

4. The current measurement circuit of claim 2, wherein the counter is further configured to digitally quantify the total number of occurrences of the sense voltage reaching the predetermined voltage threshold in a binary word having a defined number of bits, and store the binary word in a register.

5. The current measurement circuit of claim 4, wherein the determination circuit is further configured to quantify the current based on the equation: i _{Actual practice is that of} ＝N _Counting *I _{Unit (B)} *C _{Ratio of} Wherein:

I _{actual practice is that of} Representing the current;

N _counting Representing the occurrence of the total number of the sensing voltages reaching the predetermined voltage threshold within the predetermined measurement period;

I _{unit (B)} Bit units representing the current; and

C _{ratio of} Representing the ratio between the current and the sense current.

6. The current measurement circuit of claim 5, wherein the predetermined measurement period is determined based on the following equation: t (T) _{Measurement of} ＝N _{Maximum value} *T _Clock Wherein:

T _{measurement of} Representing the predetermined measurement period;

N _{maximum value} Equal to 2L, where L represents the defined number of bits of the binary word; and

T _Clock representing the clock cycle duration of the clock signal.

7. The current measurement circuit of claim 6, wherein the predetermined voltage threshold is determined based on the following equation:

V ₁ ＝V ₀ +(N _counting *I _{Unit (B)} *T _Clock )/(C0*C _{Ratio of} ) Wherein:

V ₁ representing the predetermined voltage threshold;

V ₀ an initial voltage level representing the sense voltage at the beginning of the predetermined measurement period; and

c0 represents the capacitance of the capacitor.

8. The current measurement circuit of claim 7, wherein the reference current is determined based on the following equation: i _{Reference to} ＝N _{Maximum value} *I _{Unit (B)} /C _{Ratio of} Wherein I _{Reference to} Representing the reference current.

9. The current measurement circuit of claim 1, wherein the determination circuit is further configured to determine an average value of the current over an extended measurement period that is longer than the predetermined measurement period.

10. The current measurement circuit of claim 9, wherein the determination circuit is further configured to:

counting each occurrence of the sensed voltage reaching the predetermined voltage threshold for the extended measurement period;

reducing the sensing voltage below the predetermined voltage threshold each time the sensing voltage reaches the predetermined voltage threshold occurs within the extended measurement period;

counting a total number of clock cycles of the plurality of clock cycles occurring within the extended measurement period; and

the average value of the current is quantified based on a total number of occurrences of the sense voltage reaching the predetermined voltage threshold over the extended measurement period and a total number of occurrences of the clock period over the extended measurement period.

11. The current measurement circuit of claim 10, wherein the determination circuit comprises:

a counter configured to count each occurrence of the sense voltage reaching the predetermined voltage threshold for the extended measurement period;

a reference current generator configured to generate a reference current flowing in an opposite direction with respect to the sense current in response to the sense voltage reaching the predetermined voltage threshold;

a second counter configured to count a total number of clock cycles of the plurality of clock cycles occurring within the extended measurement period;

a latch configured to latch a total number of the clock cycles occurring within the extended measurement period; and

a computing circuit configured to quantify the average value of the current based on the total number of occurrences of the sense voltage reaching the predetermined voltage threshold over the extended measurement period and the total number of occurrences of the clock period over the extended measurement period.

12. The current measurement circuit of claim 10, wherein the determination circuit is further configured to quantify the average value I of the current based on the equation _{Average of} ＝(N _Counting *N _{Maximum value} *I _{Unit (B)} )/(T _Counting *C _{Ratio of} ) Wherein:

I _{average of} Representing the average value of the current;

N _counting Representing the total number of occurrences of the sense voltage reaching the predetermined voltage threshold over the extended measurement period;

N _{maximum value} Equal to 2 ^L Wherein L represents a defined number of bits for digitally quantizing the current;

I _{unit (B)} Bit units representing the current;

T _counting Representing a total number of the clock cycles occurring within the extended measurement period; and

C _{ratio of} Representing the ratio between the current and the sense current.

13. The current measurement circuit of claim 9, wherein the determination circuit is further configured to:

counting a selected number of clock cycles of the plurality of clock cycles occurring within the extended measurement period; and

the average value of the current is quantified based on the total number of occurrences of the sensed voltage reaching the predetermined voltage threshold over the extended measurement period and a selected number of the clock cycles occurring over the extended measurement period.

14. The current measurement circuit of claim 13, wherein the determination circuit comprises:

a latch configured to latch a selected number of the clock cycles occurring within the extended measurement period;

a computing circuit configured to quantify the average value of the current based on the total number of occurrences of the sense voltage reaching the predetermined voltage threshold over the extended measurement period and a selected number of the clock cycles occurring over the extended measurement period.

15. The current measurement circuit of claim 13, wherein the determination circuit is further configured to quantify the average value of the current based on the equation: i _{Average of} ＝(N _Counting *N _{Maximum value} *I _{Unit (B)} )/(T _Counting *C _{Ratio of} ) Wherein:

I _{average of} Representing the average value of the current;

I _{unit (B)} Bit units representing the current;

T _counting Representing a selected number of said clock cycles occurring within said extended measurement period; and

C _{ratio of} Representing the ratio between the current and the sense current.

16. The current measurement circuit of claim 15, wherein the selected number of the clock cycles is determined based on the following equation: t (T) _Counting ＝2 ^K Wherein K is greater than or equal to the defined number of bits (K.gtoreq.L) for digitally quantifying the current.

17. The current measurement circuit of claim 9, wherein the extended measurement period comprises an integer number of the predetermined measurement periods.

18. The current measurement circuit of claim 17, wherein an integer number of the predetermined measurement periods corresponds to an integer number of Orthogonal Frequency Division Multiplexing (OFDM) symbols or time slots.

19. The current measurement circuit of claim 9, wherein the extended measurement period comprises a non-integer number of the predetermined measurement periods.

20. The current measurement circuit of claim 9, wherein the determination circuit is further configured to determine an average power corresponding to the average value of the current over the extended measurement period.