CN111324572A - Chip adopting heterogeneous system - Google Patents

Abstract

The present application discloses a chip using a heterogeneous system. The chip includes: a CPU; a first input/output interface, which is connected to a special chip of the narrowband Internet of Things NB-IoT protocol; a second input/output interface, which is connected to a special chip of the grade CATM protocol; data channel processing DSP chip, and The first input/output interface is connected to the second input/output interface and the CPU, and according to the control instruction sent by the CPU, the channel from the first input/output interface or the second input/output interface is performed. processing; wherein, the capacity of at least one of the data tightly coupled memory, the instruction tightly coupled memory and the first level buffer in the DSP chip is configured according to the hardware requirements of the DSP according to the CATM protocol.

Description

Chips with Heterogeneous Systems

technical field

The present application relates to the field of information processing, in particular to a chip using a heterogeneous system.

Background technique

With the development of communication and network technology, the use of new process technologies and methods of integrating multi-core processors have been widely used to enhance the computing performance of processors. However, as the manufacturing process gradually approaches the physical limit, the development cost of each chip gradually increases, and the traditional reliance on continuous squeezing processes and integrated multi-core processors to obtain computing performance gradually weakens. In this case, people began to hope that by changing Design, focusing on optimizing efficiency to obtain the maximum performance of the current processor architecture as much as possible.

The most primitive SOC architecture is to use a single CPU or CPU cluster to process all business. This is homogeneous computing, which uses the same type of instruction set and architecture to process all tasks. But isomorphic computing has limitations. The micro-architecture of the CPU determines that the CPU's expertise is to handle control services such as branch prediction, out-of-order execution, and storage access. Since there are few computing units in the CPU, parallel computing of a large amount of data, multiply-accumulate computing, etc., can only be achieved by increasing the operating frequency of the CPU or increasing the number of CPUs. However, these two methods have high requirements on the process, so they will increase the power consumption and cost of the CPU at the same time. In order to solve this problem, heterogeneous computing is introduced, that is, a method of implementing parallel processing with computing units of different types of instruction sets and architectures. Heterogeneous computing systems are as follows:

1. Heterogeneous system of CPU+GPU. This heterogeneous system makes full use of the control business capability of the CPU and the parallel processing capability of the GPU to improve the computing performance of the entire system. A typical AMD is a heterogeneous system with CPU+GPU. However, because the algorithms of the GPU are less related, if the algorithms used are not serial, the GPU cannot exert the parallel computing power well.

2. Heterogeneous system of CPU+FPGA. FPGA not only supports data parallelism, but also supports pipeline parallelism, which solves the problems of GPU. Intel's typical CPU embedded FPGA implements this heterogeneous system architecture. But at the same time, the price of a single FPGA is expensive, and the cost of mass production will increase. For small companies in the market, it is not feasible to use CPU+FPGA chips.

In order to balance the shortcomings of the above two typical architectures, ASIC will be the trend of heterogeneous computing.

The Internet of Things (IoT) was first mentioned in 1999, that is, through radio frequency identification (RFID, RFID + Internet), infrared sensors, global positioning systems, laser scanners, gas sensors and other information sensing devices, According to the agreed protocol, any item is connected to the Internet for information exchange and communication, so as to realize intelligent identification, positioning, tracking, monitoring and management of a network. Simply put, the Internet of Things is the Internet of things connected.

The CAT-M1 (category, level) and NB-IoT (Narrow Band Internet of Things, Narrow Band Internet of Things) standards formulated by 3GPPR13 are the two most popular standards in the current Internet of Things technology. Both CAT-M1 and NB-IoT are considered to be the most potential IoT technologies. These two technologies are suitable for different application scenarios, but many people generally believe that NB-IoT is better than CAT in terms of coverage, cost and power consumption. -M1 has more advantages, and the IoT chips currently appearing in the chip market are also based on the NB-IoT standard. However, some data show that CAT-M1 is actually better than NB-IoT in terms of coverage and power consumption, and the rate of CATM-M1 is higher. Therefore, IoT chips based on the CAT-M1 standard will appear in the near future.

At present, the IoT chip we have successfully completed is based on the NB-IoT standard, and we are pre-researching and evaluating the IoT chip of CATM. In the age of IoT, with digital transformation, it needs to be more agile to connect and also to process data more efficiently.

SUMMARY OF THE INVENTION

In order to solve the above technical problems, the present application provides a chip using a heterogeneous system, which can reduce the hardware cost of the chip on the premise of ensuring performance.

In order to achieve the purpose of the application, the application provides a chip using a heterogeneous system, including:

CPU;

The first input/output interface is connected to the dedicated chip of the NB-IoT protocol;

The second input/output interface is connected with the dedicated chip of the CATM protocol;

The data channel processing DSP chip is connected with the first input/output interface and the second input/output interface and the CPU, and according to the control instruction sent by the CPU, the data from the first input/output interface or the second input/output interface is The channel of the input/output interface is processed;

Wherein, the capacity of at least one of the data tightly coupled memory, the instruction tightly coupled memory and the first level buffer in the DSP chip is configured according to the hardware requirements of the DSP according to the CATM protocol.

In an exemplary embodiment, the number of the data tightly coupled memory and/or the instruction tightly coupled memory is at least two;

Wherein, when running the dedicated chip of the NB-IoT protocol, a part of the data tightly coupled memory and/or the instruction tightly coupled memory is in a working state, and the rest is in a closed state; when running the dedicated chip of the CATM protocol, All of the data tightly coupled memory and/or the instruction tightly coupled memory are in a working state.

In an exemplary embodiment, when a dedicated chip of the NB-IoT protocol is running, the first level buffer is in a closed state; the second buffer is in a working state.

In an exemplary embodiment, the signal frequency of the DSP includes a first frequency and a second frequency; wherein the first frequency is within a preset low frequency range, and the second frequency is within a preset high frequency range ;

When running the dedicated chip of the NB-IoT protocol, the DSP uses the first frequency to process the data received by the first input/output interface; when running the dedicated chip of the CATM protocol, the DSP uses the second frequency to process the data received by the first input/output interface. The data input from the second input/output interface is processed.

In an exemplary embodiment, the chip further includes:

The controller controls one of the dedicated chip of the NB-IoT protocol and the dedicated chip of the CATM protocol to be in a working state.

In an exemplary embodiment, the CPU, the DSP and the system-on-chip of peripherals constitute a first chip, and are connected to the dedicated chip of the NB-IoT protocol through a reserved first input/output interface, The reserved second input/output interface is connected with the dedicated chip of the CATM protocol.

In an exemplary embodiment, the first chip further includes:

Memory, which stores the configuration information of the dedicated chip for the NB-IoT protocol and/or the dedicated chip for the CATM protocol;

Wherein, the CPU configures the dedicated chip of the NB-IoT protocol and/or the dedicated chip of the CATM protocol by using the configuration information in the memory.

In an exemplary embodiment, the first chip, the dedicated chip for the NB-IoT protocol, and the dedicated chip for the CATM protocol are packaged together.

In an exemplary embodiment, the first chip further includes:

One or at least two input/output interfaces, wherein each input/output interface is connected to a dedicated chip corresponding to a standard or algorithm;

Wherein, the CPU controls the connection state between the dedicated chip corresponding to the standard or the algorithm and the corresponding input/output interface.

In an exemplary embodiment, the first chip further includes:

a memory, storing configuration information of the dedicated chip corresponding to the standard or algorithm;

The CPU configures the dedicated chip corresponding to the standard or algorithm by using the configuration information in the memory.

In the embodiment provided in this application, the special chip of the NB-IoT protocol and the special chip of the CATM protocol are connected through two input interfaces, so as to realize the purpose of realizing the functions required by the two protocols on one chip, and realize that the two special chips use the same group The purpose of CPU and DSP saves the hardware cost. In addition, by adjusting the hardware capacity in the DSP, the performance of the CATM protocol during operation is effectively guaranteed, and the hardware cost of the chip is reduced on the premise of ensuring the hardware performance of the chip. .

Other features and advantages of the present application will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the present application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the description, claims and drawings.

Description of drawings

The accompanying drawings are used to provide a further understanding of the technical solutions of the present application, and constitute a part of the specification. They are used to explain the technical solutions of the present application together with the embodiments of the present application, and do not constitute a limitation on the technical solutions of the present application.

1 is a structural diagram of a chip using a heterogeneous system provided by the present invention;

2 is a schematic diagram of a heterogeneous system of the Internet of Things based on the NB-IoT standard in the related art;

3 is a schematic diagram of a heterogeneous system of the Internet of Things of the CATM standard provided by the present application;

4 is a schematic diagram of a CPU+DSP+ASIC heterogeneous IoT system provided by the present application;

FIG. 5 is a schematic diagram of a CPU+DSP+ASIC heterogeneous system provided by the present application.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present application clearer, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that, the embodiments in the present application and the features in the embodiments may be arbitrarily combined with each other if there is no conflict.

The steps shown in the flowcharts of the figures may be performed in a computer system, such as a set of computer-executable instructions. Also, although a logical order is shown in the flowcharts, in some cases the steps shown or described may be performed in an order different from that herein.

FIG. 1 is a structural diagram of a chip using a heterogeneous system provided by the present invention. The chip shown in Figure 1 includes:

CPU;

The first input/output interface is connected to the dedicated chip of the NB-IoT protocol;

The second input/output interface is connected with the dedicated chip of the CATM protocol;

The data channel processing DSP chip is connected with the first input/output interface and the second input/output interface and the CPU, and according to the control instruction sent by the CPU, the data from the first input/output interface or the second input/output interface is The channel of the input/output interface is processed;

Wherein, the capacity of at least one of the data tightly coupled memory, the instruction tightly coupled memory and the first level buffer in the DSP chip is configured according to the hardware requirements of the DSP according to the CATM protocol.

In this exemplary embodiment, the dedicated chip of the NB-IoT protocol and the dedicated chip of the CATM protocol are connected through two input interfaces, so as to realize the purpose of realizing the functions required by the two protocols on one chip; after confirming that the chip can execute the NB-IoT protocol When there are two protocols, IoT and CATM, obtain the demand information of the above two protocols on the physical layer DSP, and select the demand information with high DSP performance for hardware configuration. For example, the peak rate of CATM is 375Kbps, and the peak rate of NB is about 50Kbps. Therefore, CATM has higher requirements on the performance of DSP. From the hardware configuration of DSP, on the one hand, the capacity of Tightly Coupled Memories (TCM) can be increased, so that the advantages of TCM can be fully utilized, and the delay of accessing memory can be reduced to improve the overall performance; on the other hand, a Level cache capacity, so that dynamic access to external memory can improve instruction fetch performance and reduce the area of on-chip storage. The increased size of these two aspects is balanced by software requirements and performance.

The cost of increasing the hardware performance of the DSP is lower than the cost of adding a CPU and a DSP. Therefore, the hardware cost is reduced on the premise of ensuring the hardware performance.

In the chip embodiment provided in this application, the special chip of the NB-IoT protocol and the special chip of the CATM protocol are connected through two input interfaces, so as to realize the purpose of realizing the functions required by the two protocols on one chip, and realize that the two special chips use the same chip. The purpose of combining CPU and DSP saves the hardware cost. In addition, by adjusting the hardware capacity in the DSP, the performance of the CATM protocol during operation is effectively guaranteed, and the hardware performance of the chip is guaranteed, and the hardware performance of the chip is reduced. cost.

The technical features provided by the application are described below:

In an exemplary embodiment, the number of the data tightly coupled memory and/or the instruction tightly coupled memory is at least two;

Wherein, when running the dedicated chip of the NB-IoT protocol, a part of the data tightly coupled memory and/or the instruction tightly coupled memory is in a working state, and the rest is in a closed state; when running the dedicated chip of the CATM protocol, All of the data tightly coupled memory and/or the instruction tightly coupled memory are in a working state.

In this exemplary embodiment, the number of the data tightly coupled memory and/or the instruction tightly coupled memory is at least two, the purpose is to ensure that when the dedicated chip of the CATM protocol is running, the hardware performance of the chip is provided by the present application , and when running the dedicated chip of the NB-IoT protocol, there is no problem of insufficient performance. Therefore, a part of the data tightly coupled memory and/or the instruction tightly coupled memory is in a working state, and the rest is in a closed state. , reduce the power consumption of the chip.

In an exemplary embodiment, when a dedicated chip of the NB-IoT protocol is running, the first level buffer is in a closed state; the second buffer is in a working state.

In this exemplary embodiment, the setting of the first-level buffer is to ensure that the application provides the hardware performance of the chip when running the dedicated chip of the CATM protocol, but does not need a dedicated chip when running the dedicated chip of the NB-IoT protocol. The first-level buffer can be closed to reduce the power consumption of the chip.

In an exemplary embodiment, the signal frequency of the DSP includes a first frequency and a second frequency; wherein the first frequency is within a preset low frequency range, and the second frequency is within a preset high frequency range ;

When running the dedicated chip of the NB-IoT protocol, the DSP uses the first frequency to process the data received by the first input/output interface; when running the dedicated chip of the CATM protocol, the DSP uses the second frequency to process the data received by the first input/output interface. The data input from the second input/output interface is processed.

By setting the signal frequency of the DSP to be adjustable, it is convenient for the above two protocols to work in the required signal frequency, and the working performance of the chip is guaranteed.

In an exemplary embodiment, the chip further includes:

The controller controls one of the dedicated chip of the NB-IoT protocol and the dedicated chip of the CATM protocol to be in a working state.

In this exemplary embodiment, the controller may be a software module integrated on the CPU, thereby effectively controlling the hardware cost of the chip.

When using the NB-IOT protocol, use dtcm0 and itcm0. In this scenario, dctm1 and itcm1 are in shutdown mode to reduce power consumption. Whether the first-level cache icache and dcache are used depends on software requirements. If they are not used, the corresponding storage is also in shutdown mode. When using the CATM protocol, use dtcm0+dtcm1, itcm0+itcm1 and icache+dcache.

In an exemplary embodiment, the CPU, the DSP and the system-on-chip of peripherals constitute a first chip, and are connected to the dedicated chip of the NB-IoT protocol through a reserved first input/output interface, The reserved second input/output interface is connected with the dedicated chip of the CATM protocol.

In an exemplary embodiment, the first chip further includes:

Memory, which stores the configuration information of the dedicated chip for the NB-IoT protocol and/or the dedicated chip for the CATM protocol;

Wherein, the CPU configures the dedicated chip of the NB-IoT protocol and/or the dedicated chip of the CATM protocol by using the configuration information in the memory.

In an exemplary embodiment, the first chip, the dedicated chip for the NB-IoT protocol, and the dedicated chip for the CATM protocol are packaged together.

The network access technology standards defined by 3GPP range from LTE CAT1 to CAT10. The evolution of the standard has different application scenarios, but only involves some hardware logic changes and related software changes. For some hardware logic changes, it can also be made into a dedicated ASIC chip and connected to the fixed chip. As shown in Figure 4. In this way, the chip cost for optimizing protocol evolution can also be reduced.

In an exemplary embodiment, in the chip design stage, the fixed chip is designed separately from the dedicated chip based on the NB IoT algorithm, and IO interfaces are reserved on both chips. The NB-specific chip is only used to implement algorithms and standards, and its area is not large, so it has the advantage of repeatable design. The configuration of the NB-specific chip is done in the fixed chip. When packaging, the two are sealed together through the IO port. When 3GPPR14 updates the NB standard, only the NB-specific chip can be redesigned and then repackaged. This reduces the design complexity and cost of chip optimization.

In an exemplary embodiment, in the chip design stage, the fixed chip and the two dedicated chips are designed separately, and IO interfaces are reserved on each chip. The two special-purpose chips are used to implement the algorithms and standards of NB and CATM respectively. The area itself is not large, and it has the advantage of repeatable design. The configuration of the special chip is done in the fixed chip, and the fixed chip and the two special chips are sealed through the IO port during packaging. Because the actual application scenarios of different standards or algorithms are different, the CPU can be used flexibly during the actual use of the chip, and the configuration file in the fixed chip can be configured by software to select the special chip corresponding to the standard or algorithm of NB or CATM.

In an exemplary embodiment, the first chip further includes:

One or at least two input/output interfaces, wherein each input/output interface is connected to a dedicated chip corresponding to a standard or algorithm;

Wherein, the CPU controls the connection state between the dedicated chip corresponding to the standard or the algorithm and the corresponding input/output interface.

In an exemplary embodiment, the first chip further includes:

a memory, storing configuration information of the dedicated chip corresponding to the standard or algorithm;

The CPU configures the dedicated chip corresponding to the standard or algorithm by using the configuration information in the memory.

In an exemplary embodiment, in the chip design stage, the fixed chip is designed separately from a single dedicated chip, and IO interfaces are reserved on both chips. Dedicated chips are only used to implement algorithms and standards. This standard or algorithm is not limited to IoT standards or algorithms. The area itself is not large, and it has the advantage of repeatable design. The configuration of the dedicated chip is done in the fixed chip. When packaging, the two are sealed together through the IO port. When standards or algorithms are updated, only the dedicated chip can be redesigned and then repackaged. This reduces the design complexity and cost of chip optimization.

In an exemplary embodiment, in the chip design stage, the fixed chip is designed separately from a plurality of dedicated chips, and IO interfaces are reserved on each chip. Multiple dedicated chips are used to implement different algorithms and standards, which are not limited to IoT standards or algorithms. The area itself will not be too large, and it has the advantage of repeatable design. The configuration of the special chip is done in the fixed chip, and the fixed chip and the special chip are sealed together through the IO interface before packaging. Because the actual application scenarios of different standards or algorithms are different, the CPU can be flexibly used in the actual chip use process, and the configuration files in the fixed chip can be configured by software to select the dedicated chips corresponding to different standards or algorithms.

The hardware structure provided by this application is described below:

Based on the above mentioned IoT chip and heterogeneous computing system, the present invention proposes a heterogeneous IoT chip system based on CPU+DSP+ASIC.

Figure 2 is a schematic diagram of an IoT heterogeneous system based on the NB-IoT standard in the related art; as shown in Figure 2, the IoT chip is a heterogeneous system based on the NB-IoT standard and using a CPU+DSP. Among them, the CPU mainly handles the control business, the DSP mainly handles the operation business of the protocol stack and the physical layer, and the IoT hardware module is hung on the bus to realize the NB-IoT protocol.

FIG. 3 is a schematic diagram of an IoT heterogeneous system of the CATM standard provided by the present application. As shown in Figure 3, the next-generation IoT chip is formulated based on the CATM standard. Compared with the chip of the NB-IoT standard, the difference lies in: the implementation of the IoT protocol hardware is different, the physical layer software processing is different, and the physical layer processor is different. DSP needs are different.

In addition to the programmable factor of the software part, the hardware difference is shown in the dotted box part in Figure 3. The implementation of the protocol is different in the IoT hardware module and the different requirements for DSP. The reason for the above difference is that the coverage and speed of CATM are higher, and the requirements for processor computing power are higher. After the cause is determined, the present application improves instruction fetch efficiency and computing performance by adding a level-one cache or a tightly coupled memory.

The following describes the application examples provided by the embodiments of the present invention:

Figure 4 is a schematic diagram of a CPU+DSP+ASIC heterogeneous IoT system provided by the application; as shown in Figure 4, the functions of each module are as follows:

CPU: Processes application layer control services.

DSP: handles protocol stack and physical layer operation services, where dtcm0, dtcm1, itcm0, and itcm1 are data tightly coupled memory and instruction tightly coupled memory respectively.

Peripheral: Peripheral part, including peripheral IP and external memory.

NB-IoT ASIC: A dedicated chip that implements the NB_IoT standard.

CATM ASIC: A dedicated chip that implements the CATM standard.

Config: Configure the module, configure which internal memory to use, and configure which dedicated chip to use.

When confirming the execution of the NB and CATM protocols, obtain the requirement information of the above two protocols on the physical layer DSP, and select the requirement information with high DSP performance for hardware configuration. For example, the peak rate of CATM is 375Kbps, and the peak rate of NB is about 50Kbps. Therefore, CATM has higher requirements on the performance of DSP. From the hardware configuration of DSP, on the one hand, the capacity of the tightly coupled memory can be increased, so that the advantages of TCM can be fully utilized, and the delay of accessing the memory can be reduced to improve the overall performance; on the other hand, the capacity of the first-level cache can be increased, so that the Dynamic access to external memory can improve instruction fetch performance and reduce on-chip storage area. The increased size of these two aspects is balanced by software requirements and performance.

Figure 5 is a schematic diagram of a CPU+DSP+ASIC heterogeneous system provided by this application. As shown in Figure 5, when the NB-IOT protocol is used, dtcm0 and itcm0 are used. In this scenario, dctm1 and itcm1 are in shutdown power mode to reduce power consumption. Whether the first-level cache icache and dcache are used depends on software requirements. If they are not used, the corresponding storage is also in shutdown mode. When using the CATM protocol, use dtcm0+dtcm1, itcm0+itcm1 and icache+dcache. At the same time, the DSP should do the frequency adjustable function, use high frequency under the CATM protocol, and use low frequency under the NB-IOT protocol.

Among them, the SoC architecture of CPU + DSP + peripherals is used as a separate ASIC 1 chip, and the IO interface for docking with the dedicated chip is reserved, and then the corresponding dedicated ASIC 2 chip is developed according to the current NB-IoT protocol, and the IO interface is reserved. The CATM protocol developed the corresponding dedicated ASIC 3 chip, reserved IO interface, when the chip was packaged, the three chips ASIC1, ASIC2, and ASIC3 were packaged together. Finally, the physical layer software is developed for the CATM and NB protocols respectively. When the chip is made into a product, the application scenario is determined by Config configuration whether to use the NB standard or the CATM standard.

As the IoT standard is still in the process of development, for example, some specifications of the NB standard will be formulated in 3GPPR14, and the current implementation is the R13 standard. For heterogeneous systems using CPU + DSP + ASIC, after the standard is completely determined, only the ASIC dedicated chip of the IoT protocol and the corresponding physical layer software can be updated, and there is no need to remake the chip. At the same time, for different chips of different IoT standards, only the hardware implementation of the IoT standard can be made into a dedicated chip, and then different standards can be selected according to the configuration to apply to different scenarios, so that the common part can remain unchanged. One-generation optimization saves costs. In addition, this heterogeneous system architecture is not limited to IoT chips, but is also applicable to terminal data card chips.

Those of ordinary skill in the art can understand that all or some of the steps in the methods disclosed above, functional modules/units in the systems, and devices can be implemented as software, firmware, hardware, and appropriate combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be composed of several physical components Components execute cooperatively. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer-readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). As is known to those of ordinary skill in the art, the term computer storage media includes both volatile and nonvolatile implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data flexible, removable and non-removable media. Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cartridges, magnetic tape, magnetic disk storage or other magnetic storage devices, or may Any other medium used to store desired information and which can be accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and can include any information delivery media, as is well known to those of ordinary skill in the art .

Claims (10)

1. A chip using a heterogeneous system, comprising: CPU; The first input/output interface is connected to the special chip of the NB-IoT protocol of the narrowband Internet of Things; The second input/output interface is connected with the dedicated chip of the level CATM protocol; The data channel processing DSP chip is connected with the first input/output interface and the second input/output interface and the CPU, and according to the control instruction sent by the CPU, the data from the first input/output interface or the second input/output interface is The channel of the input/output interface is processed; Wherein, the capacity of at least one of the data tightly coupled memory, the instruction tightly coupled memory and the first level buffer in the DSP chip is configured according to the hardware requirements of the DSP according to the CATM protocol. 2. chip according to claim 1, is characterized in that: The number of the data tightly coupled memory and/or the instruction tightly coupled memory is at least two; Wherein, when running the dedicated chip of the NB-IoT protocol, a part of the data tightly coupled memory and/or the instruction tightly coupled memory is in a working state, and the rest is in a closed state; when running the dedicated chip of the CATM protocol, All of the data tightly coupled memory and/or the instruction tightly coupled memory are in a working state. 3. chip according to claim 2, is characterized in that: When running the dedicated chip of the NB-IoT protocol, the first level buffer is in a closed state; the second buffer is in a working state. 4. chip according to claim 1, is characterized in that: The signal frequency of the DSP includes a first frequency and a second frequency; wherein the first frequency is within a preset low frequency range, and the second frequency is within a preset high frequency range; When running the dedicated chip of the NB-IoT protocol, the DSP uses the first frequency to process the data received by the first input/output interface; when running the dedicated chip of the CATM protocol, the DSP uses the second frequency to process the data received by the first input/output interface. The data input from the second input/output interface is processed. 5. The chip according to claim 1, wherein the chip further comprises: The controller controls one of the dedicated chip of the NB-IoT protocol and the dedicated chip of the CATM protocol to be in a working state. 6. chip according to claim 1, is characterized in that: The CPU, the DSP and the peripheral system-level chip form the first chip, and are connected to the dedicated chip of the NB-IoT protocol through the reserved first input/output interface, and the second reserved input/output interface is used. It is connected with the dedicated chip of the CATM protocol. 7. The chip according to claim 6, wherein the first chip further comprises: Memory, which stores the configuration information of the dedicated chip for the NB-IoT protocol and/or the dedicated chip for the CATM protocol; Wherein, the CPU configures the dedicated chip of the NB-IoT protocol and/or the dedicated chip of the CATM protocol by using the configuration information in the memory. 8 . The chip according to claim 1 , wherein the first chip, the dedicated chip of the NB-IoT protocol, and the dedicated chip of the CATM protocol are packaged together. 9 . 9. The chip according to claim 6, wherein the first chip further comprises: One or at least two input/output interfaces, wherein each input/output interface is connected to a dedicated chip corresponding to a standard or algorithm; Wherein, the CPU controls the connection state between the dedicated chip corresponding to the standard or the algorithm and the corresponding input/output interface. 10. The chip according to claim 9, wherein the first chip further comprises: a memory, storing configuration information of the dedicated chip corresponding to the standard or algorithm; The CPU configures the dedicated chip corresponding to the standard or algorithm by using the configuration information in the memory.

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