CN111309482B - Hash algorithm-based block chain task allocation system, device and storable medium - Google Patents
Hash algorithm-based block chain task allocation system, device and storable medium Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
- G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/01—Protocols
- H04L67/10—Protocols in which an application is distributed across nodes in the network
- H04L67/1097—Protocols in which an application is distributed across nodes in the network for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/50—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols using hash chains, e.g. blockchains or hash trees
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The application discloses a block chain task distribution system, a device and a storable medium based on a hash algorithm, which comprise the following components: the task receiving unit is used for receiving task data through the CPU interface control module; the task storage unit is used for judging a task attribution channel through the control module and writing the task attribution channel into a memory of the corresponding channel; the task sending unit is used for obtaining task data in the corresponding memory and sending the task data to the corresponding downlink port according to the sending module where the task sending unit is located; and the task output unit is used for receiving the task calculation result after each downlink port receives the task sending unit data, writing the task calculation result into the memory of the corresponding port, and acquiring the task calculation result in each memory by using a polling mode as output content. In the embodiment of the application, the memory structure in the system is used, so long as the allowance exists in the memory structure, the task receiving and the task sending of a single channel can be simultaneously carried out, the waiting time of a CPU is reduced, and the work efficiency of issuing the CPU task is increased.
Description
Technical Field
The present application relates to the field of software task allocation technologies, and in particular, to a system, an apparatus, and a storable medium for distributing blockchain tasks based on a hash algorithm.
Background
Blockchains are novel application modes of computer technologies such as distributed data storage, point-to-point transmission, consensus mechanisms, encryption algorithms, and the like. The distribution of the blockchain based on the hash algorithm is a tool for carrying out quick hash calculation on the blockchain; the control device for sending the block chain calculation task and receiving the calculation result is based on the hash algorithm.
In the prior art, in task allocation, particularly in a large number of task allocation processes, a large number of processes of a CPU are occupied, so that the situations of untimely transmission and even errors of background calculation tasks are easily caused.
Disclosure of Invention
In order to solve the technical problems, the embodiment of the application provides a block chain task allocation system and device based on a hash algorithm and a storage medium thereof.
A first aspect of the present application provides a system for distributing block chain tasks based on a hash algorithm, which may include:
the task receiving unit is used for receiving task data through the CPU interface control module;
the task storage unit is used for judging a task attribution channel through the control module and writing the task attribution channel into a memory of the corresponding channel;
the task sending unit is used for obtaining task data in the corresponding memory and sending the task data to the corresponding downlink port according to the sending module where the task sending unit is located;
and the task output unit is used for receiving the task calculation result after each downlink port receives the task sending unit data, writing the task calculation result into the memory of the corresponding port, and acquiring the task calculation result in each memory by using a polling mode as output content.
Further, a plurality of home channels are arranged, and each home channel is provided with a memory unit;
the memory unit is used for storing task content and slicing the memory of the corresponding channel according to the number of task bytes.
Further, when the memory unit is sliced, a single task command does not exceed n bytes, the memory is divided into m chip select addresses, each slice of n bytes, and the memory space is allocated as mxn.
Further, each piece of the chip select address includes:
an address sequence number unit;
the storage address unit corresponds to the address sequence number unit;
and the task content unit is internally provided with task content and corresponds to the storage address unit.
Further, in the storage address unit, the sending mode of the command is stored in the storage address 0, the length of the command is stored in the storage address 1, and the contents of the tasks are stored in other addresses of the storage address.
Further, the task transmitting unit includes:
the updating unit reads the stored task data through the control module and distributes and sends the task of the current address block to update;
the transmission mode unit is used for transmitting task content and comprises a single transmission mode unit and an N_TIME transmission mode unit; the single-time transmission mode unit limits the task to be transmitted once; the N_TIME transmit mode unit defines that the task needs to be transmitted N TIMEs.
Further, the single transmission mode unit transmits the task of adding 1 to the address sequence number unit read after one completion and then transmitting the next address sequence number unit.
Further, the n_time transmission mode unit determines whether to need to recalculate each TIME a task is transmitted, if yes, replaces a specific byte of the task, transmits the address sequence number unit read after finishing N TIMEs to be added with 1, and then transmits the task of the next address sequence number unit, otherwise, directly transmits the task.
In a second aspect of the present application, an embodiment of the present application provides a hash algorithm-based task allocation apparatus, including a memory and a processor, where the memory stores computer executable instructions, and the processor implements the system of the first aspect when executing the computer executable instructions on the memory.
In a third aspect, an embodiment of the present application provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the system of the first aspect described above.
In the embodiment of the application, the memory structure in the system is used, so long as the allowance exists in the memory structure, the task receiving and the task sending of a single channel can be simultaneously carried out, the waiting time of a CPU is reduced, and the work efficiency of issuing the CPU task is increased.
Drawings
In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a system block diagram provided by an embodiment of the present application;
FIG. 2 is a flow chart of a system provided by an embodiment of the present application;
FIG. 3 is a diagram illustrating memory space allocation;
FIG. 4 is a flow chart of a task sending unit;
FIG. 5 is a schematic diagram of a task send byte processing flow;
fig. 6 is a schematic structural view of a dispensing device according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It should be understood that the terms "comprises" and "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
As used in this specification and the appended claims, the term "if" may be interpreted as "when..once" or "in response to a determination" or "in response to detection" depending on the context. Similarly, the phrase "if a determination" or "if a [ described condition or event ] is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a [ described condition or event ]" or "in response to detection of a [ described condition or event ]".
The application provides a method for realizing task allocation based on a hash algorithm based on an FPGA.
The FPGA receives task data through the CPU interface control module, judges a task attribution channel through the control module and writes the task attribution channel into a memory of a corresponding channel; each channel transmitting module reads task data in the corresponding memory and transmits the task data to the corresponding downlink port according to the transmitting module; each downlink port receives the task calculation result and writes the task calculation result into the memory of the corresponding port, and the CPU reads the task calculation result in each memory in a polling mode through the CPU interface control module.
In order to implement the above method, as shown in fig. 1, an embodiment of the present application provides a blockchain task allocation system based on a hash algorithm, including: a task receiving unit 310, a task storage unit 320, a task transmitting unit 330, and a task output unit 340.
The task receiving unit 310 is configured to receive task data through the CPU interface control module by using the FPGA.
The task storage unit 320 is configured to determine, by using the control module, a task belonging channel, and write the task belonging channel into the memory of the corresponding channel.
In the whole system, a plurality of home channels are arranged, and each home channel is provided with a memory unit. The memory unit is used for storing task content and dividing the memory of the corresponding channel according to the number of task bytes.
Specifically, when the memory unit is sliced, a single task command does not exceed n bytes, the memory is divided into m chip select addresses, each slice of n bytes, and the memory space is allocated as mxn.
As shown in fig. 3, each chip select address includes:
an address sequence number unit 321;
a memory address unit 322 corresponding to the address sequence number unit;
the transmission mode and the transmission times of the command are stored in the storage address 0, the length of the command is stored in the storage address 1, and the contents of the task are stored in other addresses of the storage address.
The task content unit 323 incorporates task content and corresponds to the storage address unit 322.
By using the structure, as long as the memory has a margin, the task receiving and sending of a single channel can be performed simultaneously, the waiting time of a CPU is reduced, and the work efficiency of issuing the CPU task is increased.
The task storage unit 320 needs to select a corresponding channel and its internal corresponding chip selection address according to the received content immediately after receiving the task data.
The task sending unit 330 is configured to obtain task data in the corresponding memory, and send the task data to the corresponding downlink port according to the sending module where the task data is located.
As a specific embodiment, the task transmitting unit 330 is provided with an update unit 331 for reading stored task data by the control module and distributing and transmitting updates to the tasks of the current address block;
a transmission mode unit 332, configured to transmit task content, including a single transmission mode unit and an n_time transmission mode unit; the single-time transmission mode unit limits the task to be transmitted once, and the single-time transmission mode unit transmits the task of the next address sequence number unit after the address sequence number unit read after the completion of one time is added with 1.
The N_TIME transmitting mode unit limits that the task needs to be transmitted N TIMEs, when the N_TIME transmitting mode unit transmits the task each TIME, the N_TIME transmitting mode unit judges whether the task needs to be recalculated, if the task needs to be recalculated, the specific byte of the task is replaced, the address sequence number unit read after the N TIMEs is transmitted is added with 1, then the task of the next address sequence number unit is transmitted, and otherwise, the task is directly transmitted.
The sending task is generated by the FPGA based on the initial task through a specific algorithm and sent to the downlink chip, and each task does not need to be sent to the FPGA by a CPU and then sent to the downlink chip by the FPGA; the mode accelerates task allocation and transmission, simultaneously releases CPU processes, greatly reduces the transmission time of the tasks under the condition of N channels, and avoids calculation errors and repeated calculation caused by the time-out of the task transmission of a downlink calculation chip, thereby influencing the efficiency; meanwhile, the time for receiving and processing the task calculation result by the CPU is increased, and the situation that the task result is lost due to insufficient time for processing the calculation result is avoided;
the task output unit 340 is configured to receive the task calculation result after each downlink port receives the task sending unit data, write the task calculation result into the memory of the corresponding port, and acquire the task calculation result in each memory as output content in a polling mode.
Fig. 6 is a schematic structural view of a dispensing device according to an embodiment of the present application. The object detection device 4000 comprises a processor 41 and may further comprise input means 42, output means 43 and a memory 44. The input device 42, the output device 43, the memory 44 and the processor 41 are interconnected by a bus.
The memory includes, but is not limited to, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), or portable read-only memory (CD-ROM) for the relevant instructions and data.
The input means is for inputting data and/or signals and the output means is for outputting data and/or signals. The output device and the input device may be separate devices or may be a single device.
A processor may include one or more processors, including for example one or more Central Processing Units (CPUs), which in the case of a single CPU may be a single core CPU or a multi-core CPU. The processor may also include one or more special purpose processors, which may include GPUs, FPGAs, etc., for acceleration processing.
The memory is used to store program codes and data for the network device.
The processor is used to call the program code and data in the memory to perform the steps of the method embodiments described above. Reference may be made specifically to the description of the method embodiments, and no further description is given here.
It will be appreciated that fig. 6 shows only a simplified design of the object detection device. In practical applications, the motion recognition device may also include other necessary elements, including but not limited to any number of input/output devices, processors, controllers, memories, etc., and all the motion recognition devices that can implement the embodiments of the present application are within the protection scope of the present application.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.
In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the division of the unit is merely a logic function division, and there may be another division manner when actually implemented, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted or not performed. The coupling or direct coupling or communication connection shown or discussed with each other may be through some interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in or transmitted across a computer-readable storage medium. The computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital Subscriber Line (DSL)), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a read-only memory (ROM), or a random-access memory (RAM), or a magnetic medium, such as a floppy disk, a hard disk, a magnetic tape, a magnetic disk, or an optical medium, such as a Digital Versatile Disk (DVD), or a semiconductor medium, such as a Solid State Disk (SSD), etc.
The preferred embodiments of the present application have been described in detail above, but the present application is not limited to the specific details of the above embodiments, and various equivalent changes (such as number, shape, position, etc.) may be made to the technical solution of the present application within the scope of the technical concept of the present application, and these equivalent changes all belong to the protection of the present application.
Claims (6)
1. A hash algorithm-based blockchain tasking system, comprising:
the task receiving unit is used for receiving task data through the CPU interface control module;
the task storage unit is used for judging a task attribution channel through the control module and writing the task attribution channel into a memory of the corresponding channel; the number of the home channels is multiple, and each home channel is provided with a memory unit; the memory unit is used for storing task content and slicing the memory of the corresponding channel according to the number of task bytes; when the memory unit is fragmented, a single task command does not exceed n bytes, the memory is divided into m chip selection addresses, each n bytes, and the memory space is allocated as mxn; each piece of the chip select address comprises: an address sequence number unit; the storage address unit corresponds to the address sequence number unit; the task content unit is internally provided with task content and corresponds to the storage address unit;
the task sending unit is used for obtaining task data in the corresponding memory and sending the task data to the corresponding downlink port according to the sending module where the task sending unit is located; the task transmitting unit includes:
the updating unit reads the stored task data through the control module and distributes and sends the task of the current address block to update;
the transmission mode unit is used for transmitting task content and comprises a single transmission mode unit and an N_TIME transmission mode unit; the single-time transmission mode unit limits the task to be transmitted once; the N_TIME transmitting mode unit limits that the task needs to be transmitted N TIMEs;
and the task output unit is used for receiving the task calculation result after each downlink port receives the task sending unit data, writing the task calculation result into the memory of the corresponding port, and acquiring the task calculation result in each memory by using a polling mode as output content.
2. The hash algorithm-based blockchain task allocation system of claim 1, wherein in the storage address unit, the transmission mode of the command is stored in the storage address 0, the length of the command is stored in the storage address 1, and the contents of the tasks are stored in other addresses.
3. The hash algorithm-based blockchain tasking system of claim 1 wherein the single transmission mode unit transmits the task of the next address sequence number unit after the address sequence number unit read once is added 1.
4. The hash algorithm-based blockchain task allocation system according to claim 3, wherein the n_time transmission mode unit determines whether recalculation is required each TIME a task is transmitted, if recalculation is required, replaces a specific byte of the task, transmits a read address sequence number unit after completing N TIMEs by adding 1, and then transmits a task of a next address sequence number unit, otherwise directly transmits the task.
5. A hash algorithm based task allocation device comprising a memory having stored thereon computer executable instructions and a processor which when executing the computer executable instructions on the memory implements the system of any of claims 1-4.
6. A computer readable storage medium, characterized in that a computer program is stored thereon, which computer program, when being executed by a processor, implements the system of any of the preceding claims 1-4.
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