CN111293098A - Embedded chip package and method of making the same and stacked package structure - Google Patents

Abstract

The invention provides an embedded chip package, a manufacturing method thereof and a laminated packaging structure. The circuit board comprises a glass substrate and at least one conductive through hole. The glass substrate is provided with a first surface, a second surface opposite to the first surface and a through groove penetrating through the glass substrate. The conductive through hole penetrates through the glass substrate. The chip is arranged in the through groove. The dielectric material layer is filled in the through groove and covers the chip. The build-up circuit structure is configured on the circuit board. The build-up circuit structure is electrically connected with the conductive through hole. The lower surface of the chip is exposed outside the dielectric material layer.

Description

Embedded chip package and method of making the same and stacked package structure

technical field

The invention relates to a chip package, a manufacturing method and a stacked package structure, in particular to an embedded chip package, a manufacturing method and a stacked package structure.

Background technique

The current chip packaging methods all require a layer of packaging adhesive to protect the chip, and then continue to add layers of other circuits or perform packaging in a two-dimensional direction. Then, the stacking and assembly at this time tend to cause large warpage, which in turn affects the packaging yield and subsequent reliability.

SUMMARY OF THE INVENTION

The invention provides an embedded chip package with better package yield and reliability.

The present invention provides a stacked package structure with the benefit of adding stack structures and circuits.

The present invention provides a manufacturing method of an embedded chip package, so as to manufacture the aforementioned embedded chip package, which can improve the warpage problem caused by the build-up circuit or the package.

The embedded chip package of the present invention includes a circuit board, a chip, a dielectric material layer and a build-up circuit structure. The circuit board includes a glass substrate and at least one conductive through hole. The glass substrate has a first surface, a second surface opposite to the first surface, and a through groove penetrating the glass substrate. The conductive vias penetrate through the glass substrate. The chip is arranged in the through slot. The dielectric material layer is filled in the through groove and covers the chip. The build-up circuit structure is arranged on the circuit board. The build-up circuit structure is electrically connected with the conductive via. The lower surface of the chip is exposed to the dielectric material layer.

In an embodiment of the present invention, the lower surface of the chip is flush with the second surface of the glass substrate.

In an embodiment of the present invention, the build-up circuit structure described above includes a first circuit layer, a first dielectric layer, a second circuit layer, and at least one first via hole. The first dielectric layer covers the first wiring layer. The second circuit layer and the first circuit layer are respectively located on opposite sides of the first dielectric layer. The first via hole penetrates through the first dielectric layer to electrically connect the first circuit layer and the second circuit layer.

In an embodiment of the present invention, the above-mentioned build-up circuit structure is disposed on the first surface of the glass substrate. The embedded chip package also includes a patterned conductive layer and solder balls or copper pillars. The patterned conductive layer is disposed on the second surface of the glass substrate, so that the build-up circuit structure and the patterned conductive layer are respectively located on opposite sides of the glass substrate. The solder balls or copper pillars are disposed on the patterned conductive layer, so that the solder balls or copper pillars and the circuit board are respectively located on opposite sides of the patterned conductive layer.

In an embodiment of the present invention, the lower surface of the chip is an active surface. The active surface faces the patterned conductive layer and is electrically connected to the patterned conductive layer.

In an embodiment of the present invention, the above-mentioned build-up circuit structure is electrically connected to the patterned conductive layer through conductive vias.

In an embodiment of the present invention, the above build-up circuit structure is disposed on the second surface of the glass substrate. Buried chip packages also include solder balls or copper pillars. The tin balls or copper pillars are disposed on the build-up circuit structure, so that the tin balls or copper pillars and the circuit board are respectively located on opposite sides of the build-up circuit structure.

In an embodiment of the present invention, the lower surface of the chip is an active surface. The active surface faces the build-up line structure and is electrically connected with the build-up line structure.

In an embodiment of the present invention, the above-mentioned through-grooves connect the first surface and the second surface of the glass substrate.

The stacked package structure of the present invention includes a circuit board, at least one embedded chip package (the build-up circuit structure is disposed on the first surface of the glass substrate) (hereinafter referred to as the first embedded chip package), and the embedded chip package described above. Chip package (the build-up circuit structure is arranged on the second surface of the glass substrate) (hereinafter referred to as the second embedded chip package). The first embedded chip package is disposed on the circuit board. The second embedded chip package is disposed on the first embedded chip package. Wherein, the second embedded chip package and the circuit board are respectively located on opposite sides of the first embedded chip package.

In an embodiment of the present invention, the solder balls or copper pillars of the second embedded chip package are electrically connected to the build-up circuit structure of the first embedded chip package. The solder balls or copper pillars of the first embedded chip package are electrically connected to the circuit board.

The manufacturing method of the embedded chip package of the present invention includes the following steps. First, a carrier and a release layer on the carrier are provided. Next, the chip is arranged on the release layer. Configure the circuit board on the release layer. Wherein, the circuit board includes a glass substrate and at least one conductive through hole. The glass substrate has a first surface, a second surface opposite to the first surface, and a through groove penetrating the glass substrate. The conductive vias penetrate through the glass substrate. After arranging the chip and the circuit board on the release layer and embedding the chip in the through groove, a dielectric material layer is formed on the release layer. Wherein, the dielectric material layer is filled in the through groove and covers the chip. Then, the release layer and the carrier are removed to expose the lower surface of the chip to the dielectric material layer. After removing the release layer and the carrier, a build-up circuit structure is formed on the circuit board, so that the build-up circuit structure and the conductive via are electrically connected.

In an embodiment of the present invention, the above-mentioned build-up circuit structure is disposed on the first surface of the glass substrate. The fabrication method of the embedded chip package further includes the following steps. A patterned conductive layer is formed on the second surface of the glass substrate, so that the build-up circuit structure and the patterned conductive layer are respectively located on opposite sides of the glass substrate. Solder balls or copper pillars are formed on the patterned conductive layer, so that the solder balls or copper pillars and the circuit board are respectively located on opposite sides of the patterned conductive layer.

In an embodiment of the present invention, the above build-up circuit structure is disposed on the second surface of the glass substrate. The fabrication method of the embedded chip package further includes the following steps. The solder balls or copper pillars are formed on the build-up circuit structure, so that the solder balls or copper pillars and the circuit board are respectively located on opposite sides of the build-up circuit structure.

Based on the above, in the embedded chip package, the manufacturing method and the stacked package structure of the present invention, the embedded chip package includes a circuit board, a chip, a dielectric material layer and a build-up circuit structure. Wherein, the circuit board includes a glass substrate and conductive through holes, and the glass substrate has a through groove penetrating through the glass substrate. Next, the chip is arranged in the through groove, the dielectric material layer is filled in the through groove, and the build-up circuit structure is arranged on the circuit board. With this design, the manufacturing method of the embedded chip package of the present invention can improve the warpage problem caused by the build-up circuit or the package, so that the embedded chip package of the present invention has better packaging yield and reliability. In addition, the stacked packaging structure of the present invention has the advantage of increasing stacking structures and circuits.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

Description of drawings

1A to 1F are schematic cross-sectional views illustrating a method for fabricating an embedded chip package according to an embodiment of the present invention.

FIG. 1G is a schematic bottom view of the embedded chip package of FIG. 1F .

FIG. 1H is a schematic cross-sectional view of an embedded chip package according to another embodiment of the present invention.

2A to 2B are schematic cross-sectional views illustrating a method for fabricating an embedded chip package according to another embodiment of the present invention.

FIG. 2C is a schematic cross-sectional view of an embedded chip package according to another embodiment of the present invention.

3A-3B are schematic cross-sectional views of side-by-side package structures according to various embodiments of the present invention.

4A to 4B are schematic cross-sectional views of package-on-package structures according to various embodiments of the present invention.

【Symbol Description】

10, 10a: Parallel packaging structure

10b, 10c: Stacked package structure

100, 100a, 100b, 100c: Embedded chip package

110: Carrier

112: Release layer

120: Chip

121: Lower Surface

122: Active Surface

130: circuit board

131: Glass substrate

132: First Surface

133: Second Surface

134: Grooving

135: Conductive Vias

140: Dielectric Material Layer

150, 150b: Build-up circuit structure

151: The first circuit layer

152: First Dielectric Layer

153: Second circuit layer

154: first via hole

155: Second Dielectric Layer

156: second via hole

160: Patterned conductive layer

170, 170a: solder balls

172, 172a: Copper pillars

200, 200a, 200b, 200c: circuit boards

Detailed ways

The foregoing and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of the embodiments with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as "up", "down", "front", "rear", "left", "right", etc., only refer to the directions of the attached drawings. Accordingly, the directional terms used are intended to illustrate rather than limit the present invention.

In the detailed description of various embodiments, terms such as "first," "second," "third," and "fourth" may be used to describe different elements. These terms are only used to distinguish elements from each other, but in structure, these elements should not be limited by these terms. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element without departing from the scope of the present inventive concept. In addition, in the manufacturing method, except for a specific manufacturing process, the formation sequence of these elements or components should not be limited by these terms. For example, the first element may be formed before the second element. Alternatively, the first element may be formed after the second element. Alternatively, the first element and the second element may be formed in the same fabrication or step.

Also, the thicknesses of layers and regions in the drawings may be exaggerated for clarity. The same or similar reference numerals denote the same or similar elements, which will not be repeated in the following paragraphs.

1A to 1F are schematic cross-sectional views illustrating a method for fabricating an embedded chip package according to an embodiment of the present invention. FIG. 1G is a schematic bottom view of the embedded chip package of FIG. 1F . For clarity and convenience of description, the patterned conductive layer 160 and the solder balls 170 are omitted in FIG. 1G .

Referring to FIG. 1A , a carrier 110 and a release layer 112 disposed on the carrier 110 are provided first, and then a chip 120 is disposed on the release layer 112 . In this embodiment, the carrier 110 may be a metal substrate, a silicon substrate, a glass substrate, a ceramic substrate, or other suitable carriers that can be used for support. The release layer 112 may be formed of a polymer-based material, which may be removed together with the carrier 110 in a subsequent step. In some embodiments, the release layer 112 is an epoxy-based heat release material that loses its adhesive properties when heated, such as a light-to-heat-conversion (LTHC) release coating. In other embodiments, the release layer 112 may be an ultra-violet (UV) glue that loses its adhesive properties when exposed to UV light. The release layer 112 may be dispensed and cured as a liquid, the release layer 112 may be a laminate film laminated to the carrier 110, or may be in other forms.

Referring to FIG. 1B , the circuit board 130 is disposed on the release layer 112 . In this embodiment, the circuit board 130 includes a glass substrate 131 and at least one conductive via 135 . The glass substrate 131 has a first surface 132 , a second surface 133 opposite to the first surface 132 , and a through hole 134 penetrating the glass substrate 131 . In some embodiments, the through groove 134 connects the first surface 132 and the second surface 133 of the glass substrate 131 .

Next, the conductive vias 135 may be formed by the following steps, but not limited thereto. First, the glass substrate 131 is drilled by a laser or machining method to form through holes through the glass substrate 131 . The through hole connects the first surface 132 and the second surface 133 . Then, a seed layer (not shown) is formed in the through hole, and a conductive material (not shown) is formed in the through hole by electroplating, thereby forming a conductive through hole 135 penetrating the glass substrate 131 . Here, the conductive material may be a metal or metal alloy, such as copper, titanium, tungsten, aluminum, etc., or a combination thereof.

It should be noted that although in this embodiment, the chip 120 is first arranged on the release layer 112 , and then the circuit board 130 is arranged on the release layer 112 , and the through grooves 134 of the circuit board 130 are aligned with the chip 120 , so that the chip 120 is embedded in the through groove 134 of the circuit board 130 , but not limited thereto. That is to say, in other embodiments, the circuit board 130 may be disposed on the release layer 112 first, and then the chip 120 may be disposed on the release layer 112 , and the chip 120 may be embedded in the through groove of the circuit board 130 . within 134.

In addition, in this embodiment, the thickness of the circuit board 130 and the thickness of the chip 120 may be the same or different, which are not limited in the present invention. In addition, although the size of the through groove 134 and the chip 120 is not limited in this embodiment, it should be noted that the cross-sectional area of the through groove 134 of the circuit board 130 needs to be larger than the cross-sectional area of the chip 120 to make the chip 120 suitable Embedded in the through groove 134 of the circuit board 130 .

Next, referring to FIG. 1C , after the chip 120 and the circuit board 130 are disposed on the release layer 112 and the chip 120 is embedded in the through groove 134 , a dielectric material layer 140 is formed on the release layer 112 , so that the The dielectric material layer 140 is filled in the through groove 134 and covers the chip 120 . In this embodiment, for example, resin (eg: epoxy resin), silane (eg: hexamethyldisiloxane (HMDSN), tetraethoxysilane (TEOS), bis- Dimethylamine dimethylsilane (bis(dimethylamino)dimethylsilane; BDMADMS)) or other suitable dielectric materials are coated on the release layer 112 and cured to form the dielectric material layer 140 . Therefore, the dielectric material layer 140 can be filled in the through grooves 134 and located between the chip 120 and the circuit board 130 , so that there is a good buffer between the chip 120 and the circuit board 130 .

Referring to FIG. 1D , after the dielectric material layer 140 is formed, the release layer 112 and the carrier 110 are removed, so that the lower surface 121 of the chip 120 is exposed outside the dielectric material layer 140 . In some embodiments, the lower surface 121 of the chip 120 is exposed outside the through-grooves 134 of the circuit board 130 . In addition, since both the circuit board 130 and the chip 120 are placed on the release layer 112 and are in contact with the release layer 112 , the lower surface 121 of the chip 120 can be flush with the second surface 133 of the glass substrate 131 .

Referring to FIG. 1E , after removing the release layer 112 and the carrier 110 , a build-up circuit structure 150 is formed on the circuit board 130 , and a patterned conductive layer 160 is formed on the circuit board 130 . The build-up circuit structure 150 can be electrically connected to the conductive via 135 , the patterned conductive layer 160 can be electrically connected to the conductive via 135 , and the patterned conductive layer 160 can be electrically connected to the chip 120 . Therefore, the build-up circuit structure 150 can be electrically connected to the patterned conductive layer 160 through the conductive via 135 . Specifically, the build-up circuit structure 150 includes a first circuit layer 151 , a first dielectric layer 152 , a second circuit layer 153 and at least one first via hole 154 . The first circuit layer 151 covers the first surface 132 of the glass substrate 131 , and the first dielectric layer 152 covers the first circuit layer 151 and the first surface 132 of the glass substrate 131 . The first via hole 154 penetrates through the first dielectric layer 152 to electrically connect the first circuit layer 151 and the second circuit layer 153 . The second circuit layer 153 and the first circuit layer 151 are located on opposite sides of the first dielectric layer 152 respectively.

In addition, in this embodiment, since the build-up circuit structure 150 is formed on the first surface 132 of the glass substrate 131 and the patterned conductive layer 160 is formed on the second surface 133 of the glass substrate 131, the build-up circuit structure 150 and the patterned conductive layer 160 are formed on the second surface 133 of the glass substrate 131. The conductive layers 160 are respectively located on opposite sides of the glass substrate 131 .

In addition, in this embodiment, the lower surface 121 of the chip 120 can be used as the active surface 122 . The active surface 122 faces the patterned conductive layer 160 , and the active surface 122 can be electrically connected to the patterned conductive layer 160 .

Next, in order to electrically connect the embedded chip package 100 of the present embodiment with the outside thereof, a conductive connection member may be formed on the patterned conductive layer 160 . In this embodiment, the conductive connecting member may be, for example, the solder balls 170 , but not limited thereto. Referring to FIG. 1F , solder balls 170 are formed on the patterned conductive layer 160 , so that the solder balls 170 and the circuit board 130 are located on opposite sides of the patterned conductive layer 160 respectively. At this point, the embedded chip package 100 of the present embodiment is substantially completed.

In addition, please refer to FIG. 1G , in this embodiment, the shape of the through slot 134 may be circular, but not limited thereto. That is, in other embodiments, the shape of the through slot may also be a square or other suitable shapes, as long as the chip can be embedded in the through slot of the circuit board.

In short, the embedded chip package 100 of this embodiment includes a circuit board 130 , a chip 120 , a dielectric material layer 140 and a build-up circuit structure 150 . The circuit board 130 includes a glass substrate 131 and at least one conductive via 135 . The glass substrate 131 has a first surface 132 , a second surface 133 opposite to the first surface 132 , and a through groove 134 penetrating the glass substrate 131 . The conductive vias 135 penetrate through the glass substrate 131 . The chip 120 is disposed in the through slot 134 . The dielectric material layer 140 is filled in the through groove 134 and covers the chip 120 . The build-up circuit structure 150 is disposed on the circuit board 130 . The build-up circuit structure 150 is electrically connected to the conductive via 135 . The lower surface 121 of the chip 120 is exposed outside the dielectric material layer 140 . With this design, the fabrication method of the embedded chip package 100 of this embodiment can improve the warpage problem caused by the build-up circuit structure 150 or the package, and the embedded chip package 100 of this embodiment has better performance Packaging yield and reliability.

Other examples are listed below for illustration. It must be noted here that the following embodiments use the element numbers and part of the contents of the previous embodiments, wherein the same numbers are used to represent the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and repeated descriptions in the following embodiments will not be repeated.

FIG. 1H is a schematic cross-sectional view of an embedded chip package according to another embodiment of the present invention. 1F and FIG. 1H at the same time, the embedded chip package 100a of this embodiment is similar to the embedded chip package 100 in FIG. 1F, but the main difference between the two is that the embedded chip package of this embodiment is The conductive connections of 100 a are copper pillars 172 , and the build-up circuit structure 150 a further includes a second dielectric layer 155 and a second via hole 156 . Specifically, in the method for fabricating the embedded chip package 100a of the present embodiment, first referring to the steps of FIGS. 1A to 1D for fabrication, and then referring to FIG. 1H, a build-up circuit structure 150a is formed on the circuit board 130 , and a patterned conductive layer 160 is formed on the circuit board 130 . The build-up circuit structure 150 a further includes a second dielectric layer 155 and a second via hole 156 . The second dielectric layer 155 covers the second wiring layer 153 and the first dielectric layer 152 . The second via hole 156 penetrates through the second dielectric layer 155 to electrically connect the second circuit layer 153 . Then, referring to FIG. 1H again, copper pillars 172 are formed on the patterned conductive layer 160 , so that the copper pillars 172 and the circuit board 130 are located on opposite sides of the patterned conductive layer 160 respectively.

2A to 2B are schematic cross-sectional views illustrating a method for fabricating an embedded chip package according to another embodiment of the present invention. The difference between the embodiment shown in FIGS. 2A to 2B and the embodiment shown in FIGS. 1A to 1F lies in: the position of the build-up circuit structure 150b, the active surface 122 and the build-up layer of the embedded chip package 100b of this embodiment The relative relationship of the line structure 150b. In addition, the embedded chip package 100b of this embodiment does not include a patterned conductive layer.

Specifically, in the method for fabricating the embedded chip package 100b of the present embodiment, first referring to the steps in FIGS. 1A to 1D for fabrication, and then referring to FIG. 2A , a build-up circuit structure 150b is formed on the circuit board 130 . . At this time, the build-up circuit structure 150 b is disposed on the second surface 133 of the glass substrate 131 , and the build-up circuit structure 150 b can be electrically connected to the conductive via 135 . In this embodiment, the lower surface 121 of the chip 120 may be the active surface 122 . The active surface 122 faces the build-up circuit structure 150b, and the active surface 122 can be electrically connected to the build-up circuit structure 150b.

Then, referring to FIG. 2B, solder balls 170a are formed on the build-up circuit structure 150b, so that the solder balls 170a and the circuit board 130 are located on opposite sides of the build-up circuit structure 150b, respectively. At this point, the embedded chip package 100b of the present embodiment is substantially completed.

Although the solder balls 170a are formed on the build-up circuit structure 150b in FIG. 2B, it is not limited thereto. That is, in other embodiments, as shown in FIG. 2C , copper pillars 172 a can also be formed on the build-up circuit structure 150 b to complete the embedded chip package 100 c of another embodiment.

3A-3B are schematic cross-sectional views of side-by-side package structures according to various embodiments of the present invention. In the parallel package structure, the fabricated embedded chip package 100 or the embedded chip package 100a is arranged on the circuit boards 200 and 200a in a parallel manner. Referring to FIG. 3A , in the parallel package structure 10 of the present embodiment, two embedded chip packages 100 are schematically arranged on the circuit board 200 . The two embedded chip packages 100 can be electrically connected to the circuit board 200 through the solder balls 170 thereof. Referring to FIG. 3B , in the parallel package structure 10a of the present embodiment, two embedded chip packages 100a are schematically arranged on the circuit board 200a. The two embedded chip packages 100a can be electrically connected to the circuit board 200a through the copper pillars 172 thereof.

It should be noted that although FIG. 3A (or FIG. 3B ) schematically disposes two embedded chip packages 100 (or embedded chip packages 100 a ) on the circuit board 200 (or the circuit board 200 a ), the present invention does not The number of embedded chip packages 100 (or embedded chip packages 100 a ) in the side-by-side package structure is not limited. That is to say, in other not-shown embodiments, more than two embedded chip packages 100 (or embedded chip packages 100a ) may also be arranged on the circuit board 200 (or the circuit board 200a ) to Different side-by-side packaging structures are formed.

4A-4B are schematic cross-sectional views of package on package structures according to various embodiments of the present invention. In the stacked package structure, the embedded chip package 100 , the embedded chip package 100 a , the embedded chip package 100 b , the embedded chip package 100 c , or a combination thereof, are configured in a stacked manner. on the circuit boards 200b and 200c. Referring to FIG. 4A , in the stacked package structure 10b of the present embodiment, one embedded chip package 100 is schematically disposed on the circuit board 200b, and one embedded chip package 100b is disposed on the embedded chip package 100b. on the chip package 100 . The embedded chip package 100b and the circuit board 200b are located on opposite sides of the embedded chip package 100, respectively. In addition, the solder balls 170 a of the embedded chip package 100 b may be electrically connected to the build-up circuit structure 150 of the embedded chip package 100 . The solder balls 170 of the embedded chip package 100 are electrically connected to the circuit board 200b.

Referring to FIG. 4B , in the stacked package structure 10c of the present embodiment, one embedded chip package 100a is schematically disposed on the circuit board 200c, and one embedded chip package 100c is disposed on the embedded chip package 100c. on the chip package 100a. The embedded chip package 100c and the circuit board 200c are respectively located on opposite sides of the embedded chip package 100a. In addition, the copper pillars 172a of the embedded chip package 100c may be electrically connected to the build-up circuit structure 150a of the embedded chip package 100a. The copper pillars 172 of the embedded chip package 100a may be electrically connected to the circuit board 200c.

It should be noted that although FIG. 4A (or FIG. 4B ) schematically disposes one embedded chip package 100 (or embedded chip package 100 a ) in the embedded chip package 100 b (or embedded chip package 100 c ) and the circuit board 200b (or the circuit board 200c), but the present invention does not limit the number of the embedded chip packages 100 (or the embedded chip packages 100a) in the stacked package structure. That is to say, in other unshown embodiments, more than one embedded chip package 100 (or embedded chip package 100a ) may be arranged in the embedded chip package 100b (or embedded chip package 100b ). between the package 100c) and the circuit board 200b (or the circuit board 200c) to form a package-on-package structure with a plurality of stacked layers. In other words, the stacked packaging structures 10b and 10c of this embodiment have the advantage of increasing the stacking structure and the wiring.

To sum up, in the embedded chip package, the manufacturing method and the stacked package structure of the present invention, the embedded chip package includes a circuit board, a chip, a dielectric material layer and a build-up circuit structure. Wherein, the circuit board includes a glass substrate and conductive through holes, and the glass substrate has a through groove penetrating through the glass substrate. Next, the chip is arranged in the through groove, the dielectric material layer is filled in the through groove, and the build-up circuit structure is arranged on the circuit board. With this design, the manufacturing method of the embedded chip package of the present invention can improve the warpage problem caused by the build-up circuit or the package, so that the embedded chip package of the present invention has better packaging yield and reliability. In addition, the stacked packaging structure of the present invention has the advantage of increasing stacking structures and circuits.

Although the present invention has been disclosed above with examples, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the invention shall be determined by the claims.

Claims (20)

1. An embedded chip package, comprising: circuit boards, including: a glass substrate having a first surface, a second surface opposite to the first surface, and a through groove penetrating the glass substrate; and at least one conductive via, penetrating the glass substrate; a chip, disposed in the through-slot; a dielectric material layer, filling the through-grooves and covering the chip; and The build-up circuit structure is disposed on the circuit board, wherein the build-up circuit structure is electrically connected with the conductive through hole, and the lower surface of the chip is exposed outside the dielectric material layer. 2. The embedded chip package of claim 1, wherein the lower surface of the chip is flush with the second surface of the glass substrate. 3. The embedded chip package according to claim 1, wherein the build-up circuit structure comprises: the first circuit layer; a first dielectric layer covering the first circuit layer; a second wiring layer located on opposite sides of the first dielectric layer respectively from the first wiring layer; and At least one first via hole penetrates through the first dielectric layer to electrically connect the first circuit layer and the second circuit layer. 4. The embedded chip package according to claim 1, wherein the build-up circuit structure is disposed on the first surface of the glass substrate, the embedded chip package further comprising: a patterned conductive layer, disposed on the second surface of the glass substrate, so that the build-up circuit structure and the patterned conductive layer are respectively located on opposite sides of the glass substrate; and The solder balls or copper pillars are disposed on the patterned conductive layer, so that the solder balls or the copper pillars and the circuit board are respectively located on opposite sides of the patterned conductive layer. 5 . The embedded chip package of claim 4 , wherein the lower surface of the chip is an active surface, and the active surface faces the patterned conductive layer and is electrically connected to the patterned conductive layer. 6 . . 6 . The embedded chip package of claim 4 , wherein the build-up circuit structure is electrically connected to the patterned conductive layer through the conductive via. 7 . 7. The embedded chip package according to claim 1, wherein the build-up circuit structure is disposed on the second surface of the glass substrate, the embedded chip package further comprising: The solder balls or copper pillars are disposed on the build-up circuit structure, so that the solder balls or the copper pillars and the circuit board are respectively located on opposite sides of the build-up circuit structure. 8 . The embedded chip package of claim 7 , wherein the lower surface of the chip is an active surface, and the active surface faces the build-up wiring structure and is electrically connected to the build-up wiring structure. 9 . . 9 . The embedded chip package of claim 1 , wherein the through-groove connects the first surface and the second surface of the glass substrate. 10 . 10. A stacked packaging structure, comprising: circuit board; at least one embedded chip package as claimed in claim 4, disposed on the circuit board; and The embedded chip package as claimed in claim 7 is disposed on the embedded chip package as claimed in claim 4 , wherein the embedded chip package as claimed in claim 7 and the circuit The boards are respectively located on opposite sides of the embedded chip package as claimed in claim 4 . 11 . The package-on-package structure of claim 10 , wherein the solder balls or the copper pillars of the embedded chip package as claimed in claim 7 are connected to the solder balls as claimed in claim 4 . The build-up circuit structure of the embedded chip package is electrically connected, and the solder balls or the copper pillars of the embedded chip package as claimed in claim 4 are electrically connected to the circuit board. 12. A method for manufacturing an embedded chip package, comprising: providing a carrier and a release layer configured on the carrier; disposing a chip on the release layer; A circuit board is arranged on the release layer, and the circuit board includes: a glass substrate having a first surface, a second surface opposite to the first surface, and a through groove penetrating the glass substrate; and at least one conductive via, penetrating the glass substrate; After arranging the chip and the circuit board on the release layer and embedding the chip in the through-groove, a dielectric material layer is formed on the release layer, wherein the dielectric an electrical material layer is filled in the through groove and covers the chip; removing the release layer and the carrier so that the lower surface of the chip is exposed outside the dielectric material layer; After removing the release layer and the carrier, a build-up circuit structure is formed on the circuit board, so that the build-up circuit structure and the conductive via are electrically connected. 13. The method for fabricating an embedded chip package according to claim 12, wherein the lower surface of the chip is flush with the second surface of the glass substrate. 14. The method for fabricating an embedded chip package according to claim 12, wherein the build-up circuit structure comprises: the first circuit layer; a first dielectric layer covering the first circuit layer; a second wiring layer located on opposite sides of the first dielectric layer respectively from the first wiring layer; and At least one first via hole penetrates through the first dielectric layer to electrically connect the first circuit layer and the second circuit layer. 15. The manufacturing method of the embedded chip package according to claim 12, wherein the build-up circuit structure is disposed on the first surface of the glass substrate, and the manufacturing method of the embedded chip package further comprises: : forming a patterned conductive layer on the second surface of the glass substrate, so that the build-up circuit structure and the patterned conductive layer are respectively located on opposite sides of the glass substrate; and Solder balls or copper pillars are formed on the patterned conductive layer, so that the solder balls or the copper pillars and the circuit board are located on opposite sides of the patterned conductive layer, respectively. 16 . The method for manufacturing an embedded chip package according to claim 15 , wherein the lower surface of the chip is an active surface, and the active surface faces the patterned conductive layer and is connected to the patterned conductive layer. 17 . Electrical connection. 17 . The method for fabricating an embedded chip package according to claim 15 , wherein the build-up circuit structure is electrically connected to the patterned conductive layer through the conductive via. 18 . 18 . The method for manufacturing an embedded chip package according to claim 12 , wherein the build-up circuit structure is disposed on the second surface of the glass substrate, and the manufacturing method for the embedded chip package further comprises: 19 . : Solder balls or copper pillars are formed on the build-up circuit structure, so that the solder balls or copper pillars and the circuit board are located on opposite sides of the build-up circuit structure, respectively. 19 . The method for manufacturing an embedded chip package according to claim 18 , wherein the lower surface of the chip is an active surface, and the active surface faces the build-up circuit structure and is connected to the build-up circuit structure. 20 . Electrical connection. 20 . The method for fabricating an embedded chip package according to claim 12 , wherein the through-groove connects the first surface and the second surface of the glass substrate. 21 .

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