CN111276177B

CN111276177B - Shift register and driving method thereof, gate drive circuit and display device

Info

Publication number: CN111276177B
Application number: CN202010108276.7A
Authority: CN
Inventors: 王继国; 樊君
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2020-02-21
Filing date: 2020-02-21
Publication date: 2022-05-03
Anticipated expiration: 2040-02-21
Also published as: CN111276177A

Abstract

The invention discloses a shift register and a driving method thereof, a grid driving circuit and a display device, wherein an added reset module provides a second grid driving signal or a reset signal to a second grid driving signal output end under the common control of a shift signal and an inverted shift signal, so that in the closing process after the second grid driving signal output end outputs the second grid driving signal, the second grid driving signal (VGH) can be controlled to firstly fall to a reset signal (VSS) and then fall to a low voltage signal (VGL) by adjusting a time sequence, namely, the falling process (closing process) of the second grid driving signal is divided into a plurality of stages, the closing time of the second grid driving signal firstly falls to VSS and then falls to VGL, and the voltage coupling DeltaVp caused to a pixel electrode in the closing process of the second grid driving signal output end can be effectively reduced through the process, thereby preventing the pixel display from generating the flicker phenomenon.

Description

Shift register and driving method thereof, gate drive circuit and display device

Technical Field

The invention relates to the technical field of display, in particular to a shift register, a driving method thereof, a grid driving circuit and a display device.

Background

As shown in fig. 1, a conventional Integrated Memory Pixel (MIP) includes a signal writing module, a latch, and a display module. Specifically, in fig. 1, the method includes: a first N-type transistor M1, a first P-type transistor M1 ', a second N-type transistor M2, a second P-type transistor M2 ', a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, a pixel electrode P, a first node N, a positive phase node Q, and an inverse phase node Q '. The signal writing module comprises M5 and M7, and a grid electrode of M5 and a grid electrode of M7 are electrically connected with the first grid driving signal output end GateA; the latches include M1, M1 ', M2, and M2'; the display module comprises M3, M4 and M6, and the gate of M6 is electrically connected with the second gate driving signal output terminal GateB.

The integrated memory pixel cell shown in fig. 1 includes two gate drive signal outputs (GateA and GateB). When a pixel signal is written, the pixel does not display; when the pixel displays, no pixel signal is written, namely, GateA and GateB are separately driven in time division. The high voltage VDD and the low voltage VSS secure a latch, and in fig. 1, FRP is a long black signal and Data is a Data signal line. When a pixel signal is written, M5 is turned on, a Data voltage signal on a Data line Data is written into the latch, if the Data voltage signal is at a low level, the potential of Q' is at a high level, M4 is turned on, and the potential of N is the potential of the Data voltage signal; if the Data voltage signal on the Data is at high level, the potential of Q' is at low level, M3 is turned on, the long black signal FRP is connected to the first node N, and after the gate b controls M6 to be turned on, the potential of the pixel electrode P is the potential of the first node N. The existing shift register can only output one grid driving signal, cannot be used together with an integrated memory pixel unit, and cannot provide two grid driving signals which are used for driving the integrated memory pixel unit and output independently without mutual interference.

Disclosure of Invention

In view of this, embodiments of the present invention provide a shift register and a driving method thereof, a gate driving circuit, and a display device, so as to solve the problems that the conventional shift register can only output one gate driving signal, cannot be used in conjunction with an integrated memory pixel unit, and cannot provide two gate driving signals, which are output independently and do not interfere with each other, for driving the integrated memory pixel unit; and the shift register is used for solving the problem that the display flicker phenomenon is caused by large voltage coupling of the existing shift register to the pixel electrode in the closing process of the GateB signal.

Accordingly, an embodiment of the present invention provides a shift register for driving a pixel circuit in an integrated memory, including: the shift register module, the output module and the reset module; wherein,

the shift register module is used for generating a shift signal and an inverted shift signal, outputting the shift signal through the shift signal output end and outputting the inverted shift signal through the inverted shift signal output end;

the output module is used for: under the common control of the shift signal and the inverted shift signal, generating a first gate drive signal provided to a first gate drive signal output end; and generating a second gate drive signal provided to a second gate drive signal output under common control of the shift signal and the inverted shift signal;

the reset module is used for: under the common control of the shift signal and the inverted shift signal, providing a second gate drive signal to the second gate drive signal output end; and under the common control of the shift signal and the inverted shift signal, providing a reset signal to the second gate drive signal output end, wherein the voltage of the reset signal is less than that of the second gate drive signal.

In a possible implementation manner, in the shift register provided in the embodiment of the present invention, the number of the output modules and the number of the reset modules are at least one.

In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the reset module includes: a reset transmission gate, a first reset transistor, a second reset transistor, and a third reset transistor; the type of the first reset transistor is opposite to that of the second reset transistor; wherein,

the positive phase control end of the reset transmission gate is electrically connected with the shift signal output end, the reverse phase control end of the reset transmission gate is electrically connected with the reverse phase shift signal output end, and the input end of the reset transmission gate is electrically connected with the first enabling end;

the grid electrode of the first reset transistor and the grid electrode of the second reset transistor are electrically connected with the output end of the reset transmission gate, the first electrode of the first reset transistor is electrically connected with a first voltage end, the first electrode of the second reset transistor is electrically connected with a second voltage end, and the second electrode of the first reset transistor and the second electrode of the second reset transistor are electrically connected with the output end of the reset module; the first voltage end is used for providing the reset signal, and the second voltage end is used for providing the second gate driving signal;

a grid electrode of the third reset transistor is electrically connected with the inverted shift signal output end, a first electrode of the third reset transistor is electrically connected with a third voltage end, and a second electrode of the third reset transistor is electrically connected with a grid electrode of the second reset transistor; wherein a voltage of the reset signal is greater than a voltage of the third voltage terminal.

In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the shift register module includes: an input module and a shift module; wherein,

the input module is used for controlling the normal phase shift signal end or the reverse phase shift signal end to be electrically connected with the input signal end of the shift module under the common control of the forward scanning control end and the reverse scanning control end;

the shift module is used for generating the shift signal and the reverse phase shift signal according to the signal input by the input signal end under the control of the positive phase shift clock signal input end, the reverse phase shift clock signal input end and the positive phase enable end.

In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the input module includes: a forward scan transfer gate and a reverse scan transfer gate; wherein,

the forward scanning transmission gate has a forward control end electrically connected to the forward scanning control end, a reverse control end electrically connected to the reverse scanning control end, an input end electrically connected to the forward scanning transmission gate and a forward shift signal end, and an output end electrically connected to the input signal end;

the normal phase control end of the reverse scanning transmission gate is electrically connected with the reverse scanning control end, the reverse phase control end of the reverse scanning transmission gate is electrically connected with the normal scanning control end, the input end of the reverse scanning transmission gate is electrically connected with the reverse phase shift signal end, and the output end of the reverse scanning transmission gate is electrically connected with the input signal end.

In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the shift module includes: the shift control circuit comprises a first tri-state gate, a second tri-state gate, a shift control transistor, a first shift inverter, a NAND gate and a second shift inverter; wherein,

the positive phase control end of the first tri-state gate is electrically connected with the negative phase shift clock signal input end, the negative phase control end of the first tri-state gate is electrically connected with the positive phase shift clock signal input end, and the input end of the first tri-state gate is electrically connected with the input signal end;

the grid electrode of the shift control transistor is electrically connected with the positive phase enable end, the first electrode of the shift control transistor is electrically connected with the output end of the first tri-state gate, and the second electrode of the shift control transistor is electrically connected with the second voltage end;

the input end of the first shift inverter is electrically connected with the output end of the first tri-state gate;

the positive phase control end of the second tri-state gate is electrically connected with the positive phase shift clock signal input end, the negative phase control end of the second tri-state gate is electrically connected with the negative phase shift clock signal input end, the input end of the second tri-state gate is electrically connected with the output end of the first shift phase inverter, and the output end of the second tri-state gate is electrically connected with the output end of the first tri-state gate;

the first input end of the NAND gate is electrically connected with the input end of the normal phase shift clock signal, and the second input end of the NAND gate is electrically connected with the output end of the first shift inverter;

the input end of the second shift inverter is electrically connected with the inverted shift signal output end and the output end of the NAND gate, and the output end of the second shift inverter is electrically connected with the shift signal output end.

In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the output module includes: a first output submodule and a second output submodule; wherein,

the first output submodule is used for generating a first grid driving signal according to a signal of a first clock signal end and a signal of a second enabling end under the common control of the shift signal and the inverted shift signal, and outputting the first grid driving signal through a first grid driving signal output end;

and the second output submodule is used for generating a second gate drive signal according to a signal of a second clock signal end and a signal of an inverted enable end under the common control of the shift signal and the inverted shift signal, and outputting the second gate drive signal through a second gate drive signal output end.

In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the first output submodule includes: a first output transmission gate, a second output transmission gate, a first output inverter and a second output inverter; wherein,

the positive phase control end of the first output transmission gate is electrically connected with the shift signal output end, the negative phase control end of the first output transmission gate is electrically connected with the negative phase shift signal output end, and the input end of the first output transmission gate is electrically connected with the first clock signal end;

the positive phase control end of the second output transmission gate is electrically connected with the negative phase shift signal output end, the negative phase control end of the second output transmission gate is electrically connected with the shift signal output end, and the input end of the second output transmission gate is electrically connected with the second enable end;

the input end of the first output phase inverter is electrically connected with the output end of the first output transmission gate and the output end of the second output transmission gate;

the input end of the second output phase inverter is electrically connected with the output end of the first output phase inverter, and the output end of the second output phase inverter is electrically connected with the output end of the first grid driving signal.

In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the second output submodule includes: a third output transmission gate, a fourth output transmission gate, a third output inverter, a first output transistor and a second output transistor; the type of the first output transistor is opposite to that of the second output transistor; wherein,

the positive phase control end of the third output transmission gate is electrically connected with the shift signal output end, the negative phase control end of the third output transmission gate is electrically connected with the negative phase shift signal output end, and the input end of the third output transmission gate is electrically connected with the second clock signal end;

the positive phase control end of the fourth output transmission gate is electrically connected with the negative phase shift signal output end, the negative phase control end of the fourth output transmission gate is electrically connected with the shift signal output end, and the input end of the fourth output transmission gate is electrically connected with the negative phase enable end;

the input end of the third output phase inverter is electrically connected with the output end of the third output transmission gate and the output end of the fourth output transmission gate;

the grid electrode of the first output transistor and the grid electrode of the second output transistor are electrically connected with the output end of the third output phase inverter, the first electrode of the first output transistor is electrically connected with the output end of the reset module, the first electrode of the second output transistor is electrically connected with the third voltage end, and the second electrode of the first output transistor and the second electrode of the second output transistor are electrically connected with the second grid electrode driving signal output end.

Correspondingly, an embodiment of the present invention further provides a gate driving circuit, including: a plurality of cascaded shift registers of any one of the above aspects of the invention arranged on a first side of a display panel, and a plurality of cascaded shift registers of any one of the above aspects of the invention arranged on a second side of the display panel; wherein,

the cascaded shift registers arranged on the first side are electrically connected with pixel circuits in the integrated memories positioned on the odd-numbered rows, and the cascaded shift registers arranged on the second side are electrically connected with pixel circuits in the integrated memories positioned on the even-numbered rows.

In a possible implementation manner, in the gate driving circuit provided in an embodiment of the present invention, a positive phase shift clock signal input terminal of a shift module in the shift register disposed on the first side is electrically connected to the positive phase clock signal line, and a negative phase shift clock signal input terminal of the shift module in the shift register disposed on the first side is electrically connected to the negative phase clock signal line; a positive phase shift clock signal input end of a shift module in the shift register arranged on the second side is electrically connected with the reverse phase clock signal line, and the reverse phase shift clock signal input end is electrically connected with the positive phase clock signal line;

in all the shift registers, except for the first stage of shift register, the positive phase shift signal end of one stage of shift register is electrically connected with the shift signal output end of the adjacent previous stage of shift register; except the last stage of shift register, the inverted shift signal end of one stage of shift register is electrically connected with the shift signal output end of the next adjacent stage of shift register.

Correspondingly, the embodiment of the invention also provides a display device which comprises the gate driving circuit provided by the embodiment of the invention.

Correspondingly, an embodiment of the present invention further provides a driving method of the shift register, including:

the shift register module generates a shift signal and an inverse shift signal;

the output module generates a first grid driving signal provided for a first grid driving signal output end under the common control of the shift signal and the inverted shift signal; and generating a second gate drive signal provided to a second gate drive signal output under common control of the shift signal and the inverted shift signal;

the reset module provides a second grid driving signal to the second grid driving signal output end under the common control of the shift signal and the inverted shift signal; and under the common control of the shift signal and the inverted shift signal, providing a reset signal to the second gate drive signal output end, wherein the voltage of the reset signal is less than that of the second gate drive signal.

The invention has the following beneficial effects:

the embodiment of the invention provides a shift register, a driving method thereof, a grid driving circuit and a display device, wherein the shift register comprises: the shift register module, the output module and the reset module; the shift register provided by the embodiment of the invention can be used in cooperation with the MIP pixel unit, and two gate drive signal output ends respectively connected with two rows of grid lines connected with the MIP pixel unit can be controlled to independently output by adjusting a time sequence, so that no interference exists between the writing and the displaying of signals in the MIP pixel unit. In addition, the embodiment of the invention adds the reset module which provides the second gate driving signal or the reset signal to the second gate driving signal output end under the common control of the shift signal and the inverted shift signal, and the voltage of the reset signal is smaller than that of the second gate driving signal, so that in the closing process after the second gate driving signal output end outputs the second gate driving signal, the second gate driving signal (VGH) can be controlled to firstly fall to the reset signal (VSS) and then fall to the low voltage signal (VGL) by adjusting the time sequence, namely, the falling process (closing process) of the second gate driving signal is divided into a plurality of stages, the closing time of the second gate driving signal firstly falls to VSS and then falls to VGL, and the voltage coupling Δ Vp caused to the pixel electrode in the closing process of the second gate driving signal output end can be effectively reduced through the process, thereby preventing the problem of the flicker phenomenon of the pixel display.

Drawings

Fig. 1 is a circuit diagram of a conventional MIP pixel unit;

FIG. 2 is a schematic diagram of a shift register according to an embodiment of the present invention;

FIG. 3 is a second schematic diagram of a shift register according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a shift register according to a first embodiment of the present invention;

FIG. 5 is a timing diagram illustrating the input/output signals of FIG. 4 during the writing of the pixel signals in the first display mode;

FIG. 6 is a timing diagram illustrating the input/output signals displayed by the pixel of FIG. 4 in the first display mode;

FIG. 7 is a second timing diagram of the input/output signals displayed by the pixel of FIG. 4 in the first display mode;

FIG. 8 is a timing diagram illustrating an input/output relationship of the shift register according to the first embodiment of the present invention in the second display mode;

FIG. 9 is a flowchart of a driving method of a shift register according to an embodiment of the present invention;

fig. 10 is a schematic structural diagram of a shift register according to a second embodiment of the present invention;

FIG. 11 is a timing diagram illustrating the input/output signals of FIG. 10 during the writing of pixel signals in the first display mode;

fig. 12 is a schematic structural diagram of a gate driving circuit according to an embodiment of the invention;

fig. 13 is a second schematic structural diagram of a gate driving circuit according to an embodiment of the invention.

Detailed Description

The following describes in detail specific embodiments of a shift register, a driving method thereof, a gate driving circuit, and a display device according to an embodiment of the present invention with reference to the accompanying drawings.

A shift register provided in an embodiment of the present invention is used for driving a pixel circuit in an integrated memory, and as shown in fig. 2, the shift register includes: the device comprises a shift register module 1, an output module 2 and a reset module 3; wherein,

the shift register module 1 is used for generating a shift signal and an inverted shift signal, outputting the shift signal through a shift signal output end STV _ N, and outputting the inverted shift signal through an inverted shift signal output end STV _ F;

the output module 2 is used for: under the common control of the shift signal and the inverted shift signal, generating a first gate driving signal provided to a first gate driving signal output terminal GateA 1; and generating a second gate driving signal supplied to the second gate driving signal output terminal GateB1 under the common control of the shift signal and the inverted shift signal;

the reset module 3 is used for: under the common control of the shift signal and the inverted shift signal, a second gate driving signal VGH is provided to the second gate driving signal output terminal GateB 1; and supplying a reset signal VSS to the second gate driving signal output terminal GateB1 under the common control of the shift signal and the inverted shift signal, the voltage of the reset signal VSS being less than the voltage of the second gate driving signal VGH.

In the shift register provided in the embodiment of the present invention, the shift register module is adopted to generate the shift signal and the inverted shift signal, and the output module is adopted to generate the first gate driving signal and the second gate driving signal under the control of the shift signal and the inverted shift signal, so that two gate driving signals can be provided for the MIP pixel unit through the first-stage shift register, and the writing and the display of the MIP pixel unit are realized. In addition, the embodiment of the invention adds the reset module which provides the second gate driving signal or the reset signal to the second gate driving signal output end under the common control of the shift signal and the inverted shift signal, and the voltage of the reset signal is smaller than that of the second gate driving signal, so that in the closing process after the second gate driving signal output end outputs the second gate driving signal, the second gate driving signal (VGH) can be controlled to firstly fall to the reset signal (VSS) and then fall to the low voltage signal (VGL) by adjusting the time sequence, namely, the falling process (closing process) of the second gate driving signal is divided into a plurality of stages, the closing time of the second gate driving signal firstly falls to VSS and then falls to VGL, and the voltage coupling Δ Vp caused to the pixel electrode in the closing process of the second gate driving signal output end can be effectively reduced through the process, thereby preventing the problem of the flicker phenomenon of the pixel display.

In a specific implementation, in the shift register provided in the embodiment of the present invention, the number of the output modules and the number of the reset modules are at least one. Specifically, in a preferred case, the number of the output modules and the reset modules included in the shift register provided in the embodiment of the present invention may be not only 1, but also greater than 1, so that the number of the MIP pixel units that the shift register provided in the embodiment of the present invention can be used for driving may also be greater than 1, and in the specific implementation, the waveform of the clock signal needs to be adjusted accordingly, which will be described below with reference to an embodiment in which one shift register drives two MIP pixel units.

In a specific implementation, as shown in fig. 3, in the shift register provided in the embodiment of the present invention, the shift register module 1 may specifically include: an input module 11 and a shift module 12; wherein,

the input module 11 is configured to control the normal phase shift signal terminal STV _ N-1 or the reverse phase shift signal terminal STV _ N +1 to be electrically connected to the input signal terminal STV _ IN of the shift module 12 under the common control of the forward scan control terminal CN and the reverse scan control terminal CNB;

the shift module 12 is configured to generate a shift signal and an inverted shift signal according to a signal input from the input signal terminal STV _ IN under the control of the positive phase shift clock signal input terminal VCK, the inverted shift clock signal input terminal VCKB, and the positive phase enable terminal EN 3.

In specific implementation, the positive phase shift signal terminal STV _ N-1 is electrically connected to the shift signal output terminal of the adjacent previous shift register, and the negative phase shift signal terminal STV _ N +1 is electrically connected to the shift signal output terminal of the adjacent next shift register.

In a specific implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 3, the output module 2 includes: a first output submodule 21 and a second output submodule 22; wherein,

the first output submodule 21 is configured to generate a first gate driving signal according to a signal of the first clock signal terminal CK1 and a signal of the second enable terminal EN2 under common control of a shift signal and an inverted shift signal, and output the first gate driving signal through a first gate driving signal output terminal GateA 1;

the second output submodule 22 is configured to generate a second gate driving signal according to the signal of the second clock signal terminal CK2 and the signal of the inverted enable terminal EN3B under the common control of the shift signal and the inverted shift signal, and output the second gate driving signal through a second gate driving signal output terminal GateB 1.

The shift register provided by the embodiment of the invention comprises a shift register module, an output module and a reset module, the write-in and display of MIP pixels can be realized through the mutual matching of a gate circuit and a clock signal, and the clock signal ensures that each gate driving signal is independently output and does not influence each other; the arrangement of each enable end ensures the signal reset and rapid power-down functions of the shift register, and can still ensure the pixel to display the pre-written signal information under the condition of no initial signal and clock signal during low-frequency driving, thereby ensuring the effective realization of the MIP pixel unit function.

In a specific implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 4, the reset module 3 includes: a reset transmission gate 31, a first reset transistor T1, a second reset transistor T2, and a third reset transistor T3; the type of the first reset transistor T1 is opposite to that of the second reset transistor T2; wherein,

the positive phase control end of the reset transmission gate 31 is electrically connected with the shift signal output end STV _ N, the negative phase control end of the reset transmission gate 31 is electrically connected with the negative phase shift signal output end STV _ F, and the input end of the reset transmission gate 31 is electrically connected with the first enable end EN 1;

a gate of the first reset transistor T1 and a gate of the second reset transistor T2 are both electrically connected to the output terminal of the reset transmission gate 31, a first pole of the first reset transistor T1 is electrically connected to the first voltage terminal VSS, a first pole of the second reset transistor T2 is electrically connected to the second voltage terminal VGH, and a second pole of the first reset transistor T1 and a second pole of the second reset transistor T2 are both electrically connected to the output terminal of the reset module 3; the first voltage terminal VSS is used for providing a reset signal VSS, and the second voltage terminal VGH is used for providing a second gate driving signal VGH;

a gate of the third reset transistor T3 is electrically connected to the inverted shift signal output terminal STV _ F, a first pole of the third reset transistor T3 is electrically connected to the third voltage terminal VGL, and a second pole of the third reset transistor T3 is electrically connected to a gate of the second reset transistor T2; the voltage of the reset signal VSS is greater than the voltage of the third voltage terminal VGL. Therefore, in the closing process after the second gate driving signal is output by the second gate driving signal output end GateB1, the second gate driving signal (VGH) can be controlled to firstly fall to the reset signal (VSS) and then fall to the low voltage signal (VGL) by adjusting the time sequence, namely, the falling process (closing process) of the second gate driving signal is divided into multiple stages, the second gate driving signal firstly falls to VSS at the closing moment and then falls to VGL, and the voltage coupling delta Vp caused by the second gate driving signal output end in the closing process to the pixel electrode can be effectively reduced through the process, so that the problem of flicker phenomenon of pixel display can be prevented.

In a specific implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 4, the input module 11 includes: a forward scan transfer gate 111 and a reverse scan transfer gate 112; wherein,

the positive phase control end of the forward scanning transmission gate 111 is electrically connected with the positive direction scanning control end CN, the negative phase control end of the forward scanning transmission gate 111 is electrically connected with the negative direction scanning control end CNB, the input end of the forward scanning transmission gate 111 is electrically connected with the positive phase shift signal end STV _ N-1, and the output end of the forward scanning transmission gate 111 is electrically connected with the input signal end STV _ IN;

the normal phase control terminal of the reverse scan transfer gate 112 is electrically connected to the reverse scan control terminal CNB, the reverse phase control terminal of the reverse scan transfer gate 112 is electrically connected to the forward scan control terminal CN, the input terminal of the reverse scan transfer gate 112 is electrically connected to the reverse shift signal terminal STV _ N +1, and the output terminal of the reverse scan transfer gate 112 is electrically connected to the input signal terminal STV _ IN.

In a specific implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 4, the shift module 12 includes: a first tri-state gate 121, a second tri-state gate 122, a shift control transistor T4, a first shift inverter 123, a nand gate 124, and a second shift inverter 125; wherein,

the positive phase control end of the first tri-state gate 121 is electrically connected to the negative phase shift clock signal input end VCKB, the negative phase control end of the first tri-state gate 121 is electrically connected to the positive phase shift clock signal input end VCK, and the input end of the first tri-state gate 121 is electrically connected to the input signal end STV _ IN;

the gate of the shift control transistor T4 is electrically connected to the positive phase enable terminal EN3, the first pole of the shift control transistor T4 is electrically connected to the output terminal of the first tri-state gate 121, and the second pole of the shift control transistor T4 is electrically connected to the second voltage terminal VGH;

the input of the first shift inverter 123 is electrically connected to the output of the first tri-state gate 121;

the positive phase control end of the second tristate gate 122 is electrically connected with the positive phase shift clock signal input end VCK, the inverted phase control end of the second tristate gate 122 is electrically connected with the inverted phase shift clock signal input end VCKB, the input end of the second tristate gate 122 is electrically connected with the output end of the first shift inverter 123, and the output end of the second tristate gate 122 is electrically connected with the output end of the first tristate gate 121;

the first input end of the nand gate 124 is electrically connected to the non-inverting shift clock signal input end VCK, and the second input end of the nand gate 124 is electrically connected to the output end of the first shift inverter 123;

the input terminal of the second shift inverter 125 is electrically connected to the inverted shift signal output terminal STV _ F and the output terminal of the nand gate 124, and the output terminal of the second shift inverter 125 is electrically connected to the shift signal output terminal STV _ N.

In practical implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 4, the first output submodule 21 includes: a first output transmission gate 211, a second output transmission gate 212, a first output inverter 213, and a second output inverter 214; wherein,

the positive phase control terminal of the first output transmission gate 211 is electrically connected to the shift signal output terminal STV _ N, the negative phase control terminal of the first output transmission gate 211 is electrically connected to the negative phase shift signal output terminal STV _ F, and the input terminal of the first output transmission gate 211 is electrically connected to the first clock signal terminal CK 1;

the positive phase control terminal of the second output transmission gate 212 is electrically connected to the inverted shift signal output terminal STV _ F, the inverted control terminal of the second output transmission gate 212 is electrically connected to the shift signal output terminal STV _ N, and the input terminal of the second output transmission gate 212 is electrically connected to the second enable terminal EN 2;

an input terminal of the first output inverter 213 is electrically connected to an output terminal of the first output transmission gate 211 and an output terminal of the second output transmission gate 212;

an input terminal of the second output inverter 214 is electrically connected to an output terminal of the first output inverter 213, and an output terminal of the second output inverter 214 is electrically connected to the first gate driving signal output terminal GateA 1.

In practical implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 4, the second output submodule 22 includes: a third output transmission gate 221, a fourth output transmission gate 222, a third output inverter 223, a first output transistor T5, and a second output transistor T6; the type of the first output transistor T5 is opposite to that of the second output transistor T6; wherein,

the positive phase control terminal of the third output transmission gate 221 is electrically connected to the shift signal output terminal STV _ N, the negative phase control terminal of the third output transmission gate 221 is electrically connected to the negative phase shift signal output terminal STV _ F, and the input terminal of the third output transmission gate 221 is electrically connected to the second clock signal terminal CK 2;

the positive phase control terminal of the fourth output transmission gate 222 is electrically connected to the inverted shift signal output terminal STV _ F, the inverted control terminal of the fourth output transmission gate 222 is electrically connected to the shift signal output terminal STV _ N, and the input terminal of the fourth output transmission gate 222 is electrically connected to the inverted enable terminal EN 3B;

the input of the third output inverter 223 is electrically connected to the output of the third output transmission gate 221 and the output of the fourth output transmission gate 222;

a gate of the first output transistor T5 and a gate of the second output transistor T6 are electrically connected to an output terminal of the third output inverter 223, a first pole of the first output transistor T5 is electrically connected to an output terminal of the reset module 3, a first pole of the second output transistor T6 is electrically connected to the third voltage terminal VGL, and a second pole of the first output transistor T5 and a second pole of the second output transistor T6 are electrically connected to the second gate driving signal output terminal GateB 1.

In specific implementation, in the embodiment shown in fig. 4, VGH is a high voltage, VGL is a low voltage, and VSS is between VGH and VGL, so that the signal of gate b1 can be lowered from VGH to VSS and then to VGL by controlling the timing sequence, thereby effectively reducing voltage coupling Δ Vp caused by the gate b1 to the pixel electrode P during the turn-off process of the second gate driving signal output terminal gate b1, and preventing the pixel display from flickering.

In the embodiment shown in fig. 4, the second reset transistor T2, the shift control transistor T4 and the first output transistor T5 are all P-type transistors, and the first reset transistor T1, the third reset transistor T3 and the second output transistor T6 are all N-type transistors.

The shift register shown in fig. 4 provided in the embodiment of the present invention includes three parts, namely a shift register module, an output module, and a reset module, wherein gate a1 and gate b1 provide two gate driving signals required for a line of MIP pixel units, gate a1 is electrically connected to the gate of the write transistor of the MIP pixel unit, and gate b1 is electrically connected to the gate of the display transistor of the MIP pixel unit.

The shift register shown in fig. 4 provided in the embodiment of the present invention is used to provide two corresponding gate driving signals for MIP pixel units in odd rows, and in practical implementation, the shift register used to provide two corresponding gate driving signals for MIP pixel units in even rows differs from the embodiment shown in fig. 4 in that: the first input terminal of the nand gate 124 is electrically connected to the inverted shift clock signal input terminal VCKB, the non-inverting control terminal of the first tri-state gate 121 is electrically connected to the non-inverting shift clock signal input terminal VCK, the inverting control terminal of the first tri-state gate 121 is electrically connected to VCKB, the non-inverting control terminal of the second tri-state gate 122 is electrically connected to VCKB, and the inverting control terminal of the second tri-state gate 122 is electrically connected to VCK.

The shift register provided by the embodiment of the invention can be a single-side shift register, and a first-stage shift register can be used for a line of MIP pixel units. In a specific implementation, the multi-stage shift register disposed on the left side of the display panel may be controlled to drive the MIP pixel units in odd lines, and the multi-stage shift register disposed on the right side of the display panel may be controlled to drive the MIP pixel units in even lines. The phase of the start signal and the phase of the shift clock signal on the two sides are the same, the phase of the clock signal input by CK1 for output and the phase of the clock signal input by CK2 on the left side and the right side are different, and the left side and the right side have four control output clock signal input ends which ensure that the gate driving signals on the left side and the right side are independently output and are not interfered.

The Transistor in the above embodiments of the present invention may be a Thin Film Transistor (TFT) or a Metal Oxide semiconductor field effect Transistor (MOS), and is not limited herein. In specific implementations, the first and second poles of these transistors may be interchanged in function, depending on the type of transistor and the input signal, and are not specifically distinguished herein. In practical operation, the first electrode can be a source electrode, and the second electrode can be a drain electrode; or the first electrode can be a drain electrode, and the second electrode can be a source electrode.

The operation principle of the shift register shown in fig. 4 according to the embodiment of the present invention will be described in detail with reference to the timing sequences shown in fig. 5 and 6.

The circuit structure of fig. 4 mainly includes three parts: the left part shift register module 1 plays a role of shift register, the right part output module 2 is used for driving a pixel to be in grid electrode driving, and the middle part reset module 3 is controlled by an EN1 signal and is used for controlling the falling (closing) state of GateB. Taking the EN1 signal as an example of low level, to briefly describe the working principle of the present invention, Gate a1 and Gate B1 supply two Gate voltages of one row of pixels, Gate a1 is the Gate of the writing TFT, and Gate B1 is the Gate of the display TFT.

Specifically, as shown in fig. 4 and 5, in the first display mode (the first display mode is a normal display mode, when M4 in fig. 1 is turned on, and the Data voltage on the Data line Data is written into the pixel electrode P under the control of the gate b 1), when the pixel signal is written:

IN the period T1, when STV _ IN inputs high level, VCK inputs low level, VCKB inputs high level, and EN3 inputs high level, the shift control transistor T4 is turned off; when the second tri-state gate 122 is turned off, the first tri-state gate 121 outputs a low level, the first shift inverter 123 outputs a high level, and the nand gate 124 outputs a high level, the inverted shift signal output terminal STV _ F outputs a high level; the second shift inverter 125 outputs a low level, and the shift signal output terminal STV _ N outputs a low level; the first enable terminal EN1 outputs a low level, the reset transmission gate 31 is turned off, the third reset transistor T3 is turned on, a low voltage signal of the third voltage terminal VGL is transmitted to the gate of the second reset transistor T2, the second reset transistor T2 is turned on, and the second voltage terminal VGH is turned on with the first electrode of the first output transistor T5; the first output transmission gate 211 is turned off, the second output transmission gate 212 is turned on, the second enable terminal EN2 outputs a low level, the second output transmission gate 212 outputs a low level, and the second output inverter 214 outputs a low level to the first gate driving signal output terminal GateA 1;

IN the period of T2, when STV _ IN inputs low level, VCK inputs high level, VCKB inputs low level, EN3 inputs high level, the shift control transistor T4 is turned off; the first shift inverter 123 keeps outputting a high level, the first tri-state gate 121 is turned off, the second tri-state gate 122 outputs a low level, the nand gate 124 outputs a low level, the inverted shift signal output terminal STV _ F outputs a low level, and the third reset transistor T3 is turned off; the second shift inverter 125 outputs a high level, and the shift signal output terminal STV _ N outputs a high level; the first enable terminal EN1 outputs a low level, the reset transmission gate 31 is turned on, the second reset transistor T2 is turned on, and the second voltage terminal VGH is turned on with the first electrode of the first output transistor T5; the first output transmission gate 211 is turned on, the second output transmission gate 212 is turned off, CK1 outputs a high level, the first output transmission gate 211 outputs a high level, and the second output inverter 214 outputs a high level to the first gate driving signal output terminal GateA 1;

IN the period of T3, when STV _ IN inputs low level, VCK inputs high level, VCKB inputs low level, EN3 inputs high level, the shift control transistor T4 is turned off; the first shift inverter 123 keeps outputting a high level, the first tri-state gate 121 is turned off, the second tri-state gate 122 outputs a low level, the nand gate 124 outputs a low level, the inverted shift signal output terminal STV _ F outputs a low level, and the third reset transistor T3 is turned off; the second shift inverter 125 outputs a high level, and the shift signal output terminal STV _ N outputs a high level; the first enable terminal EN1 outputs a low level, the reset transmission gate 31 is turned on, the second reset transistor T2 is turned on, and the second voltage terminal VGH is turned on with the first electrode of the first output transistor T5; the first output transmission gate 211 is turned on, the second output transmission gate 212 is turned off, CK1 outputs a low level, the first output transmission gate 211 outputs a low level, and the second output inverter 214 outputs a low level to the first gate driving signal output terminal GateA 1;

IN the period T4, when STV _ IN inputs low level, VCK inputs low level, VCKB inputs high level, and EN3 inputs high level, the shift control transistor T4 is turned off; the second tri-state gate 122 is turned off, the first tri-state gate 122 outputs a high level, the first shift inverter 123 outputs a low level, the nand gate 124 outputs a high level, the inverse shift signal output terminal STV _ F outputs a high level, the third reset transistor T3 is turned on, the low voltage signal of the third voltage terminal VGL is transmitted to the gate of the second reset transistor T2, the second reset transistor T2 is turned on, and the second voltage terminal VGH is turned on with the first electrode of the first output transistor T5; the second shift inverter 125 outputs a low level, and the shift signal output terminal STV _ N outputs a low level; the first enable terminal EN1 outputs a low level, and the reset transmission gate 31 is closed; the first output transmission gate 211 is turned off, the second output transmission gate 212 is turned on, the second enable terminal EN2 outputs a low level, the second output transmission gate 212 outputs a low level, and the second output inverter 214 outputs a low level to the first gate driving signal output terminal GateA 1;

FIG. 5 is a simulation waveform diagram of the single-stage circuit structure designed in the present invention, wherein during the forward scan, the CN signal is high level, the CNB signal level is low level, and the initial signal transmitted to the present stage is the output STV _ N-1 of the previous row of pixels; during reverse scanning, the CN signal is low, the CNB signal is high, and the start signal transmitted to the current stage is the output STV _ N +1 of the next row of pixels. IN the figure, taking the positive scan as an example, VCK and VCKB are respectively responsible for shifting the two stages of shift registers, and the pulse width of VCK and VCKB is twice the pulse width of CK signal, because the start signal STV _ IN of the shift registers at both sides has the same phase, but drives the odd-numbered lines and the even-numbered lines, respectively, so the pulse width of the shift signal is twice the clock signal CK.

The simulation result shown in fig. 5 is the state at the time of gate a1 turning on, and in the stage T2, CK1 is high level, CK2 is low level, gate a1 outputs a pulse signal, M5 in fig. 1 is turned on, a data voltage is written into the latch ring, and after a pulse signal is output from the gate b1 of the next frame, a signal written by the data line when the gate a1 outputs the pulse signal is output.

Specifically, as shown in fig. 4 and 6, in the first display mode (the first display mode is a normal display mode, when M4 in fig. 1 is turned on, and the Data voltage on the Data line Data is written into the pixel electrode P under the control of the GateB 1), when the pixel signal is displayed:

at the stage T1, when STV _ IN inputs high level, VCK inputs low level, VCKB inputs high level, and EN3 inputs high level, the shift control transistor T4 is turned off; when the second tri-state gate 122 is turned off, the first tri-state gate 121 outputs a low level, the first shift inverter 123 outputs a high level, and the nand gate 124 outputs a high level, the inverted shift signal output terminal STV _ F outputs a high level; the second shift inverter 125 outputs a low level, and the shift signal output terminal STV _ N outputs a low level; the first enable terminal EN1 outputs a low level, the reset transmission gate 31 is turned off, the third reset transistor T3 is turned on, a low voltage signal of the third voltage terminal VGL is transmitted to the gate of the second reset transistor T2, the second reset transistor T2 is turned on, and the second voltage terminal VGH is turned on with the first electrode of the first output transistor T5; the third output transmission gate 221 is turned off, the fourth output transmission gate 222 is turned on, the inverting enable terminal EN3B outputs a low level, the third output inverter 223 outputs a high level, the second output transistor T6 is turned on, and a low voltage signal of the third voltage terminal VGL is transmitted to the second gate driving signal output terminal GateB 1;

at the stage T2, when STV _ IN inputs low level, VCK inputs high level, VCKB inputs low level, EN3 inputs high level, the shift control transistor T4 is turned off; the first shift inverter 123 keeps outputting a high level, the first tri-state gate 121 is turned off, the second tri-state gate 122 outputs a low level, the nand gate 124 outputs a low level, the inverted shift signal output terminal STV _ F outputs a low level, and the third reset transistor T3 is turned off; the second shift inverter 125 outputs a high level, and the shift signal output terminal STV _ N outputs a high level; the first enable terminal EN1 outputs a low level, the reset transmission gate 31 is turned on, the second reset transistor T2 is turned on, and the second voltage terminal VGH is turned on with the first electrode of the first output transistor T5; the third output transmission gate 221 is turned on, the fourth output transmission gate 222 is turned off, CK2 outputs a high level, the third output inverter 223 outputs a low level, the first output transistor T5 is turned on, and the second gate driving signal of the second voltage terminal VGH is transmitted to the second gate driving signal output terminal GateB 1;

at the stage T3, when STV _ IN inputs low level, VCK inputs high level, VCKB inputs low level, EN3 inputs high level, the shift control transistor T4 is turned off; the first shift inverter 123 keeps outputting a high level, the first tri-state gate 121 is turned off, the second tri-state gate 122 outputs a low level, the nand gate 124 outputs a low level, the inverted shift signal output terminal STV _ F outputs a low level, and the third reset transistor T3 is turned off; the second shift inverter 125 outputs a high level, and the shift signal output terminal STV _ N outputs a high level; the first enable terminal EN1 outputs a low level, the reset transmission gate 31 is turned on, the second reset transistor T2 is turned on, and the second voltage terminal VGH is turned on with the first electrode of the first output transistor T5; the third output transmission gate 221 is turned on, the fourth output transmission gate 222 is turned off, CK2 outputs a low level, the third output inverter 223 outputs a high level, the second output transistor T6 is turned on, and a low voltage signal of the third voltage terminal VGL is transmitted to the second gate driving signal output terminal GateB 1;

at the stage T4, when STV _ IN inputs low level, VCK inputs low level, VCKB inputs high level, and EN3 inputs high level, the shift control transistor T4 is turned off; the second tri-state gate 122 is turned off, the first tri-state gate 122 outputs a high level, the first shift inverter 123 outputs a low level, the nand gate 124 outputs a high level, the inverse shift signal output terminal STV _ F outputs a high level, the third reset transistor T3 is turned on, the low voltage signal of the third voltage terminal VGL is transmitted to the gate of the second reset transistor T2, the second reset transistor T2 is turned on, and the second voltage terminal VGH is turned on with the first electrode of the first output transistor T5; the second shift inverter 125 outputs a low level, and the shift signal output terminal STV _ N outputs a low level; the first enable terminal EN1 outputs a low level, and the reset transmission gate 31 is closed; the third output transmission gate 221 is turned off, the fourth output transmission gate 222 is turned on, the inversion enable terminal EN3B outputs a low level, the third output inverter 223 outputs a high level, the second output transistor T6 is turned on, and a low voltage signal of the third voltage terminal VGL is transmitted to the second gate driving signal output terminal GateB 1. The simulation result shown in fig. 6 is an output waveform of the shift register at the time of pixel display. At stage t2, CK1 is low level, CK2 is high level, GateA1 outputs low level, GateB1 outputs pulse signal, and the pixel displays the state of being written into the latch when Gate A is opened at the previous time.

The foregoing describes the GateA1 and GateB1 output waveforms of the pixel write and display time shift registers. The timing chart shown in fig. 6 outputs a pulse signal (VGH) at the stage t2 from the gate b1 due to the gate electrical connection of the gate b1 and the display TFT M6, and Δ Vp = (Voff-Von) × Cgd/(Cs + Clc + Cgd) due to the voltage coupling of the gate b1 to the pixel electrode P during the turn-off process; where Cgd is a parasitic capacitance of the pixel TFT, Clc is a liquid crystal capacitance, Cs is a storage capacitance, Von is a working voltage of the pixel TFT, and Voff is a turn-off voltage of the pixel TFT. Since the timing chart shown in fig. 6 is directly decreased from VGH to VGL after the GateB1 outputs the pulse signal, the voltage coupling Δ Vp caused by the GateB1 to the pixel electrode P during the turn-off process is large, which causes Flick phenomenon during the pixel display, thereby reducing the picture display quality. Therefore, in order to solve the problem of flicker phenomenon in the timing diagram shown in fig. 6 caused by the large voltage coupling of the gate b1 to the pixel electrode P during the turn-off process, the present invention proposes a gate b1 output waveform shown in fig. 7, where fig. 7 can be regarded as an enlarged schematic diagram of fig. 6, and the difference from fig. 6 is that the EN1 signal in fig. 7 changes, and the turn-off process of the gate b1 is divided into two stages, that is, in the T2 stage described in the operation principle shown in fig. 6, a high level signal is given to EN1 before the end of the high level potential output by CK2, and since the reset transmission gate 31 is turned on, the first reset transistor T1 is turned on, and the first voltage terminal VSS is turned on with the first pole of the first output transistor T5; since the third output transmission gate 221 is turned on, the fourth output transmission gate 222 is turned off, CK2 outputs a high level, the third output inverter 223 outputs a low level, and the first output transistor T5 is turned on, the reset signal of the first voltage terminal VSS is transmitted to the second gate driving signal output terminal GateB1, that is, after the GateB1 outputs a pulse signal for a certain period of time (less than the total duration of the T2 stage) at the T2 stage, a high level signal is given to EN1, the GateB1 signal is first lowered to VSS, and then the GateB1 signal is lowered to VGL at the T3 stage, so that compared with an embodiment in which VGL is directly lowered to VGL, voltage coupling Δ Vp caused to the pixel electrode during the turn-off process of the GateB1 can be effectively reduced.

The shift register provided by the embodiment of the invention can realize the time-sharing output of the first gate driving signal and the second gate driving signal without interference, and each gate driving signal has an independent enable signal. The enable signal has the following three functions: the EN signal has three functions, wherein one function is that when the pixel is normally written or displayed, the enabling signal plays a reset role, and the grid driving signal is ensured to be timely restored to a low level after the shift register at the current stage is closed; secondly, performing secondary filtration; when the rapid discharge is carried out, the enabling signal can pull the electric potential of the grid driving signal high, and the full discharge is carried out; when the MIP pixel unit needs to continuously display the high level or the low level written in by the GateA1, the MIP pixel unit does not need an Integrated Circuit (IC) to provide a pulse signal, and only needs to maintain an enable signal as a direct-current voltage signal during display, so that the GateB1 can be ensured to be continuously opened; thirdly, the reset module 3 is added to control the output signal of the GateB1 through an EN1 signal, the falling process (closing process) of the GateB1 signal is divided into multiple stages, the closing time of the GateB1 signal is firstly reduced to VSS and then reduced to VGL, and the voltage coupling delta Vp of the pixel electrode caused by the closing process of the GateB1 can be effectively reduced through the process.

The operation principle of the shift register of the present invention shown in fig. 4 in the first display mode is described above, and the operation principle of the shift register of the present invention shown in fig. 4 in the second display mode (low frequency display mode) is described below.

Specifically, in the second display mode:

as shown IN fig. 8, STV _ IN inputs low level, VCK inputs low level, VCKB inputs low level, EN3 inputs low level, and the shift control transistor T4 is turned on, so that the potential of the input terminal of the first shift inverter 123 is the high voltage VGH; the second tri-state gate 122 is turned off, the first tri-state gate 121 outputs a high level, the first shift inverter 123 outputs a low level, the nand gate 124 outputs a high level, the inverted shift signal output terminal STV _ F outputs a high level, the second shift inverter 125 outputs a low level, and the shift signal output terminal STV _ N outputs a low level; the first enable terminal EN1 outputs a low level, the reset transmission gate 31 is turned off, the third reset transistor T3 is turned on, a low voltage signal of the third voltage terminal VGL is transmitted to the gate of the second reset transistor T2, the second reset transistor T2 is turned on, and the second voltage terminal VGH is turned on with the first electrode of the first output transistor T5; the first output transmission gate 211 is turned off, the second output transmission gate 212 is turned on, the second enable terminal EN2 outputs a low level, the second output transmission gate 212 outputs a low level, and the second output inverter 214 outputs a low level to the first gate driving signal output terminal GateA 1; the third output transmission gate 221 is turned off, the fourth output transmission gate 222 is turned on, the inversion enable terminal EN3B outputs a high level, the third output inverter 223 outputs a low level, the first output transistor T5 is turned on, and the second gate driving signal of the first voltage terminal VGH is transmitted to the second gate driving signal output terminal GateB 1.

In the second display mode, VCK, VCKB, CK1, and CK2 all input low level, GateA1 outputs low level, and GateB1 outputs high level. That is, the Gate a1 writes a certain state to the pixel at the previous time, and then the EN3B signal is kept high without STV, VCK, VCKB and CLK signals, the Gate B1 can still be turned on, and the pixel can still display the state of the Gate a1 written at the previous time, and until the next time, the Gate a1 is turned on again, and the state of the previous writing into the pixel latch ring is changed. The display mode has the greatest advantages that power consumption is saved, an IC does not need to output pulse signals, only needs to continuously provide direct current signals such as VGH, VGL, VDD, VSS and EN, and the like, normal display can still be achieved at a pixel end under the action of the shift register, and the pixel display effect can still not be influenced under the condition of extremely low refreshing frequency.

When the pixel discharges rapidly, the GateB1 is opened, the shifting module is closed, and the shifting register of the current stage does not discharge rapidly to the shifting register of the next stage, but the rapid discharge is realized through the EN signal. When discharging rapidly, the GateB1 is guaranteed to be opened, and the input and output waveforms are the same as those in the low frequency display, refer to fig. 6.

Based on the same inventive concept, an embodiment of the present invention further provides a driving method of the shift register, as shown in fig. 9, which specifically includes:

s901, a shift register module generates a shift signal and an inverse shift signal;

s902, the output module generates a first grid driving signal provided for a first grid driving signal output end under the common control of the shift signal and the inverted shift signal; and generating a second gate drive signal provided to a second gate drive signal output under common control of the shift signal and the inverted shift signal;

s903, the reset module provides a second grid driving signal to the second grid driving signal output end under the common control of the shift signal and the inverted shift signal; and under the common control of the shift signal and the inverted shift signal, providing a reset signal to the second gate drive signal output end, wherein the voltage of the reset signal is less than that of the second gate drive signal.

In the driving method of the shift register provided in the embodiment of the present invention, the reset module is adopted to provide the second gate driving signal or the reset signal to the second gate driving signal output end under the control of the shift signal and the inverted shift signal, and the voltage of the reset signal is smaller than the voltage of the second gate driving signal, so that in the closing process after the second gate driving signal output end outputs the second gate driving signal, the second gate driving signal (VGH) can be controlled to first fall to the reset signal (VSS) and then fall to the low voltage signal (VGL) by adjusting the timing sequence, that is, the falling process (closing process) of the second gate driving signal is divided into multiple stages, the closing time of the second gate driving signal falls to VSS and then falls to VGL, and the voltage coupling Δ Vp caused to the pixel electrode in the closing process of the second gate driving signal output end can be effectively reduced through the process, thereby preventing the problem of the flicker phenomenon of the pixel display.

In a specific implementation, the working principle of the driving method of the shift register may refer to the working principle described in the shift register, which is not described herein again.

The above description processes are all described by taking an example that the first-stage shift register only includes one output module and one reset module, and the following description is given by taking an example that the first-stage shift register includes two output modules and two reset modules, as shown in fig. 10, fig. 10 is a case that an output module and a reset module are added on the basis of fig. 4, the connection relationship between the added output module and reset module and the shift module is the same as the connection relationship between the original output module and reset module and shift module, except that the first output transmission gate 211 is electrically connected to the third clock signal terminal, the third output transmission gate 221 is electrically connected to the fourth clock signal terminal, the first gate signal output terminal is GateA3, and the second gate signal output terminal is GateB3, which is not repeated herein.

The shift register shown in fig. 10 provided by the present invention can be used for driving two lines of MIP pixel units, and in specific implementation, when more output modules and reset modules are adopted, a shift register at one level can also correspond to four lines of MIP pixel units, or even more lines of MIP pixel units. When one stage of shift register corresponds to two rows of MIP pixel units, the structure of the odd-even stage shift register still has differences as follows:

the structure of the shift register for driving the MIP pixel units of the odd lines is as shown in fig. 10, while the structure of the shift register for driving the MIP pixel units of the even lines differs from that shown in fig. 10 in that: the non-inverting control terminal of the first tri-state gate 121 is electrically connected to VCK, the inverting control terminal of the first tri-state gate 121 is electrically connected to VCKB, the non-inverting control terminal of the second tri-state gate 122 is electrically connected to VCKB, the inverting control terminal of the second tri-state gate 122 is electrically connected to VCK, and the first input terminal of the nand gate 124 is electrically connected to VCKB.

As shown in fig. 11, fig. 11 is an operation principle timing chart corresponding to fig. 10, and in the first display mode, when writing of the pixels driven in a plurality of rows is performed:

at stage t 1', STV _ IN inputs high; at stage t 2', STV _ IN inputs low level, GateA1 outputs high level, and GateB1, GateA3 and GateB3 all output low level; at stage t 3', STV _ IN inputs low level, and GateA1, GateB1, GateA3 and GateB3 all output low level; at stage t 4', STV _ IN inputs low level, GateA3 outputs high level, and GateA1, GateB1 and GateB3 all output low level; at stage t 5', STV _ IN inputs low level, and GateA1, GateB1, GateA3 and GateB3 all output low level; at the t2 'stage, the t 3' stage, the t4 'stage, and the t 5' stage, the STV _ N outputs a high level.

Fig. 11 is a simulation waveform of the timing when the first-stage shift register provided in the embodiment of the present invention is used to drive two lines of MIP pixel units, and the pixel is in a writing state, that is, GateA is turned on and GateB is turned off. As shown in fig. 11, the pulse width of the shift signal output terminal STV _ N output to the next stage from each stage of shift register is the same as the pulse width of the VCK signal, but the pulse width of the CK1 signal and the pulse width of the CK2 signal become 1/4 the pulse width of the VCK signal, which is different from that when 1 line of MIP pixel units are driven from each stage of shift register, the pulse width of the CK1 signal and the pulse width of the CK2 signal become 1/2 the VCK signal.

When each stage of shift register drives 2 lines of MIP pixel units, the circuit designed by the invention still keeps all functions when each stage of shift register drives 1 line of MIP pixel units, and can also realize a series of functions such as high-frequency picture display, low-frequency picture display, rapid discharge and the like. The number of the shift registers is halved from 1 line driven by each stage to 2 lines driven by each stage for the same resolution, which is more beneficial to the realization of a narrow frame.

Based on the same inventive concept, an embodiment of the present invention further provides a gate driving circuit, including: a plurality of the shift registers provided by the embodiments of the present invention and arranged at a first side of the display panel in cascade, and a plurality of the shift registers provided by the embodiments of the present invention and arranged at a second side of the display panel in cascade; wherein,

the cascaded shift registers arranged on the first side are electrically connected with the pixel circuits in the integrated memories positioned on the odd-numbered rows, and the cascaded shift registers arranged on the second side are electrically connected with the pixel circuits in the integrated memories positioned on the even-numbered rows.

In a specific implementation, in the gate driving circuit provided in the embodiment of the present invention, a positive phase shift clock signal input terminal of a shift module in the shift register disposed on the first side is electrically connected to the positive phase clock signal line, and a negative phase shift clock signal input terminal is electrically connected to the negative phase clock signal line; a positive phase shift clock signal input end of a shift module in the shift register arranged on the second side edge is electrically connected with a negative phase clock signal line, and the negative phase shift clock signal input end is electrically connected with the positive phase clock signal line;

in all the shift registers, except the first stage shift register, the positive phase shift signal end of one stage shift register is electrically connected with the shift signal output end of the adjacent previous stage shift register; except the last stage of shift register, the inverted shift signal end of one stage of shift register is electrically connected with the shift signal output end of the next adjacent stage of shift register.

The gate driving circuit provided by the present invention is illustrated by two specific embodiments.

As shown in fig. 12, the first gate driving signal and the second gate driving signal output by the same stage of shift register are used for driving the MIP pixel units in the same row, and in specific implementation, the shift register for driving the MIP pixel units in odd rows may be disposed at the left side of the display panel, and the shift register for driving the MIP pixel units in even rows may be disposed at the right side of the display panel; namely, the left shift register and the right shift register which are positioned in the same row control two rows of MIP pixel units and respectively provide grid driving signals for the two rows of MIP pixel units.

As shown in fig. 12, GOA1L represents a first row of shift registers at the left side of the display panel for driving a first row of MIP Pixel cells Pixel 1; GOA1R shows a first row of shift registers at the right side of the display panel for driving a second row of MIP Pixel cells Pixel 2; GOA2L shows a second row of shift registers at the left side of the display panel for driving a third row of MIP Pixel cells Pixel 3; GOA2R represents a second row shift register located on the right side of the display panel for driving the fourth row of MIP Pixel cells Pixel 4; and so on … …; GOANL indicates the Nth line shift register located at the left side of the display panel for driving the 2N-1 line MIP Pixel unit Pixel 2N-1; the GOANR indicates an nth line shift register located at the right side of the display panel for driving the 2 nth line MIP Pixel cells Pixel 2N.

As shown in fig. 12, GateA1 is the first gate drive signal output terminal of GOA1L, and GateB1 is the second gate drive signal output terminal of GOA 1L; GateA2 is the first gate drive signal output terminal of GOA1R, and GateB2 is the second gate drive signal output terminal of GOA 1R; GateA3 is the first gate drive signal output terminal of GOA2L, and GateB3 is the second gate drive signal output terminal of GOA 2L; GateA4 is the first gate drive signal output terminal of GOA2R, and GateB4 is the second gate drive signal output terminal of GOA 2R; and so on … …; GateA2N-1 is the first gate drive signal output terminal of GOANL, GateB2N-1 is the second gate drive signal output terminal of GOANL; the gate A2N is a first gate drive signal output end of the GOANR, and the gate B2N is a second gate drive signal output end of the GOANR; wherein N is an integer greater than 3.

As shown in fig. 13, the first gate driving signal and the second gate driving signal output by the same stage of shift register are used to drive the MIP pixel units in the same row, and the third gate driving signal and the fourth gate driving signal output by the same stage of shift register are used to drive the MIP pixel units in another row, in specific implementation, the shift register for driving the MIP pixel units in odd rows may be disposed at the left side of the display panel, and the shift register for driving the MIP pixel units in even rows may be disposed at the right side of the display panel; namely, the left shift register and the right shift register which are positioned on the same row control four rows of MIP pixel units, and grid driving signals are respectively provided for the four rows of MIP pixel units.

As shown in fig. 13, the GOA1L represents a first row shift register located at the left side of the display panel for driving a first row of MIP Pixel cells Pixel1 and a third row of MIP Pixel cells Pixel 3; GOA1R denotes a first row shift register located at the right side of the display panel for driving a second row of MIP Pixel cells Pixel2 and a fourth row of MIP Pixel cells Pixel 4; GOA2L shows a second row shift register located at the left side of the display panel for driving the fifth row of MIP Pixel cells Pixel5 and the seventh row of MIP Pixel cells Pixel 7; GOA2R shows a second row shift register located at the right side of the display panel for driving the sixth row of MIP Pixel cells Pixel6 and the eighth row of MIP Pixel cells Pixel 8; and so on … …; GOANL indicates the Nth line shift register located at the left side of the display panel for driving the 4N-3 th line MIP Pixel unit Pixel4N-3 and the 4N-1 th line MIP Pixel unit Pixel 4N-1; the goose denotes an nth line shift register at the right side of the display panel for driving the 4N-2 th line MIP Pixel unit Pixel4N-2 and the 4 nth line MIP Pixel unit Pixel 4N.

As shown in fig. 13, the shift register in the left row and the shift register in the same row in the right side sequentially provide the first gate driving signal and the second gate driving signal for four rows of MIP pixel units.

Based on the same inventive concept, the embodiment of the invention also provides a display device, which comprises the gate driving circuit provided by the embodiment of the invention. The display device may be: the display device comprises a display device of any product with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. The implementation of the display device can be seen in the embodiments of the gate driving circuit, and repeated descriptions are omitted.

The shift register and the driving method thereof, the gate driving circuit and the display device provided by the embodiment of the invention comprise: the shift register module, the output module and the reset module; the shift register provided by the embodiment of the invention can be used in cooperation with the MIP pixel unit, and two gate drive signal output ends respectively connected with two rows of grid lines connected with the MIP pixel unit can be controlled to independently output by adjusting a time sequence, so that no interference exists between the writing and the displaying of signals in the MIP pixel unit. In addition, the embodiment of the invention adds the reset module which provides the second gate driving signal or the reset signal to the second gate driving signal output end under the common control of the shift signal and the inverted shift signal, and the voltage of the reset signal is smaller than that of the second gate driving signal, so that in the closing process after the second gate driving signal output end outputs the second gate driving signal, the second gate driving signal (VGH) can be controlled to firstly fall to the reset signal (VSS) and then fall to the low voltage signal (VGL) by adjusting the time sequence, namely, the falling process (closing process) of the second gate driving signal is divided into a plurality of stages, the closing time of the second gate driving signal firstly falls to VSS and then falls to VGL, and the voltage coupling Δ Vp caused to the pixel electrode in the closing process of the second gate driving signal output end can be effectively reduced through the process, thereby preventing the problem of the flicker phenomenon of the pixel display.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A shift register for driving a pixel circuit in an integrated memory, the shift register comprising: the shift register module, the output module and the reset module; wherein,

the shift register module is used for generating a shift signal and an inverse shift signal, outputting the shift signal through the shift signal output end and outputting the inverse shift signal through the inverse shift signal output end;

the output module is used for: under the common control of the shift signal and the inverted shift signal, generating a first gate drive signal provided to a first gate drive signal output terminal; and generating a second gate drive signal provided to a second gate drive signal output under common control of the shift signal and the inverted shift signal;

the reset module is used for: under the common control of the shift signal and the inverted shift signal, providing a second gate drive signal to the second gate drive signal output end; under the common control of the shift signal and the inverted shift signal, providing a reset signal to the second gate drive signal output end, wherein the voltage of the reset signal is less than that of the second gate drive signal;

the reset module includes: a reset transmission gate, a first reset transistor, a second reset transistor, and a third reset transistor; the type of the first reset transistor is opposite to that of the second reset transistor; wherein,

2. The shift register of claim 1, wherein the number of output modules and the number of reset modules are each at least one.

3. The shift register of claim 1 or 2, wherein the shift register module comprises: an input module and a shift module; wherein,

4. The shift register of claim 3, wherein the input module comprises: a forward scan transfer gate and a reverse scan transfer gate; wherein,

5. The shift register of claim 3, wherein the shift module comprises: the shift control circuit comprises a first tri-state gate, a second tri-state gate, a shift control transistor, a first shift inverter, a NAND gate and a second shift inverter; wherein,

the input end of the second shift phase inverter is electrically connected with the inverted shift signal output end and the output end of the NAND gate, and the output end of the second shift phase inverter is electrically connected with the shift signal output end.

6. The shift register of claim 1 or 2, wherein the output module comprises: a first output submodule and a second output submodule; wherein,

7. The shift register of claim 6, wherein the first output submodule comprises: a first output transmission gate, a second output transmission gate, a first output inverter and a second output inverter; wherein,

8. The shift register of claim 6, wherein the second output submodule comprises: a third output transmission gate, a fourth output transmission gate, a third output inverter, a first output transistor and a second output transistor; the type of the first output transistor is opposite to that of the second output transistor; wherein,

9. A gate drive circuit, comprising: a plurality of shift registers according to any one of claims 1 to 8 arranged in cascade at a first side of a display panel, and a plurality of shift registers according to any one of claims 1 to 8 arranged in cascade at a second side of the display panel; wherein,

10. The gate driving circuit according to claim 9, wherein the positive phase shift clock signal input terminal of the shift module in the shift register disposed at the first side is electrically connected to the positive phase clock signal line, and the negative phase shift clock signal input terminal is electrically connected to the negative phase clock signal line; a positive phase shift clock signal input end of a shift module in the shift register arranged on the second side is electrically connected with the reverse phase clock signal line, and the reverse phase shift clock signal input end is electrically connected with the positive phase clock signal line;

11. A display device comprising the gate driver circuit according to claim 9 or 10.

12. A driving method of a shift register according to any one of claims 1 to 8, comprising:

the shift register module generates a shift signal and an inverse shift signal;

the reset module provides a second grid driving signal to the second grid driving signal output end under the common control of the shift signal and the inverted shift signal; and under the common control of the shift signal and the inverted shift signal, providing a reset signal to the second gate drive signal output end, wherein the voltage of the reset signal is less than that of the second gate drive signal, and the voltage of the reset signal is greater than that of the third voltage end.