CN111276028A - Novel single-chip microcomputer and configuration comprehensive experiment system - Google Patents
Novel single-chip microcomputer and configuration comprehensive experiment system Download PDFInfo
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- CN111276028A CN111276028A CN202010206064.2A CN202010206064A CN111276028A CN 111276028 A CN111276028 A CN 111276028A CN 202010206064 A CN202010206064 A CN 202010206064A CN 111276028 A CN111276028 A CN 111276028A
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Abstract
The invention discloses a novel singlechip and configuration comprehensive experiment system, which comprises a singlechip CPU, wherein the singlechip CPU is double CPUs and is integrated in a system bus board, a bus board data bus interface, a bus board address bus interface and a bus board control bus interface are arranged in the system bus board, and the system bus board is connected with a graphic liquid crystal display, a programmable parallel interface, a DMA (direct memory access) data transmission controller, a programmable serial controller, a first digital-to-analog conversion module, a timing/counter module, a second digital-to-analog conversion module, an interrupt control module and a keyboard display controller through the bus board data bus interface, the bus board address bus interface and the bus board control bus interface. The invention can realize the teaching experiment of 8-bit/16-bit/32-bit microcomputer principle, and has stronger compatibility; the communication mode with the computer is improved, the communication connection of the USB/Ethernet is realized, the communication speed and the stability of the experiment system and the computer are improved, hot plugging is supported, and the device is safer and more durable.
Description
Technical Field
The invention belongs to the field of computers, and particularly relates to a novel single chip microcomputer and configuration comprehensive experiment system.
Background
The microcomputer is a computer known by people at present, the principle of the microcomputer is a computer principle, the computer highly integrates chips such as a central processing unit, a register, a data memory, a program memory, a timer, a counter, an interrupt control, a serial communication control, a universal I/O interface and the like, and the microcomputer is widely applied to various electronic devices as a controller, is large as a missile rocket national defense advanced weapon, is small as various household appliances, and has extremely wide application; the course is a course which needs to be learned by computer major and other department major, and has strong practice, many knowledge points and concepts are difficult to understand and master when learning optical theory, and the course can be learned well by practice of hands by self, so that a solid foundation is laid for the learning of subsequent courses; the microcomputer principle experiment system used in the microcomputer courses of the existing mainstream colleges and universities mainly comprises two types, wherein a part of the microcomputer principle experiment system uses low-end products based on 8088/8086CPU and belongs to 8-bit computers, students perform some basic microcomputer principle experiments, and other middle-end products are based on 80386CPU and belong to 16-bit computers, and the students can perform some slightly complex microcomputer principle experiments.
The communication between the existing experiment system and a computer adopts an RS232 serial mode, many existing notebook computers or desktop computers do not have RS232 serial interfaces, so that the experiment system cannot be used, some experiment systems adopt a serial-to-USB module designed by a third party and can be used only if the experiment system is not used, but the performance is unstable, once the experiment system is not connected, the experiment system needs to be powered off firstly and then powered on again, the use is very inconvenient, and the normal operation of the experiment is seriously influenced; meanwhile, when the existing experimental system is communicated with a computer, the requirement on the computer is mostly a 32-bit operating system, and the problem of incompatibility exists in a 64-bit operating system. Therefore, the novel single chip microcomputer and the configuration comprehensive experiment system are improved.
Disclosure of Invention
In order to solve the technical problems, the invention provides the following technical scheme:
the invention relates to a novel singlechip and configuration comprehensive experiment system, which comprises a singlechip CPU, a system bus board, a graphic liquid crystal display, a programmable parallel interface, a DMA data transmission controller, a programmable serial controller, a first digital-to-analog conversion module, a timing/counter module, a second digital-to-analog conversion module, an interrupt control module and a keyboard display controller, and is characterized in that the singlechip CPU is a double CPU and is integrated in the system bus board, the system bus board is internally provided with a bus board data bus interface, a bus board address bus interface and a bus board control bus interface, and the bus board data bus interface and the bus board control bus interface are both connected with the graphic liquid crystal display, the programmable parallel interface, the DMA data transmission controller, the programmable serial controller, the first digital-to-analog conversion module, the timing/counter module, the keyboard display controller, The bus board address bus interface is connected with the graphic liquid crystal display, the programmable parallel interface, the DMA data transmission controller, the programmable serial controller, the timing/counter module, the second digital-to-analog conversion module, the interrupt control module and the keyboard display controller in a one-way mode.
The keyboard is connected with the keyboard display controller in a unidirectional mode, and the keyboard display controller is connected with the digital display tube in a unidirectional mode.
The invention also comprises a reset circuit, a relay control module, a direct current motor control module, a stepping motor dot matrix display module and a level conversion module, wherein the reset circuit is connected with the graphic liquid crystal display, the programmable parallel interface, the DMA data transmission controller and the programmable serial controller in a one-way manner, the programmable parallel interface is connected with the relay control module, the direct current motor control module and the stepping motor dot matrix display module in a one-way manner, and the level conversion module is connected with the programmable serial controller and the computer in a two-way manner.
As a preferred technical scheme of the invention, the single chip microcomputer CPU comprises a 486DXCPU module and a 386EXCPU module, wherein the 486DXCPU module and the 386EXCPU module are respectively provided with a power supply module, a reset module and a clock module, the 486DXCPU module and the 386EXCPU module are also provided with a CPU data bus interface, a CPU address bus interface and a CPU control bus interface, the CPU data bus interface is bidirectionally connected with the bus board data bus interface and the CPU control bus interface are also bidirectionally connected with the bus board control bus interface, and the CPU address bus interface is unidirectionally connected with the bus board address bus interface.
A bidirectional data buffer, an address latch and a system control circuit are respectively connected in series between the CPU data bus interface and the bus board data bus interface, between the CPU address bus interface and the bus board address bus interface, and between the CPU control bus interface and the bus board control bus interface, wherein the bidirectional data buffer is connected with the address latch in a unidirectional manner, and the address latch is connected with the system control circuit in a unidirectional manner.
As a preferred technical scheme of the invention, a system monitoring module, a user data module, a serial communication module, a USB communication module and an Ethernet communication module are arranged between the CPU data bus interface and the bus board data bus interface, between the CPU address bus interface and the bus board address bus interface and between the CPU control bus interface and the bus board control bus interface, and the serial communication module, the USB communication module and the Ethernet communication module can be interconnected with a bit computer/system.
As a preferred technical solution of the present invention, the graphic liquid crystal display is a graphic liquid crystal display LCD12864, the programmable parallel interface is a programmable parallel interface 8255A, the DMA data transfer controller is a DMA controller 8237, the programmable serial controller is a programmable serial controller 16C550, the first digital-to-analog conversion module is a digital-to-analog conversion DAC0832, the timing/counter module is a programmable timing/counter 8253A, the second digital-to-analog conversion module is a digital-to-analog conversion ADC0809, the interrupt control module is an interrupt control 8259, and the keyboard display controller is a keyboard display controller 8279.
The invention has the beneficial effects that:
1. the teaching experiment of 8-bit/16-bit/32-bit microcomputer principle can be realized, and the compatibility is stronger;
2. the communication mode with the computer is improved, the communication connection of the USB/Ethernet is realized, the communication speed of the experimental system and the computer is improved, the communication stability is improved, and meanwhile, the communication port also supports hot plugging, so that the damage to the computer caused by the fact that a communication line is plugged with an electric plug during the original serial communication is avoided;
3. the serial communication interface chip in the course of microcomputer principle adopts a novel device 16C550, so that students are good at learning new technology and mastering the new technology.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention.
In the drawings:
FIG. 1 is a system schematic block diagram of a novel single chip microcomputer and a configuration comprehensive experiment system of the invention;
FIG. 2 is a 386EX CPU module diagram of the novel single chip microcomputer and configuration comprehensive experiment system;
fig. 3 is a 486DX CPU module of the novel monolithic computer and configuration integrated experimental system of the invention.
In the figure: 1. a single chip CPU; 1-1, CPU data bus interface; 1-2, CPU address bus interface; 1-3, a CPU control bus interface; 2. a system bus board; 2-1, bus board data bus interface; 2-2, bus board address bus interface; 2-3, controlling a bus interface by a bus board; 3. a graphic liquid crystal display; 4. a programmable parallel interface; 5. a DMA data transfer controller; 6. a programmable serial controller; 7. a first digital-to-analog conversion module; 8. a timing/counter module; 9. a second digital-to-analog conversion module; 10. an interrupt control module; 11. a keyboard display controller; 12. a reset circuit; 13. a relay control module; 14. a DC motor control module; 15. a stepping motor; 16. a dot matrix display module; 17. a level conversion module; 18. a keyboard; 19. a digital display tube; 20. a system monitoring module; 21. a user data module; 22. a serial communication module; 23. a USB communication module; 24. an Ethernet communication module; 25. a bidirectional data buffer; 26. an address latch; 27. a system control circuit.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.
Example (b): as shown in figures 1-3, the novel single chip microcomputer and configuration comprehensive experiment system comprises a single chip microcomputer CPU1, a system bus board 2, a graphic liquid crystal display 3, a programmable parallel interface 4, a DMA data transmission controller 5, a programmable serial controller 6, a first digital-to-analog conversion module 7, a timing/counter module 8, a second digital-to-analog conversion module 9, an interrupt control module 10 and a keyboard display controller 11, and is characterized in that the single chip microcomputer CPU1 is a double CPU and is integrated in the system bus board 2, the system bus board 2 is provided with a bus board data bus interface 2-1, a bus board address bus interface 2-2 and a bus board control bus interface 2-3, and the bus board data bus interface 2-1 and the bus board control bus interface 2-3 are both bidirectionally connected with the graphic liquid crystal display 3 and the programmable parallel interface 4, The system comprises a DMA data transmission controller 5, a programmable serial controller 6, a first digital-to-analog conversion module 7, a timing/counter module 8, a second digital-to-analog conversion module 9, an interrupt control module 10 and a keyboard display controller 11, wherein a bus board address bus interface 2-2 is connected with a graphic liquid crystal display 3, a programmable parallel interface 4, the DMA data transmission controller 5, the programmable serial controller 6, the timing/counter module 8, the second digital-to-analog conversion module 9, the interrupt control module 10 and the keyboard display controller 11 in a one-way mode.
The keyboard display controller comprises a keyboard 18 and a digital display tube 19, wherein the keyboard 18 is connected with the keyboard display controller 11 in a one-way mode, and the keyboard display controller 11 is connected with the digital display tube 19 in a one-way mode.
The system further comprises a reset circuit 12, a relay control module 13, a direct current motor control module 14, a stepping motor 15 dot matrix display module 16 and a level conversion module 17, wherein the reset circuit 12 is connected with the graphic liquid crystal display 3, the programmable parallel interface 4, the DMA data transmission controller 5 and the programmable serial controller 6 in a one-way mode, the programmable parallel interface 4 is connected with the relay control module 13, the direct current motor control module 14 and the stepping motor 15 dot matrix display module 16 in a one-way mode, and the level conversion module 17 is connected with the programmable serial controller 6 and a computer in a two-way mode.
The single-chip microcomputer CPU1 comprises a 486DXCPU module and a 386EXCPU module, the 486DXCPU module and the 386EXCPU module are respectively provided with a power supply module, a reset module and a clock module, the 486DXCPU module and the 386EXCPU module are also provided with a CPU data bus interface 1-1, a CPU address bus interface 1-2 and a CPU control bus interface 1-3, the CPU data bus interface 1-1 is bidirectionally connected with a bus board data bus interface 2-1, the CPU control bus interface 1-3 is bidirectionally connected with the bus board control bus interface 2-3, and the CPU address bus interface 1-2 is unidirectionally connected with the bus board address bus interface 2-2.
Wherein, a bidirectional data buffer 25, an address latch 26 and a system control circuit 27 are respectively connected in series between the CPU data bus interface 1-1 and the bus board data bus interface 2-1, between the CPU address bus interface 1-2 and the bus board address bus interface 2-2, and between the CPU control bus interface 1-3 and the bus board control bus interface 2-3, the bidirectional data buffer 25 is unidirectionally connected with the address latch 26, and the address latch 26 is unidirectionally connected with the system control circuit 27
A system monitoring module 20, a user data module 21, a serial communication module 22, a USB communication module 23 and an Ethernet communication module 24 are arranged between the CPU data bus interface 1-1 and the bus board data bus interface 2-1, between the CPU address bus interface 1-2 and the bus board address bus interface 2-2, and between the CPU control bus interface 1-3 and the bus board control bus interface 2-3, and the serial communication module 22, the USB communication module 23 and the Ethernet communication module 24 can be interconnected with a 32-bit computer/system.
The graphic liquid crystal display 3 is a graphic liquid crystal display LCD12864, the programmable parallel interface 4 is a programmable parallel interface 8255A, the DMA data transfer controller 5 is a DMA controller 8237, the programmable serial controller 6 is a programmable serial controller 16C550, the first digital-to-analog conversion module 7 is a digital-to-analog conversion DAC0832, the timing/counter module 8 is a programmable timing/counter 8253A, the second digital-to-analog conversion module 9 is a digital-to-analog conversion ADC0809, the interrupt control module 10 is an interrupt control 8259, and the keyboard display controller 11 is a keyboard display controller 8279.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. A novel single chip microcomputer and configuration comprehensive experiment system comprises a single chip microcomputer CPU (1), a system bus board (2), a graphic liquid crystal display (3), a programmable parallel interface (4), a DMA data transmission controller (5), a programmable serial controller (6), a first digital-to-analog conversion module (7), a timing/counter module (8), a second digital-to-analog conversion module (9), an interrupt control module (10) and a keyboard display controller (11), and is characterized in that the single chip microcomputer CPU (1) is a double CPU and is integrated in the system bus board (2), a bus board data bus interface (2-1), a bus board address bus interface (2-2) and a bus board control bus interface (2-3) are arranged in the system bus board (2), and the bus board data bus interface (2-1) and the bus board control bus interface (2-3) are both connected with the graphic liquid crystal display (2-3) in a bidirectional mode 3) The bus board address bus interface (2-2) is connected with the graphic liquid crystal display (3), the programmable parallel interface (4), the DMA data transmission controller (5), the programmable serial controller (6), the first digital-to-analog conversion module (7), the timing/counter module (8), the second digital-to-analog conversion module (9), the interrupt control module (10) and the keyboard display controller (11) in a one-way mode.
2. The novel comprehensive experiment system for the single chip microcomputer and the configuration according to claim 1, further comprising a reset circuit (12), a relay control module (13), a direct current motor control module (14), a stepping motor (15), a dot matrix display module (16) and a level conversion module (17), wherein the reset circuit (12) is connected with the graphic liquid crystal display (3), the programmable parallel interface (4), the DMA data transmission controller (5) and the programmable serial controller (6) in a one-way manner, the programmable parallel interface (4) is connected with the relay control module (13), the direct current motor control module (14) and the dot matrix display module (16) of the stepping motor (15) in a one-way manner, and the level conversion module (17) is connected with the programmable serial controller (6) and the computer in a two-way manner.
3. A novel comprehensive experiment system for single chip microcomputer and configuration as claimed in claim 1, further comprising a keyboard (18) and a digital display tube (19), wherein the keyboard (18) is unidirectionally connected with the keyboard display controller (11), and the keyboard display controller (11) is unidirectionally connected with the digital display tube (19).
4. The comprehensive experiment system for the new type of single chip microcomputer and configuration as claimed in claim 1, the single-chip microcomputer CPU (1) comprises a 486DXCPU module and a 386EXCPU module, the 486DXCPU module and the 386EXCPU module are respectively provided with a power supply module, a reset module and a clock module, the 486DXCPU module and 386EXCPU module are also provided with a CPU data bus interface (1-1), a CPU address bus interface (1-2) and a CPU control bus interface (1-3), the CPU data bus interface (1-1) is connected with the bus board data bus interface (2-1) in a bidirectional way, the CPU control bus interface (1-3) is connected with the bus board control bus interface (2-3) in a bidirectional way, the CPU address bus interface (1-2) is connected with the bus board address bus interface (2-2) in a unidirectional mode.
5. The system of claim 1, wherein a bidirectional data buffer (25), an address latch (26) and a system control circuit (27) are respectively connected in series between the CPU data bus interface (1-1) and the bus board data bus interface (2-1), between the CPU address bus interface (1-2) and the bus board address bus interface (2-2), and between the CPU control bus interface (1-3) and the bus board control bus interface (2-3), the bidirectional data buffer (25) is connected with the address latch (26) in one way, and the address latch (26) is connected with the system control circuit (27) in one way.
6. The system for the comprehensive experiment of the singlechip microcomputer and the configuration as claimed in claim 1, wherein a system monitoring module (20), a user data module (21), a serial communication module (22), a USB communication module (23) and an Ethernet communication module (24) are arranged between the CPU data bus interface (1-1) and the bus board data bus interface (2-1), between the CPU address bus interface (1-2) and the bus board address bus interface (2-2), and between the CPU control bus interface (1-3) and the bus board control bus interface (2-3), and the serial communication module (22), the USB communication module (23) and the Ethernet communication module (24) are all interconnected with a 32-bit computer/system.
7. The system according to claim 1, wherein the graphic LCD display (3) is a graphic LCD display LCD12864, the programmable parallel interface (4) is a programmable parallel interface 8255A, the DMA data transfer controller (5) is a DMA controller 8237, the programmable serial controller (6) is a programmable serial controller 16C550, the first DAC module (7) is a DAC0832, the timer/counter module (8) is a programmable timer/counter 8253A, the second DAC 0809 is a second DAC 0809, the interrupt control module (10) is an interrupt control 8259, and the keyboard display controller (11) is a keyboard display controller 8279.
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| CN202010206064.2A CN111276028A (en) | 2020-03-20 | 2020-03-20 | Novel single-chip microcomputer and configuration comprehensive experiment system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112509394A (en) * | 2020-12-16 | 2021-03-16 | 刘芳 | Bus type programming teaching aid |
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| EP0171940A1 (en) * | 1984-07-24 | 1986-02-19 | BRITISH TELECOMMUNICATIONS public limited company | A direct memory access device and a method of using the device in a data transfer system |
| CN203882503U (en) * | 2014-04-24 | 2014-10-15 | 启东计算机厂有限公司 | Single chip microcomputer and configuration integrated experiment system |
| CN104504974A (en) * | 2014-12-22 | 2015-04-08 | 常州大学 | Experiment instrument for designing and developing single-chip microcomputer |
| CN206574351U (en) * | 2017-01-03 | 2017-10-20 | 昆明理工大学 | A kind of SCM Based teaching platform |
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| US4344127A (en) * | 1980-08-28 | 1982-08-10 | The Bendix Corporation | Microprocessor based process control system |
| EP0171940A1 (en) * | 1984-07-24 | 1986-02-19 | BRITISH TELECOMMUNICATIONS public limited company | A direct memory access device and a method of using the device in a data transfer system |
| CN203882503U (en) * | 2014-04-24 | 2014-10-15 | 启东计算机厂有限公司 | Single chip microcomputer and configuration integrated experiment system |
| CN104504974A (en) * | 2014-12-22 | 2015-04-08 | 常州大学 | Experiment instrument for designing and developing single-chip microcomputer |
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