CN111261710A - Insulated gate bipolar transistor and method of making the same - Google Patents

Abstract

The invention relates to the technical field of power semiconductor chips, and discloses an insulated gate bipolar transistor and a preparation method thereof. The transistor comprises a substrate, a collector layer and a device layer are arranged on the substrate, and the device layer is arranged on the substrate. The projection includes at least two opposite sides having a set distance from the edge of the collector layer projected on the substrate, the outer surface of the device layer is covered with a dielectric layer, and the side of the dielectric layer facing away from the device layer is formed with an emitter bonding metal layer and a collector bonding metal layer is provided in the region outside the device layer on the side of the collector layer away from the substrate. In the above transistor, when the transistor is energized, the electrons pass through the emitter bonding metal layer, the device layer, the collector layer, and the collector bonding metal layer in sequence to realize current conduction, so that the current passing path does not pass through the substrate, so that the In the transistor, a thicker substrate can be used to carry an ultra-thin device layer, and an ultra-thin thinning process and related complicated steps are not required, thereby reducing the manufacturing cost and manufacturing difficulty.

Description

Insulated gate bipolar transistor and method of making the same

technical field

The invention relates to the technical field of power semiconductor chips, in particular to an insulated gate bipolar transistor and a preparation method thereof.

Background technique

The FS-IGBT (Field Stop Insulated Gate Bipolar Transistor) with a field stop structure is the most advanced IGBT device at present. Stop), thereby reducing the thickness of the N-type withstand voltage layer and reducing the turn-on voltage drop and power loss of the device. Compared with other PT-IGBT and NPT-IGBT structures, its performance has been greatly improved, and it has gradually become the mainstream design in the IGBT field; the structure of FS-IGBT in the prior art is shown in Figure 1, including the emitter bonding metal layer 05 , dielectric layer 04 , device layer 03 , collector layer 02 and collector bonding metal layer 06 .

However, in terms of process technology, in order to achieve this characteristic of field cut-off, the thickness of the substrate layer must be ground to a very thin thickness, which brings great difficulty to the manufacture of the entire FS-IGBT chip.

SUMMARY OF THE INVENTION

The invention provides an insulated gate bipolar transistor and a preparation method thereof. When the insulated gate bipolar transistor is energized, the current passes through the device layer and then is input into the collector bonding metal layer through the collector layer to realize the conduction of the current. It avoids the current passing through the substrate, so that the substrate does not need to be ground, and the manufacturing cost and manufacturing difficulty are reduced.

For achieving the above object, the present invention provides the following technical solutions:

A transistor includes a substrate, a collector layer is arranged on the substrate, a device layer is arranged on the side of the collector layer away from the substrate, and the projected area of the device layer on the substrate is smaller than the projected area of the collector layer on the substrate, and the projection of the device layer on the substrate includes at least two opposite sides and the collector layer on the substrate. The edge of the projection has a set distance, and the outer surface of the device layer is covered with a dielectric layer, the side of the dielectric layer away from the device layer is formed with an emitter bonding metal layer, and the collector layer is away from all A collector bonding metal layer is provided in a region outside the device layer on one side of the substrate.

In the above transistor, a collector layer and a device layer are sequentially arranged on the substrate, and the projected area of the device layer on the substrate is smaller than the projected area of the collector layer on the substrate, and the projection of the device layer on the substrate has at least There is a set distance between the two opposite sides and the edge of the projection of the collector on the substrate, so that part of the surface of the side of the collector facing away from the substrate is exposed, so that collector bonding can be provided on the exposed surface of the collector. metal layer, so that the collector bonding metal layer is electrically connected to the collector; the outer surface of the device layer is covered with a dielectric layer, which realizes the insulation treatment of the device layer, so that when the current passes through the device layer, the current can be directed It flows in the direction of the collector, that is, when the transistor is energized, the current is input into the device layer through the metal layer, and into the collector layer through the device layer, and finally input from the collector layer into the collector bonding metal layer. The current is output through the collector bonding metal layer, so that the conduction path of the current does not pass through the substrate, so that a thicker monocrystalline silicon substrate can be used to carry the ultra-thin device layer during the preparation of the transistor, preventing ultra-thin The device layer is damaged during the preparation and packaging process, which improves the reliability of the transistor, and does not require an ultra-thin thinning process and related complex steps, thereby simplifying the transistor preparation process, reducing the manufacturing cost and manufacturing difficulty.

Preferably, the device layer includes a field stop layer and a device withstand voltage layer sequentially disposed on the side of the collector layer away from the substrate.

Preferably, a component area is formed on the side of the device withstanding voltage layer away from the substrate.

Preferably, the set distance is greater than zero.

Preferably, the range of the set distance is less than or equal to 400 microns.

Preferably, the thickness of the sidewalls formed along the direction perpendicular to the substrate of the dielectric layer is greater than or equal to 1 micrometer.

The present invention also provides a method for preparing a transistor, comprising:

preparing a collector layer on the substrate;

preparing an epitaxial layer on the side of the collector layer facing away from the substrate;

etching the epitaxial layer to form a device layer, and the projected area of the device layer on the substrate is smaller than the projected area of the collector layer on the substrate to expose the collector layer, and The projection of the device layer on the substrate includes at least two opposite sides having a set distance from the edge of the projection of the collector layer on the substrate;

preparing a dielectric layer covering the device layer on the outer surface of the device layer;

patterning the dielectric layer;

A metal layer covering the dielectric layer is prepared on the outer surface of the dielectric layer, and the projected area of the metal layer on the substrate is larger than the projected area of the dielectric layer on the substrate;

patterning the metal layer to form an emitter-bonded metal layer on the side of the dielectric layer facing away from the device layer and a collector on the side of the collector layer facing away from the substrate Bond metal layers.

Preferably, the preparation of the epitaxial layer on the side of the collector layer away from the substrate includes:

preparing a field stop layer on the side of the collector layer facing away from the substrate;

A device withstand voltage layer is prepared on the side of the field stop layer facing away from the collector layer.

Preferably, the epitaxial layer is etched to form a device layer, and the projected area of the device layer on the substrate is smaller than the projected area of the collector layer on the substrate, so as to expose the collector layer, and the Before the projection of the device layer on the substrate includes at least two opposite sides having a set distance from the edge of the projection of the collector layer on the substrate, it further includes:

A component layer is prepared on the side of the device withstanding voltage layer facing away from the substrate.

Preferably, preparing the component layer on the side of the device pressure-resistant layer away from the substrate includes:

A plurality of grooves are formed by etching on the side of the device pressure-resistant layer away from the field stop layer, and the grooves are filled with materials for preparing components to form a component layer, where the component layer is The corresponding region of the device withstand voltage layer is the device forming region.

Description of drawings

1 is a schematic structural diagram of a transistor in the prior art;

2 is a schematic cross-sectional structure diagram of a transistor provided by the present invention;

3 is a schematic structural diagram of a transistor provided by the present invention;

4 is a schematic structural diagram of step 1 in the method for preparing a transistor provided by the present invention;

5 is a schematic structural diagram of step 2 in the method for preparing a transistor provided by the present invention;

6 is a schematic structural diagram of step 3 in the method for preparing a transistor provided by the present invention;

7 is a schematic structural diagram of step 4 in the method for preparing a transistor provided by the present invention;

8 is a schematic structural diagram of step 5 in the method for preparing a transistor provided by the present invention;

9 is a schematic structural diagram of step 7 in the method for preparing a transistor provided by the present invention;

10 is a schematic structural diagram of step 8 in the method for preparing a transistor provided by the present invention;

11 is a schematic structural diagram of step 9 in the method for preparing a transistor provided by the present invention;

FIG. 12 is a schematic structural diagram of step 10 in the method for manufacturing a transistor provided by the present invention.

Icons: 1-substrate; 02, 2-collector layer; 03, 3-device layer; 31-field stop layer; 32-device withstand voltage layer; 33-component forming area; 04,4-dielectric layer; 05 , 5-emitter bonding metal layer; 06, 6-collector bonding metal layer; 7-photoresist; 8-metal layer; a-first set distance; b-second set distance.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

Referring to FIGS. 2 to 3 , a transistor provided by an embodiment of the present invention includes a substrate 1 , a collector layer 2 is provided on the substrate 1 , and a device layer 3 is provided on the side of the collector layer 2 away from the substrate 1 . , the projected area of the device layer 3 on the substrate 1 is smaller than the projected area of the collector layer 2 on the substrate 1, and the projection of the device layer 3 on the substrate 1 includes at least two opposite sides and the collector layer 2 The edge of the projection on the substrate 1 has a set distance, and the outer surface of the device layer 3 is covered with a dielectric layer 4, and the side of the dielectric layer 4 away from the device layer 3 is formed with an emitter bonding metal layer 5, a collector electrode The side of the layer 2 facing away from the substrate 1 is provided with a collector bonding metal layer 6 in the region outside the device layer 3 .

In the above transistor, a collector layer 2 and a device layer 3 are arranged on the substrate 1 in turn, and the projected area of the device layer 3 on the substrate 1 is smaller than the projected area of the collector layer 2 on the substrate 1, and the device layer 3 The projection on the substrate 1 has at least two opposite sides and there is a set distance from the edge of the projection of the collector on the substrate 1, so that part of the surface of the side of the collector facing away from the substrate 1 is exposed, so that the The collector bonding metal layer 6 is arranged on the exposed surface of the collector, so that the collector bonding metal layer 6 is electrically connected with the collector; the outer surface of the device layer 3 is covered with a dielectric layer 4, which realizes the connection between the device layer 3 and the device layer 3. Insulation treatment, so that when the current passes through the device layer 3, the current can flow out in the direction of the collector, that is, when the transistor is energized, the electrons move to the device layer 3 through the emitter bonding metal layer 5, and pass through the device. The layer 3 moves to the collector layer 2, and finally moves from the collector layer 2 to the collector bonding metal layer 6, and the current conduction is realized through the collector bonding metal layer 6, so that the current passing path does not pass through the lining. Bottom 1, so that a thicker monocrystalline silicon substrate can be used to carry the ultra-thin device layer in the preparation process of the transistor, preventing the ultra-thin device layer from being damaged during the preparation and packaging process, and improving the reliability of the transistor, without the need for ultra-thin device layers. The thinning process and related complex steps simplify the fabrication process of the transistor and reduce the fabrication cost and difficulty.

As an embodiment of the above-mentioned setting distance, the range of the setting distance is less than or equal to 400 microns.

As shown in FIG. 2 , as an embodiment of the above-mentioned setting distance, the projection of the device layer 3 on the substrate 1 includes two opposite sides and the edge of the projection of the collector layer 2 on the substrate 1 has a set distance. The fixed distances are respectively the first set distance a and the second set distance b, the first set distance and the second set distance are both less than 400 microns, and the first set distance and the second set distance, at most One set distance is 0; in this embodiment, the first set distance a is greater than the second set distance b.

Specifically, the device layer 3 includes a field stop layer 31 and a device withstand voltage layer 32 sequentially disposed on the side of the collector layer 2 away from the substrate 1 .

Specifically, a component region is formed on the side of the device withstand voltage layer 32 away from the substrate 1 .

Specifically, the component area includes guard rings, trench gates, and P-N junctions.

Specifically, the thickness of the sidewalls formed along the direction perpendicular to the substrate 1 of the dielectric layer 4 is greater than or equal to 1 μm.

As an embodiment of the substrate 1 described above, the substrate 1 is made of single crystal silicon.

As an embodiment of the above-mentioned collector layer 2 , the above-mentioned collector layer 2 is formed by ion implantation of P-type impurity boron to form a P-type doped layer as the collector layer 2 in the present application.

As shown in FIG. 4 to FIG. 12 , an embodiment of the present invention further provides a method for fabricating a transistor, including:

A collector layer 2 is prepared on the substrate 1;

An epitaxial layer is prepared on the side of the collector layer 2 away from the substrate 1;

The epitaxial layer is etched to form a device layer 3, and the projected area of the device layer 3 on the substrate 1 is smaller than the projected area of the collector layer 2 on the substrate 1, so as to expose the collector layer 2, and the device layer 3 is on the substrate 1. The projection on the substrate 1 includes at least two opposite sides having a set distance from the edge of the projection of the collector layer 2 on the substrate 1;

A dielectric layer 4 covering the device layer 3 is prepared on the outer surface of the device layer 3;

patterning the dielectric layer 4;

A metal layer 8 covering the dielectric layer 4 is prepared on the outer surface of the dielectric layer 4, and the projected area of the metal layer 8 on the substrate 1 is larger than the projected area of the dielectric layer 4 on the substrate 1;

The metal layer 8 is patterned to form an emitter-bonded metal layer 5 and a gate-bonded metal layer located on the side of the dielectric layer 4 away from the device layer 3 and formed on the side of the collector layer 2 away from the substrate 1 The collector bonding metal layer 6.

In the preparation method of the above-mentioned transistor, the collector layer 2 and the epitaxial layer are sequentially prepared on the substrate 1, and the epitaxial layer is etched to form the device layer 3, so that the part of the surface of the collector on the side away from the substrate 1 is exposed, A dielectric layer 4 is prepared on the outer surface of the device layer 3 , the device layer 3 is insulated, and then a metal layer 8 is prepared on the outer surface of the dielectric layer 4 , and the metal layer 8 is etched to form an emitter bond Bonding metal layer 5, gate bonding metal layer and collector bonding metal layer 6, in this preparation method, by setting metal layer 8 and etching metal layer 8 to form emitter bonding metal layer 5, gate bond The bonding metal layer and the collector bonding metal layer 6 realize the simultaneous preparation of the emitter bonding metal layer 5, the gate bonding metal layer and the collector bonding metal layer 6, which simplifies the preparation method of the transistor and improves the preparation process. efficiency.

Specifically, an epitaxial layer is prepared on the side of the collector layer 2 away from the substrate 1, including:

A field stop layer 31 is prepared on the side of the collector layer 2 away from the substrate 1;

The device withstand voltage layer 32 is prepared on the side of the field stop layer 31 facing away from the collector layer 2 .

The above-mentioned field stop layer 31 and device withstand voltage layer 32 are formed by an epitaxial process.

Specifically, the epitaxial layer is etched to form the device layer 3, and the projected area of the device layer 3 on the substrate 1 is smaller than the projected area of the collector layer 2 on the substrate 1 to expose the collector layer 2, and Before the projection of the device layer 3 on the substrate 1 includes at least two opposite sides having a set distance from the edge of the projection of the collector layer 2 on the substrate 1, it also includes:

The component layer 3 is prepared on the side of the device withstand voltage layer 32 away from the substrate 1 .

Specifically, the component layer 3 is prepared on the side of the device withstand voltage layer 32 away from the substrate 1, including:

A plurality of grooves are formed by etching on the side of the device withstand voltage layer 32 away from the field stop layer 31 , and the grooves are filled with materials for preparing components to form a component layer 3 . The region of the device withstand voltage layer 32 is the device formation region 33 .

Specifically, the epitaxial layer is etched to form the device layer 3, and the projected area of the device layer 3 on the substrate 1 is smaller than the projected area of the collector layer 2 on the substrate 1 to expose the collector layer 2, and the device The projection of layer 3 on substrate 1 includes at least two opposite sides having a set distance from the edge of the projection of collector layer 2 on substrate 1, including:

Coat the photoresist 7 on the side of the component forming region 33 away from the substrate 1;

The area other than the photoresist 7 is etched to leak out the collector layer 2;

Strip photoresist 7.

As mentioned above, when the device layer 3 is etched, a layer of photoresist 7 is coated on the component forming area 33 to prevent damage to the component forming area 33 during the etching process.

Specifically, the dielectric layer 4 is prepared by a chemical vapor deposition process.

Specifically, the metal layer 8 is prepared by a magnetron sputtering process.

In this embodiment, the preparation method of the transistor specifically includes:

Step 1: prepare the collector layer 2 on the substrate 1;

Step 2: preparing an epitaxial layer on the side of the collector layer 2 away from the substrate 1;

Step 3: Etch the epitaxial layer to form a device layer 3, and the projected area of the device layer 3 on the substrate 1 is smaller than the projected area of the collector layer 2 on the substrate 1 to expose the collector layer 2, and the device The projection of the layer 3 on the substrate 1 comprises at least two opposite sides having a set distance from the edge of the projection of the collector layer 2 on the substrate 1;

Step 4: Coating photoresist 7 on the side of the component forming area 33 away from the substrate 1;

Step 5: Etch the area other than the photoresist 7 to leak out the collector layer 2;

Step 6: Strip photoresist 7.

Step 7: preparing a dielectric layer 4 covering the device layer 3 on the outer surface of the device layer 3;

Step 8: patterning the dielectric layer 4;

Step 9: preparing a metal layer 8 covering the dielectric layer 4 on the outer surface of the dielectric layer 4, and the projected area of the metal layer 8 on the substrate 1 is larger than the projected area of the dielectric layer 4 on the substrate 1;

Step 10: Patterning the metal layer 8 to form the emitter bonding metal layer 5 on the side of the dielectric layer 4 away from the device layer, the gate bonding metal layer and the metal layer 5 on the collector layer 2 away from the substrate 1 The collector on one side is bonded to the metal layer 6 .

Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the present invention. Thus, provided that these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims (10)

1. The insulated gate bipolar transistor is characterized by comprising a substrate, wherein a collector layer is arranged on the substrate, a device layer is arranged on one side, away from the substrate, of the collector layer, the projection area of the device layer on the substrate is smaller than that of the collector layer on the substrate, the projection of the device layer on the substrate comprises at least two opposite side edges, a set distance is reserved between the edge of the projection of the collector layer on the substrate, a dielectric layer is coated on the outer surface of the device layer, an emitter bonding metal layer is formed on one side, away from the device layer, of the dielectric layer, and a collector bonding metal layer is arranged in a region, away from the device layer, of one side, away from the substrate, of the collector layer.

2. The insulated gate bipolar transistor of claim 1, wherein the device layer comprises a field stop layer and a device voltage-withstanding layer sequentially disposed on a side of the collector layer facing away from the substrate.

3. The IGBT of claim 2, wherein a device region is formed on a side of the device voltage withstand layer facing away from the substrate.

4. The igbt of claim 1, wherein the set distance is greater than zero.

5. The IGBT of claim 4, wherein the set distance is in a range of 400 microns or less.

6. The igbt of claim 1, wherein the dielectric layer has a sidewall thickness in a direction perpendicular to the substrate in a range of less than or equal to 1 μm.

7. A preparation method of an insulated gate bipolar transistor is characterized by comprising the following steps:

preparing a collector layer on a substrate;

preparing an epitaxial layer on the side of the collector layer, which faces away from the substrate;

etching the epitaxial layer to form a device layer, wherein the projection area of the device layer on the substrate is smaller than the projection area of the collector layer on the substrate to expose the collector layer, and the projection of the device layer on the substrate comprises at least two opposite side edges and a set distance from the edge of the projection of the collector layer on the substrate;

preparing a dielectric layer wrapping the device layer on the outer surface of the device layer;

patterning the dielectric layer;

preparing a metal layer wrapping the dielectric layer on the outer surface of the dielectric layer, wherein the projection area of the metal layer on the substrate is larger than that of the dielectric layer on the substrate;

and patterning the metal layer to form an emitter bonding metal layer on one side of the dielectric layer, which is far away from the device layer, and a collector bonding metal layer on one side of the collector layer, which is far away from the substrate.

8. The method for manufacturing the insulated gate bipolar transistor according to claim 7, wherein the manufacturing the epitaxial layer on the side of the collector layer, which is away from the substrate, comprises:

preparing a field stop layer on the side of the collector layer, which faces away from the substrate;

and preparing a device voltage-withstanding layer on one side of the field stop layer, which is far away from the collector layer.

9. The method according to claim 8, wherein before the etching the epitaxial layer to form the device layer and the area of the projection of the device layer on the substrate is smaller than the area of the projection of the collector layer on the substrate to expose the collector layer, and the projection of the device layer on the substrate includes at least two opposite sides having a set distance from the edge of the projection of the collector layer on the substrate, the method further comprises:

and preparing a component layer on one side of the component voltage-resisting layer, which is far away from the substrate.

10. The method for manufacturing the insulated gate bipolar transistor according to claim 9, wherein the manufacturing of the device layer on the side of the device voltage-withstanding layer away from the substrate comprises:

and etching one side of the device pressure-resistant layer, which is far away from the field stop layer, to form a plurality of grooves, and filling materials for preparing components in the grooves to form a component layer, wherein the region of the device pressure-resistant layer, which corresponds to the component layer, is a component forming region.

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