CN111244041B - 包括两种不同导电材料的芯片接触元件的封装 - Google Patents
包括两种不同导电材料的芯片接触元件的封装 Download PDFInfo
- Publication number
- CN111244041B CN111244041B CN201911164576.0A CN201911164576A CN111244041B CN 111244041 B CN111244041 B CN 111244041B CN 201911164576 A CN201911164576 A CN 201911164576A CN 111244041 B CN111244041 B CN 111244041B
- Authority
- CN
- China
- Prior art keywords
- contact structure
- contact
- package
- pad
- sealing body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004020 conductor Substances 0.000 title claims abstract description 74
- 238000007789 sealing Methods 0.000 claims abstract description 141
- 239000010410 layer Substances 0.000 claims description 84
- 238000000034 method Methods 0.000 claims description 70
- 229910052751 metal Inorganic materials 0.000 claims description 68
- 239000002184 metal Substances 0.000 claims description 68
- 239000000463 material Substances 0.000 claims description 41
- 238000004519 manufacturing process Methods 0.000 claims description 17
- 239000011888 foil Substances 0.000 claims description 10
- 230000001681 protective effect Effects 0.000 claims description 8
- 238000004140 cleaning Methods 0.000 claims description 7
- 238000005520 cutting process Methods 0.000 claims description 4
- 239000002346 layers by function Substances 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 230000003213 activating effect Effects 0.000 claims 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 65
- 239000010949 copper Substances 0.000 description 62
- 229910052802 copper Inorganic materials 0.000 description 61
- 239000004065 semiconductor Substances 0.000 description 36
- 229910052782 aluminium Inorganic materials 0.000 description 33
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 33
- 230000008569 process Effects 0.000 description 22
- 238000000465 moulding Methods 0.000 description 14
- 238000001465 metallisation Methods 0.000 description 10
- 239000000758 substrate Substances 0.000 description 8
- 150000001875 compounds Chemical class 0.000 description 7
- 238000004806 packaging method and process Methods 0.000 description 7
- 230000002093 peripheral effect Effects 0.000 description 7
- 238000007747 plating Methods 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 239000007769 metal material Substances 0.000 description 5
- 150000002739 metals Chemical class 0.000 description 5
- 239000000565 sealant Substances 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 238000005476 soldering Methods 0.000 description 5
- 239000000956 alloy Substances 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000008393 encapsulating agent Substances 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 description 3
- 238000005452 bending Methods 0.000 description 3
- 239000011889 copper foil Substances 0.000 description 3
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- 239000000654 additive Substances 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000012778 molding material Substances 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 229920003023 plastic Polymers 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000012812 sealant material Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 238000005266 casting Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003985 ceramic capacitor Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 239000012777 electrically insulating material Substances 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000007730 finishing process Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 1
- 229910021389 graphene Inorganic materials 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000007670 refining Methods 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for individual devices of subclass H10D
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/43—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
- H01L2224/13082—Two-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/13124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/24247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37025—Plural core members
- H01L2224/3703—Stacked arrangements
- H01L2224/37032—Two-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/37117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/37124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/37147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/4013—Connecting within a semiconductor or solid-state body, i.e. fly strap, bridge strap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/404—Connecting portions
- H01L2224/40475—Connecting portions connected to auxiliary connecting means on the bonding areas
- H01L2224/40491—Connecting portions connected to auxiliary connecting means on the bonding areas being an additional member attached to the bonding area through an adhesive or solder, e.g. buffer pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45025—Plural core members
- H01L2224/4503—Stacked arrangements
- H01L2224/45032—Two-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
- H01L2224/48476—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
- H01L2224/48477—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding)
- H01L2224/48478—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball
- H01L2224/4848—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73205—Bump and strap connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73207—Bump and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73209—Bump and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73221—Strap and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
- H01L2924/15747—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
提供了一种封装(100),该封装包括具有至少一个焊盘(104)的电子芯片(102)、至少部分地密封电子芯片(102)的密封体(106),以及从至少一个焊盘(104)延伸穿过密封体(106)以相对于密封体(106)被暴露的导电接触元件(108),其中导电接触元件(108)包括至少一个焊盘(104)上由第一导电材料制成的第一接触结构(110),并包括由第二导电材料制成且相对于密封体(106)被暴露的第二接触结构(112)。至少一个焊盘中的至少一个至少具有包括第一导电材料或由第一导电材料制成的表面部分。
Description
技术领域
本发明涉及封装以及制造封装的方法。
背景技术
封装可以被表示为具有电连接的被密封电子芯片,所述电连接从密封体延伸出来并被安装到电子外围装置,例如印刷电路板上。
封装成本是本行业的重要驱动力。与此相关的是性能、尺度和可靠性。不同的封装方案是多种多样的,必须要解决应用的需求。
发明内容
可能需要以简单且可靠的方式来制造封装。
根据示范性实施例,提供了一种封装,所述封装包括具有至少一个焊盘的电子芯片、至少部分地密封所述电子芯片的密封体,以及从所述至少一个焊盘延伸穿过所述密封体以相对于所述密封体被暴露的导电接触元件,其中所述导电接触元件包括所述至少一个焊盘上由第一导电材料制成的第一接触结构,并且包括由第二导电材料制成且相对于所述密封体被暴露的第二接触结构。所述至少一个焊盘的至少一个至少具有包括所述第一导电材料或由所述第一导电材料制成的表面部分。
根据另一示范性实施例,提供了一种封装,所述封装包括至少部分导电的芯片载体、安装于芯片载体上的电子芯片,其中所述电子芯片设置有具有包括第一金属的外表面的焊盘、从焊盘延伸的导电接触元件,以及至少部分密封所述接触元件和所述电子芯片的密封体,其中所述接触元件包括位于所述至少一个焊盘上且包括第一金属的第一接触结构,并包括具有未被所述密封体覆盖的暴露表面并包括第二金属的第二接触结构。
根据又一示范性实施例,提供了一种制造封装的方法,其中所述方法包括通过密封体至少部分地密封具有至少一个焊盘的电子芯片,设置从所述至少一个焊盘延伸穿过所述密封体以相对于所述密封体被暴露的导电接触元件,以及配置所述导电接触元件以包括所述至少一个焊盘上由第一导电材料制成的第一接触结构,并包括由第二导电材料制成且相对于所述密封体被暴露的第二接触结构。所述至少一个焊盘的至少一个至少具有包括第一导电材料或由所述第一导电材料制成的表面部分。
根据示范性实施例,可以提供一种封装和一种制造这种封装的制造方法,其中导电接触元件具有直接接触芯片焊盘的第一表面,并具有相对于密封体被暴露的另一第二表面,以允许从所密封的封装的外部电接触被密封的芯片。所述接触元件的接触芯片焊盘的第一接触结构由与接触元件的被暴露部分,即第二接触结构不同的另一种导电材料制成。由此,可以例如利用与芯片焊盘相同的导电材料接触芯片焊盘,并利用优选由与第二接触结构相同的材料制成的另一导电结构接触第二接触结构的被暴露部分。说明性地讲,所述接触元件可以充当鲁棒的导电材料界面。
例如,可以提供双金属或多金属一体形成的接触元件,允许以简单且高效的方式提供用于被密封芯片焊盘的电连接,而无需一方面在芯片焊盘和接触元件以及另一方面在接触元件和外部导电接触结构的不同金属之间建立连接。这简化了芯片的封装并为芯片封装提供了简单且鲁棒的方案。接触元件可以通过机械鲁棒且稳定的方式接触芯片焊盘,同时第二接触结构延伸超过密封体的表面部分也保持自由,以在第二接触结构和电子外围器件之间建立更多导电连接。换言之,第二接触结构的被暴露部分可以充当“封装焊盘”。这确保了比使用直接接触电子芯片的键合引线更稳定更可靠的机械连接。将键合引线直接连接到电子芯片可能需要在敏感的半导体芯片上施加一些压力,这可能导致损伤后者的危险。通过使用可能导致更软引线键合和一般更容易连接到芯片焊盘的双金属或多金属接触元件,可以减小对芯片的机械冲击,由此确保在封装期间对芯片(例如,半导体管芯)有适当保护。此外,以双金属或多金属堆叠的形式连接键合引线使得能够使用所有种类的芯片顶部金属,尤其是利用其顶部金属化部的现有技术。
根据示范性实施例,所述至少一个焊盘的至少一个至少具有由第一导电材料制成的表面部分。因此,可以由接触元件防止焊盘和接触元件之间不希望有的额外材料桥。
在下文中,将解释封装和方法的其他示范性实施例。
在本申请的语境中,术语“封装”可以尤其表示具有至少一个外部电接触的至少一个至少部分被密封的电子芯片。
术语“电子芯片”可以尤其表示在其表面部分中具有至少一个集成电路元件(例如,二极管或晶体管)的半导体芯片。电子芯片可以是裸芯或者可以已经被封装或被密封。
在本申请的语境中,术语“密封体”可以尤其表示围绕(例如,密闭地围绕)电子芯片以及任选的载体的部分的基本电绝缘且优选导热的材料,以提供机械保护、电绝缘和对工作期间散热任选地提供贡献。这样的密封体可以是例如,模制化合物。在通过模制进行密封时,例如,可以进行注入模制或转移模制。
在本申请的语境中,术语“芯片载体”可以尤其表示一种导电结构,其充当一个或多个芯片的支撑,还可以有助于芯片和外围器件之间的电互连。换言之,载体可以实现机械支撑功能和电连接功能。
在本申请的语境中,术语“接触元件”可以尤其表示一体形成的导电主体,包括至少两种导电材料,其中一种构成第一接触结构,另一种构成第二接触结构。第一接触结构和第二接触结构可以在接触元件内部具有材料界面。第一接触结构可以被配置成接触芯片焊盘,第二接触结构可以被配置成在第一接触结构和第二接触结构的被暴露部分之间提供导电耦接。第一接触结构和第二接触结构可以形成双层或多层。
在实施例中,第一导电材料例如可以是纯金属、具有添加剂的金属或合金。至少一个焊盘可以特别也由第一导电材料制造。第二导电材料可以与第一导电材料不同,例如可以是纯金属、具有添加剂的金属或合金。第二金属可以与第一金属不同。
在实施例中,接触元件或键合脚可以是双金属或多金属结构,这可以允许获得更软的键合参数。还可以使用双金属或多金属接触元件,用于在芯片上安装(尤其是焊接)其他部件。
在实施例中,第一接触结构可以是仅由第一金属或第一导电材料形成的第一层。对应地,第二接触结构可以是第一层上的第二层,并仅由第二金属或第二导电材料形成。第一金属或第一导电材料可以由不同于第二金属或第二导电材料的材料制造。如上所述,封装可以包括芯片载体,其上安装有电子芯片。例如,这样的芯片载体可以包括两个相对主表面上都覆盖有相应金属层(尤其是活性金属钎焊(AMB)基板和/或直接铜键合(DCB)基板)的引线框架和/或陶瓷片(或由诸如氮化硅或氧化铝的另一种材料制造的另一电绝缘主体)。因此,可以建立用于安装芯片的适当安装基础。
在实施例中,芯片载体至少部分导电。在这样的实施例中,芯片载体也可以有助于电子芯片的电连接。例如,电子芯片面向芯片载体的主表面上的另一焊盘可以被导电耦接到芯片载体。
在另一实施例中,芯片载体为引线框架。这样的引线框架可以是片状金属结构,其可以被图案化,以便形成一个或多个用于安装封装的一个或多个电子芯片的安装部分,以及一个或多个用于在引线框架上安装电子芯片时将封装电连接到电子环境的引线部分。在实施例中,该引线框架可以是金属板(尤其是由铜制成),例如,可以通过压印或蚀刻对其进行构图。将芯片载体形成为引线框架是有成本效率且机械和电气方面有利的配置,其中至少一个电子芯片的低欧姆连接可以与引线框架的鲁棒支持能力组合。此外,引线框架可以有助于封装的导热,并可以消除在电子芯片工作期间由于引线框架的金属(尤其是铜)材料的高热导率产生的热量。引线框架可以包括例如铝和/或铜。
在实施例中,芯片载体至少具有表面部分,表面部分包括第三导电材料或由第三导电材料(例如,包括铜的合金)制造,其中第三导电材料尤其包括第二导电材料(例如,铜)或由其制造。在这样的实施例中,可以使用芯片载体的导电表面建立至一个或多个半导体芯片的电连接。在芯片载体也有电绝缘部分时,这样可以有助于电子芯片相对于电子外围器件的适当电隔离。
在实施例中,芯片载体与电子芯片的至少一个另一焊盘连接,其中至少一个焊盘形成于电子芯片的一个主表面上,而至少一个另一焊盘形成于电子芯片的相对另一主表面上。一些电子芯片在其两个相对主表面上都具有焊盘。一个示例就是具有垂直电流流动的电子芯片。例如,晶体管芯片可以在一个主表面上具有源极焊盘和栅极焊盘,在另一相对主表面上具有漏极焊盘。在这样的实施例中,可以使用一个或多个接触元件来接触电子芯片的焊盘的第一部分,而可以使用导电芯片载体来接触电子芯片的焊盘的至少一个其他部分。
在实施例中,封装包括至少一个从芯片载体突出的导电突起,尤其是突出到高达接触元件延伸的垂直高度(level)。例如,这样的导电突起可以是例如由铜制造的块、柱或支柱,经由接触元件在导电芯片载体和芯片的上主表面之间提供垂直连接。导电突起可以一直延伸到与接触元件相同的高度。这样就允许由诸如重新分布层(RDL)的平面结构实现接触元件和突起之间的连接。
在实施例中,至少一个导电突起穿过密封体延伸,从而相对于密封体被暴露。在这样的实施例中,导电突起可以由相同的密封体进行可靠的机械连接和电隔离,该密封体还用于密封芯片和接触元件的部分。得到的是紧凑且可靠的封装。
在实施例中,至少一个导电突起包括第四导电材料或由第四导电材料制造,其中第四导电材料尤其包括第二导电材料和第三导电材料之一或由其制造。在导电突起由接触元件的第二接触结构和/或载体也由其制成的第二和/或第三导电材料制成时,可以建立导电突起和延伸到密封体之外的接触元件之间的(例如,水平)连接。然后,还可以通过简单方式建立与载体的连接。
在实施例中,该方法包括在芯片载体上安装电子芯片。还可以向芯片载体附接导电突起。可以在密封突起的部分之前这样做。于是,也可以在密封流程期间部分地密封芯片载体和导电突起。
在实施例中,密封体包括电绝缘材料或由电绝缘材料构成。结果,密封体的材料可能有助于电绝缘芯片、接触元件、任选的芯片载体和任选的导电突起。
在实施例中,接触元件为双金属结构,尤其是铝-铜双金属结构。这样的双金属结构,即由其间具有材料界面的两种不同金属材料构成的接触元件制造简单且提供根据示范性实施例的封装有很高效率。例如,这样的双金属结构可以是双金属层或双金属板。在双金属结构的金属之一为铝时,可以接触半导体芯片的铝焊盘。在双金属结构的另一种金属是铜时,此类铝焊盘与铜引线框架或铜支柱或铜柱之间的适当连接也成为了可能。于是,可以获得紧凑的封装,该封装甚至在严酷的条件下对于损伤也是鲁棒的,并能够避免金属桥在芯片焊盘和电子环境之间建立接触。
在实施例中,该封装包括接触元件的表面部分上(尤其是其第二接触结构上)的导电连接结构,其表面部分相对于密封体被暴露。这样的导电连接结构可以与相对于密封体被暴露的第二接触结构由相同的材料制成。那么,可以形成接触元件和这样的导电连接结构之间的直接连接而不会在金属材料之间建立进一步的过渡,这种过渡可能会导致焊接之间的问题等等。
例如,该导电连接结构可以包括由重新分布结构(尤其是至少部分在密封体上和接触元件上的重新分布层)、夹具、引线键合和带状键合构成的组中的至少一种。
夹具可以是三维弯折板型的连接元件,其具有两个平面区段以连接到相应电子芯片的上主表面和芯片载体的上主表面,其中所述两个平面区段通过倾斜连接区段而互连。
作为此类夹具的替代,可以使用引线键合或带状键合,它们是柔性导电线或带形主体,一个端部连接到相应芯片的上主表面,另一个端部电连接到芯片载体。
重新分布结构(尤其是重新分布层)可以被表示为电介质基质之内的导电元件的多层结构,相对于导电连接表面而言,该多层结构在要经由重新分布结构,尤其是在其顶部与密封芯片连接的另一电子构件的小芯片尺寸和更大尺寸之间变换。
在实施例中,电子芯片是具有源极焊盘、漏极焊盘和栅极焊盘作为至少一个焊盘的晶体管芯片。具体而言,源极焊盘和栅极焊盘可以形成于电子芯片的同一主表面上,并且可以均与相应接触元件耦接。漏极焊盘可以形成于电子芯片的相对另一主表面上。这样的晶体管芯片可以是完成晶体管功能,尤其是场效应晶体管功能的芯片。具体而言,源极焊盘和栅极焊盘可以形成于此类晶体管芯片的一个主表面上,而漏极焊盘可以形成于该晶体管芯片的相对另一主表面上。例如,可以将这样的晶体管芯片用于半导体功率应用。
在实施例中,第一金属为铝。这样允许使用接触元件直接接触半导体芯片的铝焊盘。常规上,具有铝焊盘的半导体芯片与铜制成的另一导电连接结构(例如,引线框架)的组合涉及到由于不同金属材料导致的问题。可以通过被用作根据示范性实施例的金属-金属-结的双金属或多金属接触元件来克服这些问题。
在实施例中,第二金属为铜。在第二金属为铜时,简化了接触元件的被暴露部分与电外围器件接下来的连接,在很多情况下,电外围器件是基于铜形成的。对于铜引线框架、具有铜结构的印刷电路板、作为导电突起的铜柱这种情况保持成立。而且,引线键合、夹具和带状键合在很多情况下由铜制成。
在实施例中,第一接触结构的厚度不同于,尤其是小于第二接触结构的厚度。第一接触结构可以是由第一金属制成的层。第二接触结构可以是与第一接触层互连并由第二金属制成的层。这样的多层双金属或多金属接触元件紧凑且鲁棒,并且制造起来简单廉价。此外,这样的双层接触元件允许使用集成接触元件的各个层的各个厚度作为用于调节接触元件期望属性的设计参数。例如,连接到芯片焊盘的第一接触结构可以具有形成芯片焊盘的电连接而没有材料桥的功能。因此,在很多情况下,第一接触结构的相对小厚度就是足够的。与此相比,第二接触结构可以具有在接触元件的被暴露表面,在很多情况下为铜耦接表面处建立电连接的功能。不过,铜不仅便宜且适于加工,而且还具有非常高的热导率。因此从厚铜层提供第二接触结构能够允许在接触元件的相对两侧上避免金属间连接,并可以同时提供热学上高度适当的接触元件。
或者,第一接触结构和第二接触结构的厚度可以相同。
在实施例中,接触元件被配置为多金属堆叠,例如,其可以包括三个或更多个堆叠的接触结构。具体而言,接触元件可以额外包括第一接触结构和第二接触结构之间的第三接触结构。由于接触元件的第一和第二金属的功能是与芯片焊盘和封装的电子外围器件建立连接而没有材料桥,所以存在设计自由来在第一接触结构和第二接触结构之间夹置至少一个另外的第三接触结构(尤其是第三接触层)。然后可以根据特定应用的要求调整第三接触结构的材料特性。例如,可以由第三接触结构提供诸如耐腐蚀性、高电导率、高热导率等特性。可能第三接触结构的垂直尺度甚至比第一接触结构和第二接触结构的垂直尺度更大,因此接触元件的物理特性由第三接触结构支配。
具体而言,第三接触结构可以包括比第一接触结构和第二接触结构中的至少一个具有更高热导率、更高电导率和/或更低杨氏模量的材料或由所述材料构成。在配置材料具有极高热导率和/或电导率(例如,石墨烯)的第三接触结构时,可以进一步改善封装的热和/或电性能。在另一个有利的实施例中,第三接触结构可以由具有低杨氏模量,即非常软的材料制成,因此它可以充当应力缓冲,因此可以改善封装的可靠性。
在实施例中,接触元件是板形或条形的。具体而言,接触元件可以是多层(尤其是双层)多金属(尤其是双金属)薄片。可以由更大的片或带,例如通过冲压来容易地形成这样的薄片。此外,接触元件的板形几何形状优点在于,既可以与芯片焊盘接触,又可以通过鲁棒的方式与封装的电子外围器件接触。与灵敏得多的引线键合不同,可以在这样的板状接触元件上施加很大压力而没有损伤接触元件、电子芯片或封装的风险。
在实施例中,接触元件的厚度在10μm至1mm之间的范围内,尤其是20μm至500μm之间的范围内,更特别地,在50μm至200μm之间的范围内。例如,接触元件的厚度可以是100μm。然而,接触元件的长度和宽度可以大于其厚度。例如,接触元件的长度和宽度可以至少是其厚度的两倍,尤其是至少5倍。这提供了鲁棒的接触元件。
在实施例中,导电接触元件是条形元件(带状键合形状的元件),包括具有由第一导电材料制成的第一层的第一接触结构,以及具有由第二导电材料制成的第二层的第二接触结构。可以通过切割条形元件材料构成的连续条带来提供条形元件。因此,条形元件可以是金属带/条元件,其中一层尤其包括第一接触结构的第一层和第二接触结构的第二层。相应的层彼此堆叠并形成例如层结构。条形元件可以是柔性的,尤其是可塑性形变的元件。例如,条形元件的第一层可以由第一金属,例如铝制成,条形元件的第二层可以由第二金属,例如铜制成。因此,通过条形元件,实现了用于分别与焊盘和芯片,以及其他部件或导电结构连接的带件。条形元件可以被布置到焊盘上并可以通过例如带状键合技术电耦接到焊盘。因此,芯片上额外的Cu镀流程可以不是必要的。
在实施例中,条形元件包括第一接触结构和第二接触结构之间的至少一个第三接触结构,其中至少一个第三接触结构尤其包括比第一接触结构和第二接触结构中的至少一者具有更高热导率、更高电导率和/或更低杨氏模量的材料或由所述材料构成。
在实施例中,弯折条形元件,使得条形元件包括弯曲轮廓,尤其是U形、V形、Z形和W形的一种。
在实施例中,条形元件包括第一末端、第二末端以及第一末端和第二末端之间的中心部分,其中第一末端和第二末端被耦接到焊盘,中心部分与焊盘分隔开。
具体而言,可以通过在布置到相应焊盘之前弯折条形元件来形成条形元件的弯曲轮廓。具体而言,有条形元件的多种鲁棒轮廓可用。例如,可以将包括U形或V形轮廓的条形元件利用其第一末端和第二末端键合到焊盘,其中中心部分与焊盘间隔开并特别延伸出密封体,以便提供通往外部部件的连接,例如导电连接结构,例如重新分布层。或者,条形元件的Z形轮廓也是可弯折的,使得条形元件的第一末端被键合到焊盘,条形元件的第二末端与焊盘分隔开,并可以连接到另一外部部件。为了向焊盘或外部部件上提供多个,尤其是超过两个键合点,可以以W形状,例如曲流状形状的形式弯折。此外,可以通过密封体将弯折的条形元件完全嵌入,其中仅一部分,尤其是中心部分的一部分未被密封体覆盖。
在实施例中,该方法包括在密封之前将接触元件附接到至少一个焊盘。通过在密封之前已经将接触元件连接到芯片焊盘,半导体芯片是可适当触及的,并且处置接触元件的流程很简单。例如,可以通过焊接、熔接等建立连接。
在实施例中,该方法还包括(在向至少一个焊盘附接形成导电接触元件的条形元件之前)从包括第一层和第二层的连续条带,例如,双金属带或条带(例如,由铝和铜层制成)切割条形元件。
在实施例中,该方法还包括在将条形元件附接到至少一个焊盘之前弯折条形元件,使得条形元件的轮廓是弯曲的,尤其是弯曲的U形、弯曲的V形、弯曲的Z形和弯曲的W形。具体而言,可以在密封封装之前弯折相应的条形元件。例如,弯折的条形元件密封开放腔体。不过,在密封期间,密封剂在相应腔体之内流动,以完全围绕并由此嵌入相应的条形元件。因此,可以降低封装中出现不希望有的空气穴的风险,因为密封步骤是在将条形元件安装到相应焊盘之后进行的。
在另一实施例中,该方法包括在密封之后将接触元件附接到至少一个焊盘。因此,替代地还可以首先通过密封剂密封电子芯片,然后形成通过密封剂一直延伸到芯片焊盘的进出孔(access hole)。然后可以在密封之后将接触元件插入这样的进出孔中。这样的实施例优点在于接触元件的第二接触结构不必在密封之后单独暴露。
在实施例中,该方法包括在密封之后通过去除密封体的多余材料来暴露接触元件。这可以通过机械和/或化学方式完成。
在实施例中,该方法包括通过在密封期间阻止密封接触元件的被暴露部分来暴露接触元件。作为去除无意中覆盖接触元件的第二接触结构的表面的多余密封剂的补充或替代,可以采取措施防止暴露可能形成于表面上的密封剂材料。例如,这可以通过由模制工具的表面部分覆盖在密封之后应当保持被暴露的第二接触结构的表面来实现。例如,可以将已经预先安装了接触元件的电子芯片插入模制工具中,使接触元件的应当保持被暴露的表面直接接触模制工具的一部分。接下来插入的模制化合物的预成型件然后可以流入模制工具中,但将阻止其流到接触元件应当保持被暴露的表面上。此外或替代地,可以在密封期间通过具有保护箔的密封剂来覆盖接触元件应当保持不被覆盖的表面。在将这样的保护箔附着(例如,粘附)到接触元件应当保持被暴露的表面时,在密封之后去除箔将允许获得具有被暴露表面的接触元件。
因此,所述方法可以包括通过由以下操作构成的组中的至少一项相对于密封剂暴露第二接触结构:
-在密封期间利用保护箔覆盖第二接触结构的至少一部分,并在封装之后去除保护箔;
-在密封期间利用密封工具的表面接触第二接触结构的至少一部分,防止密封剂覆盖被接触部分;
-在密封之后,清洁,尤其是通过机械和/或化学方式清洁第二接触结构的至少一部分,由此从该部分去除密封剂材料。
其他方法当然也是可能的。
在实施例中,该方法包括精整(refining)第二接触结构的被暴露表面,尤其是通过在第二接触结构上形成功能层。因此,可以对第二接触结构的被暴露表面进行后处理,以便改善其期望的特性,以完成适当封装。精整其表面可以包括例如添加银层,以改善可焊接性。还可以涂覆镍-金保护层。这样的层保护接触元件并促成其充当导电连接的能力。精整接触元件的被暴露表面还可以包括清洁流程,例如,机械抛光和/或化学去氧流程。进一步替代地,可以在被暴露的第二接触结构上形成薄的氧化铝层,作为防止接触元件氧化的保护。例如,可以执行电镀流程,以在第二接触结构的被暴露表面上形成额外材料。这可以通过例如电沉积流程来完成。更一般地,对被暴露表面进行这样的精整可以改善接触元件的可焊接性、可键合性或可电镀性。而且,化学镀也是可能的选项。
在实施例中,至少一个电子芯片包括由控制器电路、驱动电路和功率半导体电路构成的组中的至少一个。所有这些电路都可以集成到一个半导体芯片中,或独立集成在不同芯片中。例如,可以通过芯片实现对应的功率半导体应用,其中这样的功率半导体芯片的集成电路元件可以包括至少一个晶体管(尤其是MOSFET、金属氧化物半导体场效应晶体管)、至少一个二极管等。具体而言,可以制造完成半桥功能、全桥功能等的电路。
在实施例中,密封体包括模制化合物。因此,密封体可以包括模制件,具体而言包括塑料模制件。例如,可以通过在上模制工具和下模制工具之间放置一个或多个主体,并在其中注入液体模制材料,来提供相应密封主体(尤其是带有载体的芯片)。在模制材料固化之后,完成了密封体的形成。如果需要,可以利用颗粒填充模制件,改善其性质,例如其散热性质。
在其他示范性实施例中,密封体也可以是层压部件或浇注部件。
作为用于半导体芯片的衬底或晶圆,可以使用半导体衬底,即,硅衬底。或者,可以提供氧化硅或另一种绝缘体衬底。还可以实施锗衬底或III-V半导体材料。例如,可以在GaN或SiC技术中实现示范性实施例。
说明性地讲,接触元件可以形成延伸出密封体的特别稳定的焊盘。
本发明还提供了以下方面:
根据一方面,提供了一种封装,该封装包括具有至少一个焊盘的电子芯片、至少部分地密封电子芯片的密封体,以及从至少一个焊盘延伸穿过密封体以便相对于密封体被暴露的导电接触元件,其中导电接触元件包括至少一个焊盘上由第一导电材料制成的第一接触结构,并包括由第二导电材料制成且相对于密封体被暴露的第二接触结构。
根据一方面,提供了一种封装,该封装包括至少部分导电的芯片载体、安装于芯片载体上的电子芯片,其中该电子芯片设置有具有包括第一金属的外表面的焊盘、从焊盘延伸的导电接触元件,以及至少部分密封接触元件和电子芯片的密封体,其中该接触元件包括至少一个焊盘上且包括第一金属的第一接触结构,并包括具有未被密封体覆盖的被暴露表面并包括第二金属的第二接触结构。
根据一方面,提供了一种制造封装的方法,其中该方法包括通过密封体至少部分地密封具有至少一个焊盘的电子芯片,设置从至少一个焊盘延伸穿过密封体以相对于密封体被暴露的导电接触元件,以及配置导电接触元件以包括在至少一个焊盘上由第一导电材料制成的第一接触结构,并包括由第二导电材料制成且相对于密封体被暴露的第二接触结构。
结合附图考虑以下描述和附属权利要求,本发明的以上和其他目的、特征和优点将变得显而易见,在附图中,由类似附图标记表示类似部分或元件
附图说明
附图被包括在说明书中以提供对本发明示范性实施例的进一步理解并构成说明书的一部分,其示出了本发明的示范性实施例。
在附图中:
图1示出了根据示范性实施例的封装的截面图。
图2示出了根据另一示范性实施例的封装的截面图。
图3示出了根据示范性实施例的制造封装的方法流程图。
图4示出了根据又一示范性实施例的封装的截面图。
图5示出了根据又一示范性实施例的封装的截面图。
图6到图11示出了根据示范性实施例,在制造图4或图5所示封装期间获得的结构的截面图。
图12示出了根据又一示范性实施例的封装的截面图。
图13示出了根据又一示范性实施例的封装的截面图。
图14示出了根据示范性实施例的封装的接触元件的截面图。
图15示出了根据另一示范性实施例的封装的接触元件的截面图。
图16示出了根据又一示范性实施例的封装的截面图。
图17示出了根据示范性实施例,用于形成条形元件的连续(endless)条带的示意图。
图18示出了根据示范性实施例的弯折条形元件的示意图。
具体实施方式
附图中的图示为示意性的且不成比例。
在参考附图更详细地描述示范性实施例之前,将总结一些一般性的考虑事项,基于它们将发展出示范性实施例。
根据示范性实施例,提供了一种形式为双金属或多金属键合脚的接触元件作为超薄封装的互连。可以通过高度紧凑的方式并利用很低人工,使用现有芯片技术而无需专门调节前侧金属化部来形成这样的封装。这可以通过以接触结构的形式提供简单的双金属或多金属互连来完成。
通过使用激光钻孔、通孔和重新分布技术直接接触芯片,建立了芯片嵌入变体,实现了增强的电气和热性能。不过,常规方式的缺点在于通孔连接需要具有芯片的适当前侧金属化部,尤其是铜焊盘的芯片技术。另外,铜通孔的电镀可能涉及额外的成本。
为了克服尤其是这些缺点,示范性实施例以上述接触元件的形式提供了一种用于芯片连接的(例如,铝-铜)多金属键合脚。通过采取这种措施,可以通过密封,尤其是使用模制化合物或层合物来形成薄封装。随后,可以减薄密封剂材料,直到键合脚的铜侧延伸超过(例如,模制件型或层合物型)密封体。随后,可以形成另一导电连接结构(例如,重新分布结构)以与接触元件的暴露表面电耦接。例如,可以在密封体上以及第二接触结构的被暴露表面上执行铜电镀。后者可以由与被密封的半导体芯片焊盘直接连接的接触元件的第一接触结构不同的金属制成。形成诸如重新分布结构的导电连接结构还可能涉及在接触元件延伸出密封体的位置层压铜箔与对应的凹陷。随后,可以执行铜电镀流程。可以在键合脚上直接形成导电连接结构,例如重新分布结构。换言之,键合脚或接触元件可以充当封装焊盘。可以通过切割或冲压双层片或带的一部分来形成这样的接触元件,例如,该片或带具有与铜层一体形成的铝层。
所提到的实施例具有如下优点:也可以实施没有用于通孔连接的适当前侧金属化部的芯片技术。因此不必在芯片上应用铜电镀工艺,该工艺常规涉及大量的人力。
根据示范性实施例,可以提供接触元件形式的双金属互连用于在其一侧接触芯片焊盘。其相对的另一侧可以相对于密封体被暴露并可以用于使被密封的电子芯片与封装的电子环境接触。在实施例中,可以执行印刷电路板工艺用于封装的进一步处理。
根据示范性实施例,可以使用由不同金属材料构成,尤其是实现为双金属双层结构的键合脚。对应于层之一的一种金属例如可以是铝,可以使用标准工艺将其与铝芯片焊盘连接。另一种金属和另一层可以是例如铜,其可以充当另一重新分布结构的基础或作为焊盘,例如,以连接到另一铜结构(例如,铜柱、印刷电路板或引线框架)。
在实施例中,可以通过超声波键合将键合脚或接触元件与芯片焊盘连接。可以利用层合物、模制件或塑料来密封键合的芯片。
可以通过清洁流程来执行接触元件表面的暴露,以精整或清洁暴露表面。因此可以使用接触元件的被暴露金属表面作为焊盘,尤其是引线键合焊盘。接触元件的这种焊盘状暴露表面也可以用于芯片嵌入工艺。还可以精整接触元件的焊盘型暴露表面用于引线结合。另外,可以进一步在接触元件上精整焊盘型暴露表面,以用于提供阻焊剂或预焊接。
也可以进行通过直接铜电镀或与铜箔层压以及铜电镀进一步形成重新分布结构。然后可以基于所述原理制造模制和/或层压封装。
在极小的容器中,示范性实施例可以提供具有诸如芯片的半导体器件的半导体封装。作为密封体的绝缘材料可以覆盖半导体芯片的至少一个表面。半导体封装还可以包括接触元件。接触元件可以布置于半导体芯片的表面。此外,接触元件可以在绝缘材料中形成通孔。接触元件可以具有至少两个不同的金属层。
图1示出了根据示范性实施例的封装100的截面图。
所示出的封装100包括电子芯片102,例如半导体芯片。在所示的实施例中,在电子芯片102的上主表面上为电子芯片102设置了例如铝的焊盘104。密封体106,例如模制化合物部分地密封了电子芯片102以及导电接触元件108。导电接触元件108在此被实现为双金属双层堆叠,从焊盘104延伸(并连接到其上)。导电接触元件108垂直延伸穿过密封体106,使得接触元件108相对于密封体106被暴露。更具体而言,接触元件108包括焊盘104上由第一导电材料,例如铝制成的第一接触结构110。接触元件108还包括由第二导电材料,例如铜制成的第二接触结构112。如图1所示,第二接触结构112的上表面相对于密封体106暴露,使得可以从封装100外部触及到它。
根据图1的封装100具有如下优点:接触元件108的第二接触结构112的被暴露表面131可以充当与芯片焊盘104的金属不同的另一种材料的焊盘。因此,被暴露表面131可以与第二金属制成的另一电子构件直接连接而没有不希望的金属间桥,第二接触结构112也是由第二金属制成的。同时,芯片焊盘104的金属和接触元件108的第一接触结构110的金属可以相同,从而在这个区域中也可以没有不希望有的金属间桥。
图2示出了根据另一示范性实施例的封装100的截面图。
根据图2的封装100包括导电芯片载体114,例如铜引线框架。电子芯片102,例如功率半导体芯片安装(例如,焊接)于芯片载体114上。电子芯片102的底部主表面124附接到芯片载体114。电子芯片102设置有具有外表面的焊盘104,该外表面包括第一金属,例如铝。导电接触元件108从焊盘104向上延伸,并通过例如焊接而连接到焊盘104。密封体106(例如可以通过浇注形成)仅部分密封接触元件108和电子芯片102。如图所示,接触元件108包括直接在焊盘104上形成第一接触结构110的第一金属层(例如,铝层)。此外,接触元件108包括形成第二接触结构112的第二金属层(例如,铜层)。如图所示,第二接触结构112具有与密封体106的上表面对准的被暴露上表面。被暴露上表面不被密封体106覆盖。导电接触结构118在此被实现为夹具(例如,由铜构成),在第二接触结构112的被暴露表面和芯片载体114之间提供连接。
如图所示,夹具118(例如由铜制成)可以简单地与芯片载体114(尤其是也由铜制成的引线框架)并与也可以由铜制成的第二接触结构112的被暴露表面131连接。与此相比,芯片焊盘104和第一接触结构110都可以由铝制成。因此可以建立从铝到铜的材料过渡而没有不希望有的金属间桥。这可以由接触元件或键合脚的双金属特性实现。
图3示出了根据示范性实施例的制造封装100的方法300的流程图。
如框310所示,该方法包括通过密封体106至少部分地密封具有至少一个焊盘104的电子芯片102。如框320所示,该方法还包括提供导电接触元件108,该导电接触元件从至少一个焊盘104延伸穿过密封体106以便相对于密封体106被暴露。此外,框330指出,该方法可以额外包括配置接触元件108以包括在至少一个焊盘104上由第一导电材料制成的第一接触结构110,并包括由第二导电材料制成且相对于密封体106被暴露的第二接触结构112。
当然,可以向参考图3描述的方法添加其他流程。
图4示出了根据又一示范性实施例的封装100的截面图。
图4的封装100包括导电芯片载体114(例如,可以由铜形成的引线框架),电子芯片102安装于其上。此外,图4中所示的封装100包括导电突起116(例如,铜块),该导电突起从芯片载体114突起直到高达接触元件108(如参考图1或图2所述)延伸的垂直高度。突起116延伸穿过密封体106并相对于密封体106在上侧被暴露。密封体106可以由电介质模制化合物形成。接触元件108被形成为双层双金属结构,即,板形铝-铜双金属双层结构。例如,接触元件108的垂直厚度在50μm至200微米之间范围中。接触元件108在水平平面中的长度和宽度可以大于垂直厚度。
在图4的实施例中,电子芯片102的上主表面上设置了两个芯片焊盘104,它们直接连接(例如,通过焊接或熔接)到接触元件108的第一接触结构110。例如,芯片焊盘104和第一接触结构110都可以由铝制成。不过,两个接触元件108的被暴露第二接触结构112相对于密封体106暴露,但其顶表面与密封体106的顶表面对准。因此,第二接触结构112可以充当由铜制成的焊盘状结构,其实现与被密封的电子芯片102和铝焊盘104的间接接触。导电突起116的被暴露上表面133也与接触元件108以及密封体106的上主表面处在相同垂直高度。因此,形成了平面表面,允许导电结构116、112之间的平面连接。下文参考图5更详细地描述这种情况。芯片载体114(例如,铜引线框架)以及突起116(例如,铜块)可以与接触元件108的第二接触结构112由相同材料(例如,铜)制成,并因此可以与其连接而不会形成不希望有的金属间桥。
图5示出了根据又一示范性实施例的封装100的截面图。下面将描述与图4的实施例不同之处。
根据图5,芯片载体114与电子芯片102的另一焊盘122在其底部主表面124上连接。在图示的实施例中,在电子芯片102的上主表面120上形成两个焊盘104(利用附图标记104a、104b表示),在电子芯片102的相对底部主表面124上形成一个另一焊盘122。图5的封装100还包括接触元件108的被暴露表面部分、突起116的被暴露表面部分以及密封体106的上主表面上的平面导电连接结构118。在图示的实施例中,导电连接结构118被配置成密封体106上、突起116上以及接触元件108上的重新分布层。
由于根据图5的封装100的电子芯片102是晶体管芯片,所以其具有源极焊盘104a、漏极焊盘122和栅极焊盘104b。源极焊盘104a和栅极焊盘104b形成于电子芯片102的同一上主表面120上,并且均与接触元件108的相应一个的第一接触结构110耦接。与此相比,漏极焊盘122形成于电子芯片102的相对下主表面124上,与芯片载体114直接导电连接。
如图5的实施例中所示,可以通过还在电子芯片102的下主表面上提供另一焊盘122而进一步发展图4的实施例。这个另一焊盘122可以经由导电芯片载体114、导电突起116和重新分布层118(通过在图4中所示的封装100的顶主表面上构图一个或多个铜层形成后者)与半导体芯片102的上主表面上的芯片焊盘104a、104b之一电连接。说明性地讲,重新分布型的导电连接结构118可以在芯片界的小尺度和安装基底(例如,印刷电路板)界的更大尺度之间转换,图5的封装100的上主表面可以连接到该安装基底(未示出)。
如图4的实施例中那样,除了接触元件108的内部之外,未形成不希望的金属间桥,接触元件108可以是铜和铝的叠层。不过,可以用很低人力将这样的叠层提供为预先形成的一体多层结构。
因此,图5的实施例对应于具有被密封的晶体管芯片102的封装100,该晶体管芯片102在其下主表面124上具有另一焊盘122作为漏极焊盘,在其上主表面120上具有栅极焊盘104b和源极焊盘104a。
图6到图11示出了根据示范性实施例,在制造图4或图5所示封装100期间获得的结构的截面图。
被用作起点并如图6中所示的芯片载体114是结构化的引线框架。
参考图7,该方法包括在芯片载体114上安装电子芯片102以及将导电突起116附接到芯片载体114。可以通过将裸芯,即裸露的半导体芯片102附接在图6中示为芯片载体114的示例的结构化引线框架的安装区域上,从而获得图7中所示的结构。
此外,可以附接铜块作为芯片载体114的安装表面上垂直延伸超过电子芯片102的上主表面的垂直导电突起116。
或者,还可以与芯片载体114一体地形成导电突起116,即,无需将突起116附接到载体114上。例如,可以蚀刻掉芯片载体114的原始预成型件的材料,从而选择性地去除突起116之间的区域,且突起116保持与芯片载体114的板形部分一体连接。
在又一示范性实施例中,还可以在下文参考图9所述的密封流程之后形成导电突起116。在这样的实施例中,可以在密封体106中蚀刻凹陷。接下来,可以向凹陷中插入形成突起116的材料。例如,焊球可以被插入这样的凹陷中,可以被熔化并随后固化,并由此可以被转换成突起116。
参考图8,提供导电接触元件108,每个导电接触元件都从焊盘104的相应一个延伸。接触元件108均具备由第一导电材料制成且在焊盘104上连接的第一接触结构110,并设置有由第二导电材料制成且具有上自由端的第二接触结构112。如图所示,接触元件108被附接到焊盘104并与之连接。
因此,为了获得图8中所示的结构,可以将铝-铜键合脚作为接触元件108附接到电子芯片102的上主表面上的芯片焊盘104。可以将接触元件108的上主表面与导电突起116的上主表面对准。
参考图9,载体114、电子芯片102、突起116和芯片载体114被模制型密封体106部分密封。接触元件108穿过密封体106延伸,但在第二接触结构112的平坦平面水平顶表面处相对于密封体106被暴露。突起116的平坦平面水平顶表面也相对于密封体106被暴露。
如果需要或要求,可以通过在密封之后从其顶表面去除密封体106的多余材料,来处理接触元件108。例如,可以在密封之后通过机械和/或化学方式清洁第二接触结构112,由此从第二接触结构112的顶部去除密封体106的材料。
然而,还可以通过阻止在密封流程期间密封接触元件108的顶部来确保暴露接触元件108。例如,可以通过在密封期间利用保护箔(未示出)覆盖第二接触结构112的顶部并在密封之后去除保护箔,来确保相对于密封体106暴露第二接触结构112。此外或替代地,在密封流程期间可以使第二接触结构112的顶部与密封工具(未示出)的表面接触,以防止密封体106的材料覆盖被接触的部分。
于是,可以通过密封图8中所示的结构,尤其是通过模制,来获得图9中所示的结构。在这一密封流程期间,可以阻止接触元件108的上主表面以及突起116的上主表面被密封和/或可以在密封之后使其从密封体106暴露。例如,可以通过机械处理(喷水、抛光)和/或化学方式(例如,通过蚀刻掉多余的密封体材料)来实现这一目的。
可以通过在图9所示结构的平面上主表面上形成重新分布层(作为导电连接结构118的示例)来获得图9所示的结构。这可能涉及附着并图案化铜箔,通过电镀来沉积铜或其他导电材料,执行构图流程(例如,光刻构图)等。还可能导电连接结构118包括电绝缘层(未示出),其中可以嵌入导电连接结构118的导电元件。
如图11中所示,任选地可以在图10中所示的结构的上主表面上附接另一构件135,例如,诸如陶瓷电容器或欧姆电阻器的无源部件。
如图11中所示,可以批量水平形成多个封装100,如参考图6到图11所述。在同时制造多个封装100的这种常见制造工艺之后,可以对图11中所示的结构进行单个化,以便获得图4或图5中所示的多个封装。
图12示出了根据又一示范性实施例的封装的截面图。
图12的实施例示出了封装100,其中在两个相对主表面上具有焊盘104a、104b、122的电子芯片102,连同上述接触元件108一起,被密封在密封体106中。接触元件108的第二接触结构112相对于密封体106被暴露并延伸到与密封体106相同的垂直高度。之后,可以执行精整流程,用于精整接触元件108的被暴露表面。对应于图12的封装100的制造方法于是可以包括例如通过在第二接触结构112上形成功能层132而精整第二接触结构112的被暴露表面。
此外,可以在功能层132和芯片载体114的导电表面,例如,其铜表面之间连接作为导电连接结构118的另一示例的引线键合。于是,可以使用铜引线键合连接作为芯片载体114的铜引线框架与第二接触结构112的被暴露铜表面,尽管半导体芯片102的顶侧上的芯片焊盘104a、104b可以由另一种材料,例如铝制成。这种铝材料可以连接到第一接触结构110,该第一接触结构也可以由铝制成。
图13示出了根据又一示范性实施例的封装100的截面图,其中,两个半导体芯片102以半桥配置连接并嵌入同一密封体106中。可以将两个接触元件108用于经由夹具连接两个半导体芯片102的上方焊盘104a、122,夹具是导电连接结构118的另一示例。在图示的示例中,夹具可以延伸到附接到两个电子芯片102的接触元件108的相应第二接触结构112中形成的凹陷139中。同样,尽管所示半导体芯片102的所接触焊盘104a、122可以由铝制成,但可以使用例如铜夹具。
图14示出了根据示范性实施例的封装100的接触元件108的截面图。图14的实施例示出了根据示范性实施例的双金属双层接触元件108。
在图14的接触元件108中,第一接触结构110的厚度d小于第二接触结构112的厚度D。如图所示,层型第一接触结构110的厚度d可以比层型第二接触结构112的厚度D更薄。例如,厚度为d且形成第一接触结构110的薄铝层于是可以与形成第二接触结构112的更厚(厚度D>d)铜层一体连接。通过采取这一措施,可以将铜的更低成本、更好的可加工性以及高热导率与薄铝层组合,该铝层充当通往半导体芯片的铝焊盘的连接,而不会形成金属间桥。
图15示出了根据另一示范性实施例的封装100的接触元件108的截面图。
在本实施例中,接触元件108包括第三接触结构111作为夹置于层型第一接触结构110和层型第二接触结构112之间的额外层。于是,图15的实施例由三个互连的层(参见附图标记110、111、112)构成。最下层形成第一接触结构110,最上层形成第二接触结构112,第三接触结构111作为第三层夹置于其间。例如,第一接触结构110可以由铝制成,第二接触结构112可以由铜制成,第三接触结构111可以由另一种金属材料制成,该另一种金属材料可以由电路设计者基于特定应用的要求来选择。
图16示出了根据又一示范性实施例的封装100的截面图。
所示出的封装100包括电子芯片102,例如半导体芯片。在电子芯片102的上主表面上为电子芯片102设置了例如铝的焊盘104。密封体106,例如模制化合物部分地密封了电子芯片102以及导电接触元件108。在图示的实施例中,导电接触元件108是条形元件(带状键合形状的元件),包括具有由第一导电材料制成的第一层的第一接触结构110,以及具有由第二导电材料制成的第二层的第二接触结构112。
例如,条形元件的第一层可以由第一金属,例如铝制成,条形元件的第二层可以由第二金属,例如铜制成。因此,通过条形元件,实现了用于分别与焊盘和芯片,以及其他部件或导电结构连接的带件。条形元件与焊盘104电耦接并通过例如带状键合技术电耦接到焊盘104。
条形元件包括第一末端1601、第二末端1602以及布置于第一末端1601和第二末端1602之间的中心部分1603。在图16中所示的示范性实施例中,第一末端1601和第二末端1602电耦接到相应焊盘104,中心部分1603与相应焊盘104间隔开。在图16中所示的示范性实施例中,条形元件具有U形。外层形成第二接触结构112,第二接触结构在中心部分1603的区域中连接到另一部件,例如导电连接结构118,例如重新分布结构或引线框架。条形元件的内层形成第一接触结构110,第一接触结构以其末端1601、1602连接到相应焊盘104。沿着焊盘104,第一末端1601和第二末端1602彼此间隔开。在相应的末端1601、1602处,第一接触结构110的材料部分地围绕并覆盖第二接触结构112的相应端面,使得第一接触结构110的材料接触半导体芯片102的相应焊盘104并可以键合到其上。因此,条形元件垂直延伸穿过密封体106,使得条形元件相对于密封体106被暴露。更具体而言,条形元件包括焊盘104上由第一导电材料,例如铝制成的第一接触结构110的层。条形元件还包括由第二导电材料,例如铜制成的第二接触结构112的层。
此外,在图16的示范性实施例中,示出了另一电子芯片1604,包括前侧金属化部1605和后侧金属化部1606。后侧金属化部1606可以直接电连接到电子芯片102。相应的导电元件108被连接到前侧金属化部1605,使得根据所主张权利的方案,前侧金属化1605部可以充当相应焊盘104。将前侧金属化部1605耦接到导电连接结构118的导电接触元件108也可以是U形的,并包括具有由第一导电材料制成的第一层的第一接触结构110,以及具有由第二导电材料制成的第二层的第二接触结构112。芯片1603可以是IGBT(绝缘栅双极型晶体管)、MOSFET(金属氧化物半导体场效应晶体管)、二极管或集成电路IC。
图17示出了根据示范性实施例,用于形成条形元件的连续条带1701的示意图。
通过切割条形元件材料构成的连续条带1701来提供条形元件。因此,条形元件可以是金属带/条元件,其中一层尤其包括第一接触结构的第一层和第二接触结构的第二层。条形元件可以是柔性的,尤其是可塑性形变的元件。
图18示出了根据示范性实施例的弯折条形元件的示意图。条形元件在图18中被示为弯折的,使得条形元件形成弯曲轮廓,尤其是U形或V形。具体而言,可以通过在布置到相应焊盘之前弯折条形元件来形成条形元件的弯曲轮廓。具体而言,有条形元件的多种鲁棒轮廓可用。例如,可以将包括U形或V形轮廓的条形元件利用其第一末端1601和第二末端1602键合到焊盘104,其中中心部分1603与焊盘104间隔开并特别延伸出密封体,以便提供通往诸如部件载体的外部部件的连接。
从图18中可以看出,末端1601、1602被折叠,使得第一接触结构110的材料部分地围绕并覆盖第二接触结构112的相应端面,使得第一接触结构110的材料接触半导体芯片102的相应焊盘104并可以键合到其上。
此外,可以由密封体106完全嵌入弯折的条形元件。在被键合到焊盘104之后,形成了由末端部分1601、1602和中心部分1603包围的条形元件内腔。不过,在密封期间,密封剂在相应腔体之内流动,以围绕并由此嵌入相应的条形元件。因此,可以降低封装中出现不希望有的空气穴的风险,因为密封步骤是在将条形元件安装到相应焊盘之后进行的。
应当提到的是,尽管在以上实施例中提到了铜和铝作为示例,但可以使用金属或合金的任何其他组合来构成接触元件108。这可能取决于特定应用的特别之处。
应当指出,术语“包括”不排除其他元件或特征,“一”或“一个”不排除多个。而且,结合不同实施例描述的元件可以被组合。还应该指出的是,附图标记不应被理解为限制权利要求的范围。此外,本申请的范围并非意在限于说明书中描述的过程、机器、制造以及物质组成、手段、方法和步骤的特定实施例。因此,所附权利要求意在在其范围之内包括这样的过程、机器、制造、物质组成、手段、方法或步骤。
Claims (39)
1.一种封装(100),包括:
·具有至少一个焊盘(104)的电子芯片(102);
·至少部分地密封所述电子芯片(102)的密封体(106);
·导电接触元件(108),所述导电接触元件从所述至少一个焊盘(104)延伸穿过所述密封体(106)以相对于所述密封体(106)被暴露;
·其中所述导电接触元件(108)包括在所述至少一个焊盘(104)上由第一导电材料制成的第一接触结构(110),并包括由第二导电材料制成且相对于所述密封体(106)被暴露的第二接触结构(112),其中,所述第一接触结构完全设置在所述密封体内,并且所述第二接触结构至少部分地设置在所述密封体内;并且
·其中所述至少一个焊盘(104)中的至少一个至少具有包括所述第一导电材料或由所述第一导电材料制成的表面部分。
2.根据权利要求1所述的封装(100),包括芯片载体(114),所述电子芯片(102)安装于所述芯片载体上。
3.根据权利要求2所述的封装(100),其中所述芯片载体(114)至少具有包括第三导电材料或由所述第三导电材料制成的表面部分。
4.根据权利要求3所述的封装(100),其中所述第三导电材料包括所述第二导电材料或由所述第二导电材料制成。
5.根据权利要求2、3或4所述的封装(100),其中所述芯片载体(114)与所述电子芯片(102)的至少一个另一焊盘(122)连接,其中所述至少一个焊盘(104)形成于所述电子芯片(102)的主表面(120)上,并且所述至少一个另一焊盘(122)形成于所述电子芯片(102)的相对另一主表面(124)上。
6.根据权利要求3至4中的任一项所述的封装(100),包括至少一个导电突起(116),所述至少一个导电突起(116)从所述芯片载体(114)突出。
7.根据权利要求6所述的封装(100),所述至少一个导电突起(116)突出到高达所述接触元件(108)延伸的垂直高度。
8.根据权利要求6所述的封装(100),其中所述至少一个导电突起(116)包括第四导电材料或由所述第四导电材料制成。
9.根据权利要求8所述的封装(100),其中所述第四导电材料包括所述第二导电材料和所述第三导电材料之一或由所述第二导电材料和所述第三导电材料之一制成。
10.根据权利要求1至4中的任一项所述的封装(100),其中所述导电接触元件(108)是层堆叠体,所述层堆叠体包括作为所述第一接触结构(110)的由所述第一导电材料制成的至少第一层,以及作为所述第二接触结构(112)的由所述第二导电材料制成的至少第二层。
11.根据权利要求1至4中的任一项所述的封装(100),包括所述第二接触结构(112)的表面部分上的导电连接结构(118),所述表面部分相对于所述密封体(106)被暴露。
12.根据权利要求11所述的封装(100),其中所述导电连接结构(118)包括由重新分布结构、夹具、引线键合和带状键合构成的组中的至少一种。
13.根据权利要求12所述的封装(100),其中所述重新分布结构是至少部分在所述密封体(106)上和所述接触元件(108)上的重新分布层。
14.根据权利要求1至4中的任一项所述的封装(100),其中所述导电接触元件(108)是条形元件,所述条形元件包括具有由所述第一导电材料制成的第一层的所述第一接触结构(110)以及具有由所述第二导电材料制成的第二层的所述第二接触结构(112)。
15.根据权利要求14所述的封装(100),其中所述条形元件包括所述第一接触结构(110)和所述第二接触结构(112)之间的至少一个第三接触结构(111)。
16.根据权利要求15所述的封装(100),其中所述至少一个第三接触结构(111)包括比所述第一接触结构(110)和所述第二接触结构(112)中的至少一者具有更高热导率、更高电导率和/或更低杨氏模量的材料或由所述材料构成。
17.根据权利要求15所述的封装(100),其中所述条形元件被弯折成使得所述条形元件包括弯曲轮廓。
18.根据权利要求17所述的封装(100),其中所述弯曲轮廓是U形、V形、Z形和W形中的一种。
19.根据权利要求17所述的封装(100),其中所述条形元件包括第一末端(1601)、第二末端(1602)以及布置于所述第一末端(1601)和所述第二末端(1602)之间的中心部分(1603),其中所述第一末端(1601)和所述第二末端(1602)耦接到所述焊盘(104),并且所述中心部分(1603)与所述焊盘(104)间隔开。
20.一种封装(100),包括:
·至少部分导电的芯片载体(114);
·安装于所述芯片载体(114)上的电子芯片(102),其中所述电子芯片(102)设置有焊盘(104),所述焊盘具有包括第一金属的外表面;
·从所述焊盘(104)延伸的导电接触元件(108);
·至少部分地密封所述接触元件(108)和所述电子芯片(102)的密封体(106);
·其中所述接触元件(108)包括:
o在所述至少一个焊盘(104)上并且完全设置在所述密封体的上表面下方的第一接触结构(110),以及
o至少部分地设置在所述密封体的所述上表面下方并且包括未被所述密封体(106)覆盖的被暴露表面的第二接触结构(112),
o所述第一接触结构(110)包括所述第一金属,并且所述第二接触结构(112)包括第二金属。
21.根据权利要求20所述的封装(100),其中所述第一接触结构(110)的厚度(d)不同于所述第二接触结构(112)的厚度(D)。
22.根据权利要求20所述的封装(100),其中所述第一接触结构(110)的厚度(d)小于所述第二接触结构(112)的厚度(D)。
23.根据权利要求20、21或22所述的封装(100),其中所述导电接触元件(108)包括所述第一接触结构(110)和所述第二接触结构(112)之间的至少一个第三接触结构(111)。
24.根据权利要求23所述的封装(100),其中所述至少一个第三接触结构(111)包括比所述第一接触结构(110)和所述第二接触结构(112)中的至少一者具有更高热导率、更高电导率和/或更低杨氏模量的材料或由所述材料构成。
25.根据权利要求20至22中的任一项所述的封装(100),其中所述导电接触元件(108)是板形或条形的。
26.一种制造封装(100)的方法,其中所述方法包括:
·通过密封体(106)至少部分地密封具有至少一个焊盘(104)的电子芯片(102);
·设置导电接触元件(108),所述导电接触元件从所述至少一个焊盘(104)延伸穿过所述密封体(106)以相对于所述密封体(106)被暴露;
·配置所述导电接触元件(108)以包括:在所述至少一个焊盘(104)上由第一导电材料制成的第一接触结构(110),所述第一接触结构(110)完全设置在所述密封体的上表面下方;并包括:由第二导电材料制成的第二接触结构(112),所述第二接触结构(112)至少部分地设置在所述密封体的所述上表面下方并且相对于所述密封体(106)被暴露,
·其中所述至少一个焊盘(104)中的至少一个至少具有包括所述第一导电材料或由所述第一导电材料制成的表面部分。
27.根据权利要求26所述的方法,其中所述方法包括在所述密封之前将所述导电接触元件(108)附接到所述至少一个焊盘(104)。
28.根据权利要求27所述的方法,其中所述导电接触元件(108)是条形元件,所述条形元件包括具有由所述第一导电材料制成的第一层的所述第一接触结构(110)以及具有由所述第二导电材料制成的第二层的所述第二接触结构(112)。
29.根据权利要求28所述的方法,还包括在将所述条形元件附接到所述至少一个焊盘(104)之前,从包括所述第一层和所述第二层的连续条带(1701)切割所述条形元件。
30.根据权利要求28或29所述的方法,还包括:在将所述条形元件附接到所述至少一个焊盘(104)之前,弯折所述条形元件,使得所述条形元件的轮廓是弯曲的。
31.根据权利要求30所述的方法,其中所述条形元件的轮廓是弯曲的U形、弯曲的V形、弯曲的Z形和弯曲的W形。
32.根据权利要求27至29中的任一项所述的方法,包括以下特征之一:
·其中所述方法包括通过在密封之后去除所述密封体(106)的多余材料来暴露所述导电接触元件(108);
·其中所述方法包括通过在密封期间防止密封所述接触元件(108)的被暴露部分来暴露所述接触元件(108)。
33.根据权利要求26至29中的任一项所述的方法,其中所述方法包括在芯片载体(114)上安装所述电子芯片(102)。
34.根据权利要求33所述的方法,其中所述方法包括在所述芯片载体(114)上设置导电突起(116)。
35.根据权利要求26至29中的任一项所述的方法,其中所述方法包括在芯片载体(114)上安装所述电子芯片(102),以及在所述芯片载体(114)上设置导电突起(116),然后至少部分密封所述突起(116)和所述电子芯片(102)。
36.根据权利要求26至29中的任一项所述的方法,其中所述方法包括通过由如下操作构成的组中的至少一项相对于所述密封体(106)暴露所述第二接触结构(112):
·在密封期间利用保护箔覆盖所述第二接触结构(112)的至少一部分,并且在所述密封之后去除所述保护箔;
·在所述密封期间,建立所述第二接触结构(112)的至少一部分与密封工具的表面的接触,以防止密封体(106)覆盖所接触的部分;
·在所述密封之后,清洁所述第二接触结构(112)的至少一部分,由此从所述部分去除所述密封体(106)的材料。
37.根据权利要求36所述的方法,其中,所述清洁是机械和/或化学清洁。
38.根据权利要求26至29中的任一项所述的方法,其中所述方法包括精整所述第二接触结构(112)的被暴露表面。
39.根据权利要求38所述的方法,其中所述精整是通过清洁、通过激活和/或通过在所述第二接触结构(112)上形成功能层(132)。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102018130292 | 2018-11-29 | ||
DE102018130292.4 | 2018-11-29 | ||
DE102019130778.3 | 2019-11-14 | ||
DE102019130778.3A DE102019130778A1 (de) | 2018-11-29 | 2019-11-14 | Ein Package, welches ein Chip Kontaktelement aus zwei verschiedenen elektrisch leitfähigen Materialien aufweist |
Publications (2)
Publication Number | Publication Date |
---|---|
CN111244041A CN111244041A (zh) | 2020-06-05 |
CN111244041B true CN111244041B (zh) | 2024-03-26 |
Family
ID=70681480
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201911164576.0A Active CN111244041B (zh) | 2018-11-29 | 2019-11-25 | 包括两种不同导电材料的芯片接触元件的封装 |
Country Status (3)
Country | Link |
---|---|
US (1) | US11056458B2 (zh) |
CN (1) | CN111244041B (zh) |
DE (1) | DE102019130778A1 (zh) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112151400B (zh) * | 2020-09-23 | 2023-04-21 | 锦州七七七微电子有限责任公司 | 一种解决smd管壳键合点金铝系统的方法 |
TWI785651B (zh) * | 2021-06-16 | 2022-12-01 | 先豐通訊股份有限公司 | 封裝結構及其製造方法、電路板及其製造方法 |
US11848244B2 (en) * | 2021-09-30 | 2023-12-19 | Texas Instruments Incorporated | Leaded wafer chip scale packages |
EP4213187A1 (en) * | 2022-01-12 | 2023-07-19 | Nexperia B.V. | Electronic package and method for manufacturing the same |
EP4333030A1 (en) * | 2022-08-31 | 2024-03-06 | Nexperia B.V. | Electronic package and manufacturing method therefor |
DE102022211788A1 (de) * | 2022-11-08 | 2024-05-08 | Zf Friedrichshafen Ag | Leistungsmodul |
DE102023200119A1 (de) * | 2023-01-10 | 2024-07-11 | Robert Bosch Gesellschaft mit beschränkter Haftung | Chip-Package und Verfahren zum Verpacken eines Bauteils |
CN115881681B (zh) * | 2023-02-23 | 2023-06-27 | 徐州致能半导体有限公司 | 一种电子器件、封装结构及其制备方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102569099A (zh) * | 2010-12-28 | 2012-07-11 | 万国半导体(开曼)股份有限公司 | 一种倒装芯片的封装方法 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040217488A1 (en) | 2003-05-02 | 2004-11-04 | Luechinger Christoph B. | Ribbon bonding |
US6835580B1 (en) | 2003-06-26 | 2004-12-28 | Semiconductor Components Industries, L.L.C. | Direct chip attach structure and method |
DE102004030042B4 (de) | 2004-06-22 | 2009-04-02 | Infineon Technologies Ag | Halbleiterbauelement mit einem auf einem Träger montierten Halbleiterchip, bei dem die vom Halbleiterchip auf den Träger übertragene Wärme begrenzt ist, sowie Verfahren zur Herstellung eines Halbleiterbauelementes |
DE102005028951B4 (de) | 2005-06-22 | 2018-05-30 | Infineon Technologies Ag | Anordnung zur elektrischen Verbindung einer Halbleiter-Schaltungsanordnung mit einer äusseren Kontakteinrichtung |
JP5141076B2 (ja) | 2006-06-05 | 2013-02-13 | 株式会社デンソー | 半導体装置 |
DE102007035902A1 (de) | 2007-07-31 | 2009-02-05 | Siemens Ag | Verfahren zum Herstellen eines elektronischen Bausteins und elektronischer Baustein |
US7799614B2 (en) | 2007-12-21 | 2010-09-21 | Infineon Technologies Ag | Method of fabricating a power electronic device |
US8138587B2 (en) * | 2008-09-30 | 2012-03-20 | Infineon Technologies Ag | Device including two mounting surfaces |
US9018742B2 (en) * | 2012-01-19 | 2015-04-28 | Infineon Technologies Ag | Electronic device and a method for fabricating an electronic device |
EP2677541A1 (en) | 2012-06-19 | 2013-12-25 | ABB Technology AG | Method for wire bonding a power semiconductor chip and the corresponding device |
US20150262918A1 (en) * | 2014-03-14 | 2015-09-17 | Texas Instruments Incorporated | Structure and method of packaged semiconductor devices with bent-lead qfn leadframes |
DE102015205704B4 (de) | 2015-03-30 | 2024-07-11 | Robert Bosch Gmbh | Kontaktanordnung und Verfahren zu Herstellung der Kontaktanordnung |
US9490192B1 (en) * | 2015-12-30 | 2016-11-08 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and manufacturing method thereof |
DE102016105581A1 (de) | 2016-03-24 | 2017-09-28 | Infineon Technologies Ag | Umleiten von Lotmaterial zu einer visuell prüfbaren Packungsoberfläche |
-
2019
- 2019-11-14 DE DE102019130778.3A patent/DE102019130778A1/de active Granted
- 2019-11-21 US US16/690,948 patent/US11056458B2/en active Active
- 2019-11-25 CN CN201911164576.0A patent/CN111244041B/zh active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102569099A (zh) * | 2010-12-28 | 2012-07-11 | 万国半导体(开曼)股份有限公司 | 一种倒装芯片的封装方法 |
Also Published As
Publication number | Publication date |
---|---|
US20200176412A1 (en) | 2020-06-04 |
CN111244041A (zh) | 2020-06-05 |
DE102019130778A1 (de) | 2020-06-04 |
US11056458B2 (en) | 2021-07-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN111244041B (zh) | 包括两种不同导电材料的芯片接触元件的封装 | |
CN103035601B (zh) | 在烧结银层上包括扩散焊接层的半导体器件 | |
KR102585450B1 (ko) | 브레이징된 전기 전도성 층을 포함하는 칩 캐리어를 구비한 몰딩된 패키지 | |
KR101947599B1 (ko) | 상이한 용융 온도를 갖는 인터커넥션들을 가진 패키지 | |
CN103426861B (zh) | 功率半导体的可靠区域接合件 | |
CN103178030B (zh) | 包括安装在dcb衬底上的分立器件的模块及制造模块的方法 | |
KR101297645B1 (ko) | 반도체 다이 패키지 및 그의 제조 방법 | |
TWI485817B (zh) | 微電子封裝及其散熱方法 | |
KR970010678B1 (ko) | 리드 프레임 및 이를 이용한 반도체 패키지 | |
US8466548B2 (en) | Semiconductor device including excess solder | |
TWI495055B (zh) | 半導體晶片封裝體及其製造方法 | |
CN101290930B (zh) | 包含半导体芯片叠层的半导体器件及其制造方法 | |
TWI628761B (zh) | 一種封裝結構及其製造方法 | |
JP4254527B2 (ja) | 半導体装置 | |
CN102593081A (zh) | 包括散热器的半导体器件 | |
CN101577237A (zh) | 包括第一和第二支座的半导体装置和方法 | |
JP5845634B2 (ja) | 半導体装置 | |
CN112928033A (zh) | 半导体裸片和夹用不同的连接方法制造半导体器件的方法 | |
CN111564415A (zh) | 具有填充的导电腔体的半导体封装 | |
TW201603201A (zh) | 嵌入式封裝及封裝方法 | |
Essig et al. | High efficient mid power modules by next generation chip embedding technology | |
CN118824985A (zh) | 将功率终端连接到半导体封装内的衬底的方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |