CN111243635B - Write data sampling signal timing monitoring method, monitoring circuit and memory - Google Patents
Write data sampling signal timing monitoring method, monitoring circuit and memory Download PDFInfo
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Abstract
本发明提供一种写数据采样信号时序监测方法、监测电路和存储器。该监测方法包括：生成提前写数据采样信号和延时写数据采样信号，提前写数据采样信号的时序提前于写数据采样信号，延时写数据采样信号的时序滞后于写数据采样信号，且提前写数据采样信号和延时写数据采样信号之间的时间差不超过写入数据信号一个周期内的有效时间；利用提前写数据采样信号和延时写数据采样信号分别对写入数据信号进行采样，判断采样结果中包含的数据种类，若仅包含一种数据，判断时序准确，否则判断时序不符合要求。本发明能够准确的监控写入时写数据采样信号的时序，以便于处理器确定应当如何调整写数据采样信号的时序。
The present invention provides a method, a monitoring circuit and a memory for monitoring the timing of a write data sampling signal. The monitoring method comprises: generating an advance write data sampling signal and a delayed write data sampling signal, wherein the timing of the advance write data sampling signal is ahead of the write data sampling signal, the timing of the delayed write data sampling signal is behind the write data sampling signal, and the time difference between the advance write data sampling signal and the delayed write data sampling signal does not exceed the effective time within one cycle of the write data signal; using the advance write data sampling signal and the delayed write data sampling signal to sample the write data signal respectively, and judging the type of data contained in the sampling result, if only one type of data is contained, judging that the timing is accurate, otherwise judging that the timing does not meet the requirements. The present invention can accurately monitor the timing of the write data sampling signal when writing, so that the processor can determine how to adjust the timing of the write data sampling signal.
Description
Technical Field
The invention relates to the technical field of memories, in particular to a write data sampling signal time sequence monitoring method, a write data sampling signal time sequence monitoring circuit and a memory.
Background
With the rapid development of memories, in order to provide memories with better performance, requirements for internal timing control of the memories are increasing.
In a write operation of a double rate synchronous dynamic random access memory (DDR SDRAM), a write data sampling signal (DQS signal) is used to clock the write data. The edges of the DQS signal should be aligned in time with the center of the data signal (DQ signal) during a write operation (taking into account timing margin, which may also allow substantial alignment at the center), as shown in FIG. 1, to obtain the most stable setup and hold window. However, the DQS signal and DQ signal may have different delays at the interface, resulting in the edges of the DQS signal not being aligned with the center of the DQ signal. Therefore, it is necessary to monitor the DQS signal timing to meet alignment requirements, and to help determine whether the DQS signal timing needs to be adjusted and to determine the manner of adjustment.
However, there is no accurate and simple monitoring method, so it is difficult to accurately adjust the DQS signal.
Disclosure of Invention
The invention aims to provide a time sequence monitoring method for a write data sampling signal, which solves one or more problems in the prior art.
Another object of the present invention is to provide a write data sampling signal timing monitoring circuit and a memory to implement the above monitoring method.
According to an aspect of the present invention, there is provided a write data sampling signal timing monitoring method applied to a write operation, including:
Generating an advanced write data sampling signal, the timing of which is advanced relative to the write data sampling signal;
Generating a delayed write data sampling signal, wherein the time sequence of the delayed write data sampling signal lags behind the write data sampling signal, and the time difference between the advanced write data sampling signal and the delayed write data sampling signal does not exceed the effective time in one period of the data signal;
respectively sampling the data signals by utilizing the advanced write data sampling signal and the delayed write data sampling signal to obtain a sampling result;
Judging the type of data contained in the sampling result, if only one type of data is contained, judging that the time sequence of the data-writing sampling signal meets the requirement, otherwise, if two types of data are contained, judging that the time sequence of the data-writing sampling signal does not meet the requirement.
In an exemplary embodiment of the present invention, the advanced write data sampling signal includes a first advanced write data sampling signal to an nth advanced write data sampling signal, and the delayed write data sampling signal includes a first delayed write data sampling signal to an nth delayed write data sampling signal, N is a natural number;
The time sequence of N advanced writing data sampling signals is different, the time sequence of N delayed writing data sampling signals is different, the time of any advanced writing data sampling signal advancing the writing data sampling signal is equal to the time of the corresponding delayed writing data sampling signal lagging behind the writing data sampling signal, and the time difference between the advanced writing data sampling signal with the largest time difference with the writing data sampling signal and the delayed writing data sampling signal does not exceed the effective time of one period of the data signal.
In an exemplary embodiment of the invention, the unsatisfactory sampling results are saved.
In an exemplary embodiment of the present invention, when the monitoring method is performed multiple times and a plurality of unsatisfactory sampling results are generated, the method further includes calculating a difference absolute value of numbers of two data types in the plurality of unsatisfactory sampling results, and covering other sampling results with the sampling result having the smallest difference absolute value.
In an exemplary embodiment of the present invention, the n=2, the write data sampling signal timing is determined to be satisfactory when the sampling result is 4'b0000 or 4' b1111, and the sampling result is stored when the sampling result is 4'b0111, 4' b0001, 4'b1000, 4' b1110, 4'b1100 or 4' b 0011.
In an exemplary embodiment of the present invention, the early write data sample signal and the late write data sample signal are both generated by delaying the write data sample signal.
According to another aspect of the present invention, there is also provided a write data sampling signal timing monitoring circuit for implementing the above method, including:
the signal generation module comprises a plurality of output ends and is used for generating and transmitting the advanced write data sampling signal and the delayed write data sampling signal;
The triggering module is connected with the data signal end and the output end of the signal generating module, and is used for receiving the data signal, the advanced writing data sampling signal and the delayed writing data sampling signal and triggering the data signal by utilizing the advanced writing data sampling signal and the delayed writing data sampling signal so as to sample;
And the judging module is connected with the triggering module, receives the sampling result and is used for judging whether the time sequence of the write data sampling signal meets the requirement according to the data type contained in the sampling result.
In an exemplary embodiment of the present invention, the signal generating module includes a plurality of buffers connected to write data sample terminals for differently delaying the write data sample signals to generate the advanced write data sample signal and the delayed write data sample signal.
In an exemplary embodiment of the present invention, the trigger module includes a plurality of triggers, and the plurality of triggers are connected to the output terminals of the signal generating module in a one-to-one correspondence.
In an exemplary embodiment of the invention, the judging module includes a comparator for determining a kind of data contained in the sampling result.
In an exemplary embodiment of the present invention, the monitoring circuit further includes a storage module, connected to the determining module, for storing the sampling result.
In an exemplary embodiment of the present invention, the judging module includes a comparator for determining a data type included in the sampling result, and an operation module for calculating an absolute value of a difference value of numbers of two data types in the saved sampling result so as to cover other sampling results with the sampling result having the smallest absolute value of the difference value by the saving module.
In an exemplary embodiment of the present invention, the determining module further includes an operation module configured to calculate an absolute value of a difference between numbers of two data types, so as to cover, by the saving module, the other sampling result with the sampling result having the smallest absolute value of the difference.
According to still another aspect of the present invention, there is also provided a memory including the above write data sampling signal timing monitoring circuit.
In an exemplary embodiment of the invention, the system further comprises a data strobe device, a trigger module connected with a plurality of data signal ends of the memory and the monitoring circuit, and used for selecting one data signal from the plurality of data signals to transmit to the trigger module so as to sample.
In an exemplary embodiment of the present invention, the memory is any one of a fourth generation double rate synchronous dynamic random access memory, a fourth generation low power consumption double rate synchronous dynamic random access memory, a fifth generation double rate synchronous dynamic random access memory, and a fifth generation low power consumption double rate synchronous dynamic random access memory.
In the writing operation, the invention utilizes two signals of which the time sequence is advanced and delayed to the writing data sampling signal to sample the data signal, and judges whether the writing data sampling signal is aligned with the center of the data signal according to the data type number contained in the sampling result. On one hand, the method can accurately monitor the time sequence of the write data sampling signal in real time so as to facilitate the processor to determine how to adjust the time sequence of the write data sampling signal, and on the other hand, the circuit structure for realizing the method is simple and easy to implement, occupies less circuit resources, and is beneficial to cost and area control.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention. It is evident that the drawings in the following description are only some embodiments of the present invention and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is an eye diagram of a DDR data signal;
FIG. 2 is a schematic diagram of a write data transfer scheme for DDR DRAM;
FIG. 3 is a flow chart of a method for monitoring DQS signal timing according to the present invention;
FIG. 4 is an eye diagram corresponding to the DQS signal timing monitoring method of the present invention;
FIG. 5 is a flowchart of another method for DQS signal timing monitoring according to the present invention;
FIG. 6 is a schematic diagram of a DQS signal timing monitor circuit according to the present invention.
In the figure, a signal generation module 101, a trigger module 102, a judgment module 103, a storage module 104.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, but rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus detailed descriptions thereof will be omitted.
In the related art, taking the fourth generation low power consumption double rate synchronous dynamic random access memory (LPDDR 4) as an example, as shown in fig. 2, a data signal (hereinafter, DQ signal) receiving module is usually beside a DQ input port, and a write data sampling signal (hereinafter, DQs signal) needs to be pulled from the DQs input port to each DQ receiving module, so that when a write operation is performed, an internal delay of the DQs signal is greater than an internal delay of the DQ signal in a receiving direction, resulting in that an edge of the DQs signal cannot be aligned with a center of the DQ signal in time sequence, which affects an accurate trigger of a write operation.
To improve this, the memory requires the controller to compensate for the delay difference between the DQS signal and the DQ signal, which is sent earlier than the DQ signal to ensure that the two are aligned. The advanced transmit time is defined in the JEDEC standard, tDQS DQ. The standard requires LPDDR4 with tDQS DQ ranging from 200ps to 800ps. Meanwhile, the LPDDR4 also tracks and adjusts tDQS DQ values through an oscillator to ensure that the DQS signal and the DS signal can accurately make up for the time sequence gap.
After the DQS signal is sent, it is confirmed whether its edges are aligned in time with the center of the DQ signal, and it can be determined whether the currently set tDQS DQ 2DQ value is appropriate. If aligned, the value of tDQS DQ does not need to be adjusted, and if not aligned, the value of tDQS DQ needs to be adjusted. One judgment mode which can be realized at present is that the read or write operation is sent to confirm by changing tDQS DQ values through the DRAM controller, the process is complicated, and if the sending data volume is too small to accurately reflect the working condition, the bandwidth is wasted if the sending data volume is too large. Moreover, this approach has a 20ps error, and for LPDDR5 and DDR5 the transmission rate needs to reach 6400Mbps, where only 156.25ps is a clock cycle, the active part is likely to be 100ps only, and 20ps error accuracy may not be sufficient to adjust the tDQS DQ value.
In an embodiment of the invention, a DQS signal timing monitoring method is provided for monitoring whether an edge of a DQS signal is aligned with a center of a DQ signal in timing when a memory performs a write operation. The monitoring method can be used for timing monitoring of a dynamic random access memory, such as a fourth generation double rate synchronous dynamic random access memory (DDR 4), a fourth generation low power consumption double rate synchronous dynamic random access memory (LPDDR 4), a fifth generation double rate synchronous dynamic random access memory (DDR 5), a fifth generation low power consumption double rate synchronous dynamic random access memory (LPDDR 5), and the like, which are not listed here, and the LPDDR4 is taken as an example.
As shown in fig. 3, the DQS signal timing monitoring method according to the embodiment of the invention includes:
Step S110, generating a DQS signal with a timing advanced with the DQS signal, generating a delayed DQS signal with a timing delayed with the DQS signal, wherein the time difference between the DQS signal and the delayed DQS signal is not more than the effective time in one period of the DQ signal;
Step S210, sampling DQ signals by using the advanced DQS signal and the delayed DQS signal respectively to obtain sampling results;
Step S310, judging the kind of data contained in the sampling result, if only one kind of data is contained, judging that the DQS signal time sequence meets the requirement, otherwise, if two kinds of data are contained, judging that the DQS signal time sequence does not meet the requirement.
Referring to fig. 4, the DQS signal is sampled with two signals whose timings are advanced and delayed, and since the time difference of the two signals is within the effective time of one DQ signal period, if the sampling results are identical, it is indicated that both the advanced DQS signal and the delayed DQS signal correspond to within the DQ signal effective window, and the DQS signal timing symbols whose timings lie therebetween are summed. If different sampling results appear in the advance DQS signal and the delay DQS signal, indicating that one of the advance DQS signal and the delay DQS signal does not correspond to the DQ signal valid window, the DQS signal with the time sequence between the two is inevitably deviated from the center of the DQ signal, is not aligned with the DQS signal, and is not satisfactory.
The time difference between the advanced DQS signal and the delayed DQS signal does not exceed the effective time within one period of the data signal, so as to ensure that the sampling result can accurately reflect whether the time sequence is correct. If the valid time in one period is exceeded, the DQS signal must be advanced or delayed beyond the valid window of the DQ signal, two data types can appear in the sampling result no matter whether the DQS signal is aligned with the center of the DQ signal, and erroneous judgment can be caused by the fact that the time sequence is not in accordance with the requirements. If the sampling result is not within the effective time, the sampling result cannot accurately reflect the accuracy of the time sequence.
Since the type of data contained in the sampling result can only be 0 or 1, if the result of advancing the DQS signal and delaying the DQS signal is 0 in the result of each sampling, the DQS signal is aligned with the DQ signal center, which indicates that the data transferred by the DQ signal is 0. If both are 1, the same applies. If there are both 0 and 1 in the sampling result, it indicates that the DQS signal is not aligned with the DQ signal center, and the offset is large and unsatisfactory. According to the principle, whether the time sequence of DQS signals is in accordance with the requirement can be conveniently and accurately known.
The method of the invention can be used for time sequence monitoring in the test stage and time sequence monitoring when a user uses the method.
The following describes a timing monitoring method according to an embodiment of the present invention in detail:
In the present exemplary embodiment, the advance DQS signal in step S110 includes a first advance DQS signal to an N-th advance DQS signal, the delay DQS signal includes a first delay DQS signal to an N-th delay DQS signal, the timing sequences of the advance DQS signal and the delay DQS signal correspond one-to-one, and N is a natural number. The time sequence of the N advanced DQS signals is different, the time sequence of the N delayed DQS signals is different, the time of any advanced DQS signal advanced by the DQS signal is equal to the time of the corresponding delayed DQS signal lagging the DQS signal, and the time difference between the advanced DQS signal with the largest time sequence difference with the DQS signal and the delayed DQS signal does not exceed the effective time of one cycle of the DQS signal.
Specifically, the advance DQS signal and the delayed DQS signal may each comprise a plurality and be equal in number, i.e., the advance DQS signal comprises a first advance DQS signal, a second advance DQS signal, an N-1 advance DQS signal, an N advance DQS signal, and the delayed DQS signal comprises a first delayed DQS signal, a second delayed DQS signal, an N-1 delayed DQS signal, an N delayed DQS signal. According to the timing ordering, the first advanced DQS signal corresponds to the first delayed DQS signal, the second advanced DQS signal corresponds to the second delayed DQS signal, and the N advanced DQS signal corresponds to the N delayed DQS signal. Meanwhile, the time of the first advanced DQS signal in advance of the DQS signal is equal to the time of the first delayed DQS signal lagging behind the DQS signal, the time of the second advanced DQS signal in advance of the DQS signal is equal to the time of the second delayed DQS signal lagging behind the DQS signal. And, the time difference between the N-th advanced DQS signal and the N-th delayed DQS signal does not exceed the active time of one cycle of the DQ signal. When n=1, the timing sequence of the DQS signal can be detected only by sampling and monitoring one advanced DQS signal and one delayed DQS signal, but the accuracy is lower. The larger N is, the sampling monitoring is needed to be carried out through a plurality of advanced DQS signals and a plurality of delayed DQS signals at the same time, and the accuracy is higher.
For example, the DQ signal of LPDDR4 has a period of 156.25 picoseconds, where the active time is 100 picoseconds, and in one exemplary embodiment, n=2, as shown in fig. 4, the advance DQs signal includes a first advance DQs signal and a second advance DQs signal, and the corresponding delayed DQs signal includes a first delayed DQs signal and a second delayed DQs signal. The time difference between the first advanced DQS signal and the DQS signal is-20 picoseconds and the time difference between the second advanced DQS signal and the DQS signal is-50 picoseconds. The time difference between the first delayed DQS signal and the DQS signal is +20 picoseconds and the time difference between the second delayed DQS signal and the DQS signal is +50 picoseconds.
In step S210 and step S310, four signals are used to sample DQ data simultaneously, and the sampling results are sorted according to the sequence from the early to the late, and if the sampling result only includes one kind of data, that is, the sampling result is 4'b0000 or 4' b1111, it is determined that the DQs signal sequence meets the requirement. If the sampling result contains two kinds of data, namely, the sampling result is 4'b0111, 4' b0001, 4'b1000, 4' b1110, 4'b1100 or 4' b0011, the DQS signal timing is judged to be unsatisfactory. For sampling data whose timing is not satisfactory, 4' b0111 indicates that the data of DQ data transmission is 1, and the second advanced DQS signal is located at the left side of the DQ signal valid window, which indicates that the DQS signal is not aligned with the center of the DQ signal and is located far to the left, i.e. the timing of the DQS signal is earlier, the DQS signal needs to be further delayed to be sent, i.e. the value of tDQS DQ is reduced. Similarly, 4' b1110 indicates that the data representing DQ data transfer is 1 and the second delayed DQS signal is to the right of the DQ signal valid window, indicating that the DQS signal is not centered and is right-shifted, i.e., the DQS signal is late in timing, requiring further advance transmission of the DQS signal, i.e., increasing the value of tDQS DQ. The timing analysis is the same for the 4'b0001, 4' b1000 transfer data only. If the sampling result is 4' b1100, it indicates that both signals are located outside the valid window of the DQ signal, and may be the advanced DQs signal or the delayed DQs signal, at this time, it cannot be determined what data is transmitted, and it indicates that the DQs signal has a large center deviation from the DQ signal, and the value of tDQS DQ needs to be adjusted, which does not meet the requirement, but it cannot be determined whether the DQs signal timing is advanced or retarded, and therefore it cannot be directly inferred that the value of tDQS DQ should be increased or decreased. The same applies when the sampling result is 4' b 0011.
The timing margin of the memory is taken into account in advancing the DQS signal and delaying the time difference between the DQS signal and the DQS signal. Because the timing margin determines the deviation degree of the DQS signal in the DQ signal center, if the timing margin is smaller, the DQS signal is required to be strictly aligned with the DQ signal center, the time difference between the advanced DQS signal and the delayed DQS signal needs to be set larger at the moment, and once the DQS signal is slightly deviated, the phenomenon that the advanced DQS signal or the delayed DQS signal is located outside the valid window of the DQ signal (namely, two data types can appear) occurs, so that the DQS signal is not strictly aligned with the DQ signal center at present, and the DQS signal is not in accordance with the requirement. If the timing margin is large, which means that DQS is allowed to be basically aligned within a certain range around the DQ signal center, the time difference between the advanced DQS signal and the delayed DQS signal can be set smaller, and as long as the DQS signal deviates within the set range of the timing margin, the phenomenon that the advanced DQS signal or the delayed DQS signal does not correspond to the DQ signal within the valid window (namely, only one data type can appear) can not occur, and the DQS signal is considered to be basically aligned with the DQ signal center at present, so that the DQS signal meets the requirements. In this exemplary embodiment, the-20, +20 picosecond setting time is set according to the minimum timing margin acceptable to the system, the-50, +50 picosecond setting time is set according to the maximum timing margin acceptable to the system (long-term steady operation margin), and the processor can know whether the timing margin is appropriate or not according to the sampling result. In other exemplary embodiments of the present invention, the need for adjusting the accuracy of each of the early DQS signal and the delayed DQS signal to the DQS signal may also be set to other values, which are not listed here.
In other exemplary embodiments of the present invention, N may also be other values, for example, n=1, and the sampling result may be 4'b11, 4' b00, 4'b01, 4' b10.4'b11, 4' b00 indicate that the DQS signal timing is satisfactory, and 4'b01, 4' b10 indicate that it is undesirable. As another example, n=3, the sampling result may be 4'b01111, 4' b00001, 4'b00011, 4' b00111,. Similarly, if N is other values, it can be inferred whether the DQS signal is aligned with the DQ signal center, and the determination method is the same, which is not described here again.
In addition, in other exemplary embodiments of the present invention, the time that any of the advanced DQS signals advances from the DQS signal may not be equal to the time that the corresponding delayed DQS signal lags behind the DQS signal, as long as the set timing difference is guaranteed to ensure that even if the DQS signal is offset in the center of the DQ signal window, the timing margin of the system is sufficient to accept the offset.
In this exemplary embodiment, as shown in fig. 5, the monitoring method of the present invention further includes:
step S410, the sampling result which does not meet the requirement of the time sequence is stored.
And storing the sampling result with the unsatisfactory time sequence, and allowing the processor to read the monitoring result to determine whether the value of tDQS DQ is wrong, thereby further adjusting the value of tDQS DQ. The sampling result may be stored in a register and read by setting an associated read instruction in a mode register of the memory.
When the monitoring method is executed for a plurality of times and a plurality of sampling results with non-satisfactory time sequences are generated, in the step S410, when the plurality of sampling results with non-satisfactory time sequences are stored, the absolute value of the difference value of the numbers of two data types in the plurality of sampling results with non-satisfactory time sequences is calculated, and the sampling results with the smallest absolute value of the difference value are used for covering other sampling results.
The smaller the absolute value of the difference value of the numbers of the two data types in the sampling result with the unconditional time sequence is, the closer the numbers of the two data types are, the more serious the unconditional situation is, and other unconformity results are covered by the most serious unconformity results, so that the most serious time sequence problem of DQS signals is known when the processor reads the results, and the adjustment is needed urgently. For example, taking a sampling result with a timing unsatisfactory in n=2 as an example, when the sampling result is 4'b1100 or 4' b0011, the two data numbers are equal, the absolute value of the difference is 0, the DQS signal timing problem is most serious, the sampling result is 4'b0111, 4' b0001, 4'b1000 or 4' b1110, the two data numbers are unequal, and the absolute value of the difference is 2, which indicates that the DQS signal has a slight timing problem. Once the sampling result of 4'b1100 or 4' b0011 appears, it is used to override other erroneous results.
In the present exemplary embodiment, both the early DQS signal and the delayed DQS signal may be generated by phase-delaying the DQS signal by a phase-delaying circuit, and thus the generated early DQS signal and the delayed DQS signal can ensure synchronicity with the DQS signal to accurately determine the timing of the DQS signal. The phase delay circuit may be a buffer.
The embodiment of the invention also provides a DQS signal time sequence monitoring circuit for realizing the monitoring method, which comprises a signal generating module 101, a triggering module 102 and a judging module 103, wherein the signal generating module 101 comprises a plurality of output ends for generating and transmitting the advanced DQS signal and the delayed DQS signal as shown in figure 5. The trigger module 102 is connected to the DQ signal end and the output end of the signal generating module, and receives the DQ signal, the advance DQs signal and the delay DQs signal, and is configured to trigger the DQ signal by using the advance DQs signal and the delay DQs signal, so as to perform sampling. The judging module 103 is connected to the triggering module, receives the sampling result, and is configured to judge whether the timing sequence meets the requirement according to the data type contained in the sampling result.
In the present exemplary embodiment, signal generation module 101 includes a plurality of buffers coupled to the DQS signal terminals for differently phase delaying the DQS signal to generate an early DQS signal and a delayed DQS signal. For example, as shown in fig. 6, when n=2, four buffers are required to delay DQS phase respectively to generate four different timing advance DQS signals and delay DQS signals. The buffer may be in a common two-serial CMOS tube structure or other structures, and the invention is not limited in particular.
In the present exemplary embodiment, the trigger module 102 includes a plurality of flip-flops that are connected in one-to-one correspondence with the outputs of the signal generation module to generate the advance DQS signal and the delay DQS signal. As shown, when n=2, four flip-flops are required in total, and are connected in one-to-one correspondence with four buffers to respectively trigger sampling of DQ signals. The flip-flop includes, but is not limited to, a pulse type flip-flop, which is not particularly limited by the present invention.
In the present exemplary embodiment, the judging module 103 includes a comparator for determining the kind of data in the sampling result. The comparator may adopt an exclusive or gate structure, and determine the kind of data included in the sampling result by comparing whether the phase of the advanced DQS signal or the delayed DQS signal is the same as the preset phase, and outputting different results. Other structures may be adopted for the comparator, and the invention is not particularly limited thereto.
In this exemplary embodiment, the monitoring circuit further includes a storage module 104, and the connection determination module stores the sampling result in which the time sequence does not meet the requirement. The save module may be a register that saves results for the processor to read.
In another exemplary embodiment of the present invention, the judging module 103 may further include a comparator and an operation module. The comparator is used for determining the type of the data in the sampling result, and as described above, the comparator may adopt an exclusive or gate structure, and determine the type of the data contained in the sampling result by comparing whether the phase of the advanced DQS signal or the delayed DQS signal is the same as the preset phase or not to output different results. The operation module can calculate the absolute value of the difference value of the numbers of the two data types in the stored sampling results through the digital logic circuit, and the storage module covers other sampling results with the sampling result with the smallest absolute value of the difference value, so that the processor can know the worst time sequence situation and then make proper adjustment. The digital logic circuit may have an existing circuit structure, and the present invention is not limited thereto.
In the above embodiment, the data signal for monitoring is from the DQ0 pin, and in other embodiments of the present invention, other DQ pins may be used for monitoring.
The embodiment of the invention also provides a memory, which comprises the DQS signal time sequence monitoring circuit, can accurately provide time sequence monitoring results, is beneficial to timely adjusting signal time sequence when a processor writes data, and can more accurately execute writing operation. The memory can be any one of a fourth generation double-rate synchronous dynamic random access memory, a fourth generation low-power-consumption double-rate synchronous dynamic random access memory, a fifth generation double-rate synchronous dynamic random access memory and a fifth generation low-power-consumption double-rate synchronous dynamic random access memory.
In this exemplary embodiment, the memory further includes a data strobe connected to the plurality of DQ terminals of the memory and the trigger module in the monitoring circuit, for selecting one DQ signal from the plurality of DQ signals to transmit to the trigger module for monitoring. Only one DQ end is selected from DQ 0-7 for detection, so that the requirement of monitoring time sequence can be met, and circuit resources can be saved. Meanwhile, different DQ ends can be used for monitoring at different times, so that resources are effectively utilized, and meanwhile, the monitoring can be fully and comprehensively carried out.
The monitoring method and the monitoring circuit sample DQ signals by utilizing two signals of which the time sequence is advanced and delayed, and judge whether the DQS signals are aligned with the center of the DQ signals according to the number of data types contained in the sampling result. On the one hand, the method can accurately monitor the time sequence of the DQS signal during writing so that a processor can determine how the time sequence of the DQS signal should be adjusted, and on the other hand, the circuit structure for realizing the method is simple and feasible, occupies less circuit resources, and is beneficial to cost and area control.
Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification for convenience only, such as in terms of the orientation of the examples described in the figures. It will be appreciated that if the device of the icon is flipped upside down, the recited "up" component will become the "down" component. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.
The terms "a," "an," "the," "said" and "at least one" are used to indicate the presence of one or more elements/components/etc., and the terms "comprising" and "having" are intended to mean that there may be additional elements/components/etc. in addition to the listed elements/components/etc.
Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
Claims (15)
1. A write data sampling signal timing monitoring method, applied to a write operation, comprising:
Generating an advanced write data sampling signal, the timing of which is advanced relative to the write data sampling signal;
Generating a delayed write data sampling signal, wherein the time sequence of the delayed write data sampling signal lags behind the write data sampling signal, and the time difference between the advanced write data sampling signal and the delayed write data sampling signal does not exceed the effective time in one period of the data signal;
respectively sampling the data signals by utilizing the advanced write data sampling signal and the delayed write data sampling signal to obtain a sampling result;
Judging the type of data contained in the sampling result, if only one type of data is contained, judging that the time sequence of the data-writing sampling signal meets the requirement, otherwise, if two types of data are contained, judging that the time sequence of the data-writing sampling signal does not meet the requirement.
2. The method for monitoring the time sequence of the write data sampling signals according to claim 1, wherein the write data sampling signals comprise first write data sampling signals to Nth write data sampling signals in advance, the delay write data sampling signals comprise first delay write data sampling signals to Nth delay write data sampling signals, and N is a natural number;
The time sequence of N advanced writing data sampling signals is different, the time sequence of N delayed writing data sampling signals is different, the time of any advanced writing data sampling signal advancing the writing data sampling signal is equal to the time of the corresponding delayed writing data sampling signal lagging behind the writing data sampling signal, and the time difference between the advanced writing data sampling signal with the largest time difference with the writing data sampling signal and the delayed writing data sampling signal does not exceed the effective time of one period of the data signal.
3. The write data sampling signal timing monitoring method of claim 1, further comprising:
And storing the sampling result which does not meet the requirements.
4. The method of claim 3, wherein the method is performed a plurality of times and when generating a plurality of unsatisfactory sampling results, further comprising:
And calculating the absolute value of the difference value of the numbers of two data types in a plurality of sampling results with the time sequence which does not meet the requirement, and covering other sampling results with the sampling result with the minimum absolute value of the difference value.
5. The method according to claim 2, wherein n=2, wherein the sampling result is 4'b0000 or 4' b1111, and the sampling result is stored when the sampling result is 4'b0111, 4' b0001, 4'b1000, 4' b1110, 4'b1100 or 4' b 0011.
6. The write data sample signal timing monitoring method of claim 1, wherein the early write data sample signal and the late write data sample signal are both generated by delaying the write data sample signal.
7. A write data sampling signal timing monitoring circuit for implementing the method of any of claims 1-6, comprising:
the signal generation module comprises a plurality of output ends and is used for generating and transmitting the advanced write data sampling signal and the delayed write data sampling signal;
The triggering module is connected with the data signal end and the output end of the signal generating module, and is used for receiving the data signal, the advanced writing data sampling signal and the delayed writing data sampling signal and triggering the data signal by utilizing the advanced writing data sampling signal and the delayed writing data sampling signal so as to sample;
And the judging module is connected with the triggering module, receives the sampling result and is used for judging whether the time sequence of the write data sampling signal meets the requirement according to the data type contained in the sampling result.
8. The write data sample signal timing monitoring circuit of claim 7, wherein the signal generation module comprises a plurality of buffers coupled to write data sample signal terminals for differently delaying the write data sample signal to generate the advanced write data sample signal and the delayed write data sample signal.
9. The write data sampling signal timing monitoring circuit of claim 7, wherein the trigger module comprises a plurality of flip-flops coupled in one-to-one correspondence with the output of the signal generation module.
10. The write data sample signal timing monitoring circuit of claim 7, wherein the determination module comprises a comparator for determining a type of data contained in the sample result.
11. The write data sample signal timing monitoring circuit of claim 10, further comprising:
and the storage module is connected with the judging module and used for storing the sampling results which do not meet the requirements.
12. The write data sampling signal timing monitoring circuit of claim 11, wherein said determination module comprises a comparator for determining a data type contained in said sampling result and an operation module for calculating a difference absolute value of the numbers of two data types in said sampling result held so as to cover other of said sampling results with said sampling result whose difference absolute value is smallest by said holding module.
13. A memory comprising the write data sample signal timing monitoring circuit of any of claims 7-12.
14. The memory of claim 13, further comprising:
And the data strobe is connected with a plurality of data signal ends of the memory and the trigger module of the monitoring circuit and is used for selecting one data signal from the plurality of data signals to transmit to the trigger module so as to sample.
15. The memory of claim 14, wherein the memory is any one of a fourth generation double rate synchronous dynamic random access memory, a fourth generation low power consumption double rate synchronous dynamic random access memory, a fifth generation double rate synchronous dynamic random access memory, and a fifth generation low power consumption double rate synchronous dynamic random access memory.
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| CN114461473B (en) * | 2022-01-29 | 2023-03-31 | 北京奕斯伟计算技术股份有限公司 | Method for detecting time sequence of serializer, detection circuit and electronic device |
| CN115113812B (en) * | 2022-05-20 | 2024-10-01 | 腾讯科技（深圳）有限公司 | Write data signal delay control method, device, equipment and medium |
| US12019120B2 (en) | 2022-05-26 | 2024-06-25 | Changxin Memory Technologies, Inc. | Method and device for evaluating performance of sequential logic element |
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