CN111240395B - Reference voltage source with high power supply rejection ratio - Google Patents
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- G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
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Abstract
The invention discloses a reference voltage source with high power supply rejection ratio, which comprises a voltage reference core, a local voltage generating circuit and a super source follower, wherein the voltage reference core is used for providing reference voltage, the local voltage generating circuit is used for generating local voltage, the super source follower is used for stabilizing the local voltage generating circuit, the local voltage generating circuit is arranged to generate local voltage which is less changed along with a power supply in a loop, and the local power supply which is isolated from the power supply is provided for the voltage reference core and the super source follower, so that the voltage reference value jitter caused by power supply ripples is reduced, the power supply rejection ratio of the reference voltage source is improved, the circuit structure is simple, the noise performance is good, and the super source follower is suitable for keeping the high power supply rejection ratio in a full frequency domain range.
Description
Technical Field
The invention relates to the technical field of reference voltage sources, in particular to a reference voltage source with a high power supply rejection ratio.
Background
In the field of power management, the input voltage range of a power management chip is wide, and in order to ensure the working stability and consistency of the chip, an on-chip voltage reference source is required to be insensitive to the change of power voltage, namely, the voltage reference source is required to provide a stable reference direct current level which is irrelevant to the process and has a determined temperature characteristic for each module in the chip. In general, the output voltage of the voltage reference source fluctuates due to the influence of the input power supply ripple, and particularly in a high-speed digital-analog hybrid circuit, a large amount of switching signals generate large fluctuations on a power supply line and a ground line, so the voltage reference source with a high power supply rejection ratio is particularly important.
At present, a commonly used method for improving the power supply rejection ratio of a voltage reference source is to use a negative feedback circuit with an operational amplifier for adjustment, but an operational amplifier with high open-loop gain needs to be designed, and with the introduction of the operational amplifier with high open-loop gain, not only power consumption and complexity of the circuit are increased, but also noise of the circuit is amplified.
Disclosure of Invention
The invention aims to provide a reference voltage source with simple structure, high integration level, low noise and high power supply rejection ratio.
In order to solve the above problems, the present invention provides a reference voltage source with a high power supply rejection ratio, comprising a local voltage generating circuit for generating a local voltage, a voltage reference core for providing a reference voltage, and a super source follower for stabilizing the local voltage generating circuit;
the local voltage generating circuit is provided with a power supply input end, a second bias voltage output end, a third bias voltage output end, a local voltage output end and a grounding end, wherein the power supply input end is connected with an external power supply, the second bias voltage output end is used for providing a second bias voltage, the third bias voltage output end is used for providing a third bias voltage, and the local voltage output end is used for outputting a local voltage;
the voltage reference core is provided with a first local voltage input end, a first bias voltage output end and a ground end, wherein the first local voltage input end is used for accessing local voltage, and the first bias voltage output end is used for providing first bias voltage;
the super source follower is provided with a first bias voltage input end, a second bias voltage input end, a third bias voltage input end, a second local voltage input end and a grounding end, wherein the first bias voltage input end is used for being connected with a first bias voltage, the second bias voltage input end is used for being connected with a second bias voltage, the third bias voltage input end is used for being connected with a third bias voltage, and the second local voltage input end is used for being connected with a local voltage.
Further, the local voltage generating circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, and a sixth PMOS transistor, wherein a source of the fourth PMOS transistor is connected to a drain of the fifth PMOS transistor, a drain of the fourth PMOS transistor is connected to a drain of the first NMOS transistor, a gate of the second NMOS transistor, and a gate of the fourth NMOS transistor, a source of the fifth PMOS transistor is connected to a source of the sixth PMOS transistor, a gate of the fifth PMOS transistor is connected to a gate of the sixth PMOS transistor, a drain of the sixth PMOS transistor, and a drain of the third NMOS transistor, a gate of the third NMOS transistor is connected to the gate of the first NMOS transistor, a source of the first NMOS transistor is connected to the drain of the second NMOS transistor, a gate of the second NMOS transistor is further connected to the gate of the fourth NMOS transistor, and a drain of the fourth NMOS transistor is connected to a source of the third NMOS transistor, the source electrode of the second NMOS tube and the source electrode of the fourth NMOS tube are grounded, the power input end is connected between the source electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube, the local voltage output end is connected between the source electrode of the fourth PMOS tube and the drain electrode of the fifth PMOS tube, the second bias voltage output end is connected between the grid electrode of the first NMOS tube and the grid electrode of the third NMOS tube, and the third bias voltage output end is connected between the grid electrode of the second NMOS tube and the grid electrode of the fourth NMOS tube.
Further, the voltage reference core comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first triode, a second triode, a third triode, a first resistor and a second resistor, wherein a source electrode of the first PMOS transistor, a source electrode of the second PMOS transistor and a source electrode of the third PMOS transistor are all connected with a local voltage output end, a gate electrode of the first PMOS transistor is connected with a drain electrode thereof, a gate electrode of the second PMOS transistor, a gate electrode of the third PMOS transistor and a gate electrode of the fourth PMOS transistor, a drain electrode of the first PMOS transistor is also connected with a collector electrode of the first triode, an emitter electrode of the first triode is grounded through the first resistor, a drain electrode of the second PMOS transistor is connected with a collector electrode of the second triode, an emitter electrode of the second triode is grounded, a drain electrode of the third PMOS transistor is connected with a collector electrode of the third triode, and an emitter electrode of the third triode is grounded through the second resistor, the base electrode of the first triode is connected with the base electrode of the second triode and the base electrode of the third triode, the source electrode of the first PMOS tube, the source electrode of the second PMOS tube and the source electrode of the third PMOS tube are connected to be used as a first local voltage input end of a voltage reference core, and the first bias voltage output end is connected between the drain electrode of the second PMOS tube and the collector electrode of the second triode.
Further, the super source follower comprises a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a third resistor, a fourth resistor, a first capacitor and a second capacitor, wherein a source electrode of the seventh PMOS transistor is connected to a drain electrode of the seventh NMOS transistor, a drain electrode of the seventh PMOS transistor is connected to a source electrode of the eighth PMOS transistor, a drain electrode of the eighth PMOS transistor is connected to a source electrode of the ninth PMOS transistor, a drain electrode of the ninth PMOS transistor is connected to a drain electrode of the fifth NMOS transistor and a gate electrode of the seventh NMOS transistor, a source electrode of the fifth NMOS transistor is connected to a drain electrode of the sixth NMOS transistor, a source electrode of the seventh NMOS transistor, a gate electrode of the eighth PMOS transistor and a gate electrode of the ninth PMOS transistor are all grounded, one end of the first capacitor is connected between the source electrode of the seventh PMOS transistor and the drain electrode of the seventh NMOS transistor, and the other end of the first capacitor is connected to one end of the third resistor, the other end of the third resistor is connected between the drain electrode of the ninth PMOS tube and the grid electrode of the seventh NMOS tube, one end of the fourth resistor is connected between the drain electrode of the sixth PMOS tube and the grid electrode of the seventh NMOS tube, the other end of the fourth resistor is grounded through the second capacitor, all second local voltage input ends are further connected between the source electrode of the seventh PMOS tube and the drain electrode of the seventh NMOS tube, the grid electrode of the seventh PMOS tube is connected with a first bias voltage input end, the grid electrode of the fifth NMOS tube is connected with a second bias voltage input end, and the grid electrode of the sixth NMOS tube is connected with a third bias voltage input end.
The invention has the beneficial effects that: the circuit generates a local voltage with smaller amplitude change along with the power supply by increasing the local voltage generating circuit, and provides the local voltage isolated from the power supply for the voltage reference core and the super source follower, so that the jitter of the voltage reference value caused by power supply ripples is reduced, the power supply rejection ratio of the reference voltage source is improved, the circuit structure is simple, the noise performance is good, and the circuit is suitable for keeping the high power supply rejection ratio in the full frequency domain range.
Drawings
FIG. 1 is a circuit diagram of a preferred embodiment of a reference voltage source with high power supply rejection ratio according to the present invention.
Detailed Description
The invention will be further explained with reference to the drawings.
In the description of the present invention, unless otherwise specified and limited, it is to be noted that the term "connected" is to be interpreted broadly, and may be, for example, a mechanical connection or an electrical connection, or a communication between two elements, or may be a direct connection or an indirect connection through an intermediate medium, and a specific meaning of the term may be understood by those skilled in the art according to specific situations.
Fig. 1 is a circuit diagram of a reference voltage source with high power supply rejection ratio according to a preferred embodiment of the present invention, which is used to provide a reference voltage for subsequent modules (such as data converters, voltage regulators, etc.) in the circuit. The preferred embodiment of the reference voltage source comprises a local voltage generation circuit 1, a voltage reference core 2 and a super source follower 3. The local voltage generating circuit 1 is used for generating local voltage to provide a stable local power supply for the voltage reference core 2 and the super source follower 3. The voltage reference core 1 is configured to output a stable reference voltage and provide a reference for a subsequent module. The super source follower 3 is used for stabilizing the local voltage generating circuit 1, so that the local voltage generating circuit 1 can generate a stable local voltage. In this embodiment, the super source follower 3 provides a low-resistance path to ground for the local voltage generating circuit 1 through a negative feedback loop formed, so that the local voltage generating circuit 1 is more similar to the ideal voltage source, and the local voltage generating circuit 1 is further stabilized.
With continued reference to fig. 1, the local voltage generating circuit 1 has a power input terminal VDD for accessing an external power supply, a second bias voltage output terminal V2o, a third bias voltage output terminal V3o, a local voltage output terminal VO, and a ground terminal, wherein the second bias voltage output terminal V2o is configured to provide a second bias voltage to the super source follower 3, the third bias voltage output terminal V3o is configured to provide a third bias voltage to the super source follower 3, and the local voltage output terminal VO is configured to output a local voltage to power the voltage reference core 2 and the super source follower 3.
The local voltage generating circuit 1 includes a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3 and a fourth NMOS transistor MN4, a source of the fourth PMOS transistor MP4 is connected to a drain of the fifth PMOS transistor MP5, a drain of the fourth PMOS transistor MP4 is connected to a drain of the first NMOS transistor MN1, a source of the fifth PMOS transistor MP5 is connected to a source of the sixth PMOS transistor MP6, a gate of the fifth PMOS transistor MP5 is connected to a gate of the sixth PMOS transistor MP6, a drain of the sixth PMOS transistor MP6 and a drain of the third NMOS transistor MN3, a gate of the third NMOS transistor MN3 is connected to a gate of the first NMOS transistor MN1, a drain of the first NMOS transistor MN1 is connected to a drain of the second NMOS transistor MN2, a drain of the second NMOS transistor MN 86 2 is connected to a gate of the fourth NMOS transistor MN 368658, and a drain of the fourth NMOS transistor MN 368658, the source electrode of the second NMOS transistor MN2 and the source electrode of the fourth NMOS transistor MN4 are both grounded.
The source of the fifth PMOS transistor MP5 and the source of the sixth PMOS transistor MP6 are connected as the power input end VDD of the entire local voltage generating circuit 1 and the external power supply VDDThe source of the fourth PMOS transistor MP4 and the drain of the fifth PMOS transistor MP5 are connected to provide a stable local voltage as a local voltage output terminal VO for the voltage reference core 2 and the super source follower 3, the gate of the first NMOS transistor MN1 and the gate of the third NMOS transistor MN3 are connected to provide a second bias voltage as a second bias voltage output terminal V2o for the super source follower 3, and the gate of the second NMOS transistor MN2 and the gate of the fourth NMOS transistor MN4 are connected to provide a third bias voltage as a third bias voltage output terminal V3o for the super source follower 3.
The voltage reference core 2 has a first local voltage input terminal VI1 (not shown), a first bias voltage output terminal V1o and a ground terminal, the first local voltage input terminal VI1 (not shown) is connected to the local voltage output terminal VO for receiving a local voltage to supply the voltage reference core 2, and the first bias voltage output terminal V1o is used for providing a first bias voltage to the super source follower 3.
The voltage reference core 2 comprises a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first triode Q1, a second triode Q2, a third triode Q3, a first resistor R1 and a second resistor R2, the source of the first PMOS transistor MP1, the source of the second PMOS transistor MP2 and the source of the third PMOS transistor MP3 are all connected with the local voltage output terminal VO, the gate and the drain of the first PMOS transistor MP1, the gate of the second PMOS transistor MP2, the gate of the third PMOS transistor MP3 and the gate of the fourth PMOS transistor 4 are all connected, the drain of the first PMOS transistor MP1 is further connected with the collector of the first triode Q1, the emitter of the first triode Q1 is grounded through the first resistor R1, the drain of the second PMOS transistor MP2 is connected with the drain of the second triode Q2, the collector of the second PMOS transistor MP 69556 is grounded, and the collector of the third PMOS transistor MP 8653 is connected with the drain of the third PMOS transistor MP3, the emitter of the third triode Q3 is grounded through the second resistor R2, and the base of the first triode Q1 is connected with the base of the second triode Q2 and the base of the third triode Q3.
The source of the first PMOS transistor MP1, the source of the second PMOS transistor MP2, and the source of the third PMOS transistor MP3 are connected to serve as a first local voltage input terminal VI1 (not shown) of the voltage reference core 2 to provide a stable local voltage for the voltage reference core 2, and the drain of the second PMOS transistor MP2 is connected to the collector of the second triode Q2 to serve as a first bias voltage output terminal V1o to provide a first bias voltage for the super source follower 3.
The super source follower 3 is provided with a first bias voltage input end V1i, a second bias voltage input end V2i, a third bias voltage input end V3i, a second local voltage input end VI2 and a grounding end, the second local voltage input end VI2 is used for being connected with the local voltage output end VO to access local voltage and supply power to the super source follower 3, the first bias voltage input end V1i is connected with the first bias voltage output end V1o to access first bias voltage, the second bias voltage input end V2i is connected with the second bias voltage output end V2o to access second bias voltage, and the third bias voltage input end V3i is connected with the third bias voltage output end V3o to access third bias voltage.
The super source follower 3 comprises a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a third resistor R3, a fourth resistor R4, a first capacitor C1 and a second capacitor C2, a source of the seventh PMOS transistor MP7 is connected to a drain of the seventh NMOS transistor MN7, a drain of the seventh PMOS transistor MP7 is connected to a source of the eighth PMOS transistor MP8, a drain of the eighth PMOS transistor MP8 is connected to a source of the ninth PMOS transistor MP9, a drain of the ninth PMOS transistor MP9 is connected to a drain of the fifth NMOS transistor MN 36 5 and a gate of the seventh NMOS transistor MN7, a source of the fifth PMOS transistor MN5 is connected to a drain of the sixth NMOS transistor MN5, a source of the sixth PMOS transistor MN5, a source of the seventh NMOS transistor MN5, a source of the eighth PMOS transistor MP5 and a drain of the seventh NMOS transistor MP5 are connected between the drain of the seventh PMOS transistor MN 36363672 and a drain of the seventh NMOS transistor MP 363672, a drain of the seventh PMOS transistor MP 36363672, a drain of the seventh NMOS transistor MP 36363672 is connected to the drain of the seventh NMOS transistor MN 36363672, the other end of the first capacitor C1 is connected to one end of the third resistor R3, the other end of the third resistor R3 is connected between the drain of the ninth PMOS transistor MP9 and the gate of the seventh NMOS transistor MN7, one end of the fourth resistor R4 is also connected between the drain of the ninth PMOS transistor MP9 and the gate of the seventh NMOS transistor MN7, and the other end of the fourth resistor is grounded through the second capacitor C2.
The source of the seventh PMOS transistor MP7 is connected to the drain of the seventh NMOS transistor MN7 to serve as the second local voltage input VI2 of the super source follower 3 to provide stable local voltage for the super source follower 3, the gate of the seventh PMOS transistor MP7 is connected to the first bias voltage input V1i, the gate of the fifth NMOS transistor MN5 is connected to the second bias voltage input V2i, and the gate of the sixth NMOS transistor MN6 is connected to the third bias voltage input V3 i.
The working principle of the invention is as follows:
wherein: vBEQ3The voltage difference between the base electrode and the emitting electrode of the third triode Q3; vTFor thermal voltage, the expression is kT/q (k is Boltzmann's constant, T is temperature in Kelvin, q is unit charge amount); n is the number ratio of the second triode Q2 to the third triode Q3; r1Is the resistance of the first resistor R1; r2Is the resistance of the second resistor R2.
The local voltage generation circuit 1 adopts a cascode current mirror structure, and a cascode structure is formed by the first NMOS transistor MN1, the second NMOS transistor MN2, the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6, and the mirror ratio of the cascode structure is 1: 1.
Local voltage VOThe drain generated in the fifth PMOS transistor MP5 is connected to the drain of the fifth PMOS transistor MP5 and the source of the fourth PMOS transistor MP4, i.e. the source of the fourth PMOS transistor MP4 is connected to the local voltage VOMeanwhile, the source of the seventh PMOS transistor MP7 is also connected to the local voltage, so that the drain current I of the fourth PMOS transistor MP4 can be obtainedDMP4And drain current I of seventh PMOS transistor MP7DMP7Are equal, thereby obtaining VSGMP4＝VSGMP7And due to VSGMP4＝VSGMP1Therefore V isSGMP7＝VSGMP1Then the local voltage V can be further obtainedOComprises the following steps:
VO＝VSGMP7+VEBQ2 (2)
wherein: vSGMP7The gate-source voltage of the seventh PMOS transistor MP 7; vBEQ2The voltage difference between the base and the emitter of the second transistor Q2.
The above equation (2) is established when the seventh PMOS transistor MP7 operates in the saturation region, but when the local voltage V isODue to supply voltage VDDWhen the voltage rises, the seventh PMOS transistor MP7 enters a linear region due to the bias current of the seventh PMOS transistor MP7
And (6) determining. Due to the first bias voltage V1The gate of the seventh PMOS transistor MP7 is connected, so the gate voltage of the seventh PMOS transistor MP7
When the bias current of the seventh PMOS transistor MP7 changes very little, V1The variation of (2) is also small, so that the gate voltage of the seventh PMOS transistor MP7 can be considered approximately constant.
If the gate voltage of the seventh PMOS transistor MP7 is not changed, it follows the local voltage VOWhen the voltage of the source electrode rises, the voltage of the drain electrode of the seventh PMOS transistor MP7 will rise, and the voltage of the drain electrode of the seventh PMOS transistor MP7 will rise. When the seventh PMOS transistor MP7 enters the linear region, the gate-source voltages of the seventh PMOS transistor MP7 and the fourth PMOS transistor MP4 have a larger and larger difference, so that VSGMP7≠VSGMP4Eventually causing the reference output to change. Therefore, to ensure the local voltage VOCan stabilize local voltage V by adding negative feedback circuit composed of super source followerO。
The negative feedback circuit of the super source follower 3 consists of a seventh PMOS tube MP7, an eighth PMOS tube MP8, a ninth PMOS tube MP9 and a seventh NMOS tube MN7, so that the local voltage V is stabilizedOLoop gain A ofVComprises the following steps:
wherein: gmLow-frequency transconductance of a PMOS tube and an NMOS tube; r isoIs the output impedance of the MOS tube.
The output impedance R of the super source follower can be obtained according to the formula (3)VO-gndComprises the following steps:
wherein: gmLow-frequency transconductance of a PMOS tube and an NMOS tube; r isoIs the output impedance of the MOS tube.
The local voltage V can be seen from equation (4)OThe resistance to ground is very small, so that when the supply voltage changes, the local voltage VOSignal variation amount Δ V ofOComprises the following steps:
from equation (5), the local voltage VOChange amount of (Δ V)OFollowing VDDThe variation of (a) is very small, and the obtained reference voltage source can have a good power supply rejection ratio.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent structures made by using the contents of the present specification and the drawings can be directly or indirectly applied to other related technical fields, and are within the scope of the present invention.
Claims (3)
1. A reference voltage source having a high power supply rejection ratio, characterized by: the device comprises a local voltage generation circuit, a voltage reference core and a super source follower, wherein the local voltage generation circuit is used for generating local voltage, the voltage reference core is used for providing reference voltage, and the super source follower is used for stabilizing the local voltage generation circuit;
the local voltage generating circuit is provided with a power supply input end, a second bias voltage output end, a third bias voltage output end, a local voltage output end and a grounding end, wherein the power supply input end is connected with an external power supply, the second bias voltage output end is used for providing a second bias voltage, the third bias voltage output end is used for providing a third bias voltage, and the local voltage output end is used for outputting a local voltage;
the voltage reference core is provided with a first local voltage input end, a first bias voltage output end and a ground end, wherein the first local voltage input end is used for accessing local voltage, and the first bias voltage output end is used for providing first bias voltage;
the super source follower is provided with a first bias voltage input end, a second bias voltage input end, a third bias voltage input end, a second local voltage input end and a grounding end, wherein the first bias voltage input end is used for being connected with a first bias voltage, the second bias voltage input end is used for being connected with a second bias voltage, the third bias voltage input end is used for being connected with a third bias voltage, and the second local voltage input end is used for being connected with a local voltage;
the local voltage generating circuit comprises a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth PMOS tube, a fifth PMOS tube and a sixth PMOS tube, wherein the source electrode of the fourth PMOS tube is connected with the drain electrode of the fifth PMOS tube, the drain electrode of the fourth PMOS tube is connected with the drain electrode of the first NMOS tube, the grid electrode of the second NMOS tube and the grid electrode of the fourth NMOS tube, the source electrode of the fifth PMOS tube is connected with the source electrode of the sixth PMOS tube, the grid electrode of the fifth PMOS tube is connected with the grid electrode of the sixth PMOS tube, the drain electrode of the sixth PMOS tube and the drain electrode of the third NMOS tube, the grid electrode of the third NMOS tube is connected with the grid electrode of the first NMOS tube, the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube, the grid electrode of the second NMOS tube is also connected with the grid electrode of the fourth NMOS tube, the drain electrode of the fourth NMOS tube is connected with the source electrode of the third NMOS tube, and the source electrode of the second NMOS tube is grounded, the power input end is connected between the source electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube, the local voltage output end is connected between the source electrode of the fourth PMOS tube and the drain electrode of the fifth PMOS tube, the second bias voltage output end is connected between the grid electrode of the first NMOS tube and the grid electrode of the third NMOS tube, and the third bias voltage output end is connected between the grid electrode of the second NMOS tube and the grid electrode of the fourth NMOS tube.
2. A reference voltage source with high power supply rejection ratio as claimed in claim 1, wherein: the voltage reference core comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a first triode, a second triode, a third triode, a first resistor and a second resistor, wherein a source electrode of the first PMOS tube, a source electrode of the second PMOS tube and a source electrode of the third PMOS tube are all connected with a local voltage output end, a grid electrode of the first PMOS tube is connected with a drain electrode thereof, a grid electrode of the second PMOS tube, a grid electrode of the third PMOS tube and a grid electrode of the fourth PMOS tube, a drain electrode of the first PMOS tube is also connected with a collector electrode of the first triode, an emitter electrode of the first triode is grounded through the first resistor, a drain electrode of the second PMOS tube is connected with a collector electrode of the second triode, an emitter electrode of the second triode is grounded, a drain electrode of the third PMOS tube is connected with a collector electrode of the third triode, and an emitter electrode of the third triode is grounded through the second resistor, the base electrode of the first triode is connected with the base electrode of the second triode and the base electrode of the third triode, the source electrode of the first PMOS tube, the source electrode of the second PMOS tube and the source electrode of the third PMOS tube are connected to be used as a first local voltage input end of a voltage reference core, and the first bias voltage output end is connected between the drain electrode of the second PMOS tube and the collector electrode of the second triode.
3. A reference voltage source with high power supply rejection ratio as claimed in claim 1, wherein: the super source follower comprises a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a fifth NMOS tube, a sixth NMOS tube, a third resistor, a fourth resistor, a first capacitor and a second capacitor, wherein the source electrode of the seventh PMOS tube is connected with the drain electrode of the seventh NMOS tube, the drain electrode of the seventh PMOS tube is connected with the source electrode of the eighth PMOS tube, the drain electrode of the eighth PMOS tube is connected with the source electrode of the ninth PMOS tube, the drain electrode of the ninth PMOS tube is connected with the drain electrode of the fifth NMOS tube and the grid electrode of the seventh NMOS tube, the source electrode of the fifth NMOS tube is connected with the drain electrode of the sixth NMOS tube, the source electrode of the seventh NMOS tube, the grid electrode of the eighth PMOS tube and the grid electrode of the ninth PMOS tube are all grounded, one end of the first capacitor is connected between the source electrode of the seventh PMOS tube and the drain electrode of the seventh NMOS tube, and the other end of the first capacitor is connected with one end of the third resistor, the other end of the third resistor is connected between the drain electrode of the ninth PMOS tube and the grid electrode of the seventh NMOS tube, one end of the fourth resistor is connected between the drain electrode of the ninth PMOS tube and the grid electrode of the seventh NMOS tube, the other end of the fourth resistor is grounded through the second capacitor, all second local voltage input ends are further connected between the source electrode of the seventh PMOS tube and the drain electrode of the seventh NMOS tube, the grid electrode of the seventh PMOS tube is connected with a first bias voltage input end, the grid electrode of the fifth NMOS tube is connected with a second bias voltage input end, and the grid electrode of the sixth NMOS tube is connected with a third bias voltage input end.
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