CN111224671A

CN111224671A - Signal processing apparatus

Info

Publication number: CN111224671A
Application number: CN202010042954.4A
Authority: CN
Inventors: 高跃; 齐浩然
Original assignee: Individual
Current assignee: Shenzhen Yueyueyuebaohe Technology Co ltd
Priority date: 2020-01-15
Filing date: 2020-01-15
Publication date: 2020-06-02

Abstract

A signal processing apparatus comprising: a signal sampling module comprising a signal input unit configured to receive an input signal comprising a multi-band frequency spectrum, a signal distributor configured to distribute the input signal along a plurality of branches, and a plurality of analog-to-digital converters, wherein each branch comprises a respective one of the analog-to-digital converters to sample the input signal; and a clock distribution module configured to generate a plurality of unique and random delays for each of the branches such that delays in sampling the input signal in each of the branches by each respective analog-to-digital converter are offset from each other, wherein the plurality of unique and random delays are generated based on delay values stored in the clock distribution module.

Description

Signal processing apparatus

Technical Field

The present invention relates to signal sampling and reconstruction, and more particularly to a system for sampling and reconstruction of a multi-band signal.

Background

Spectrum sensing is a method for detecting environmental spectrum availability information, which is necessary for applications such as dynamic spectrum access. Dynamic spectrum access means that unused spectrum holes can be accessed dynamically. In order to realize broadband spectrum sensing (WSS for short) in real time, it is necessary to sample and process the broadband spectrum at the Nyquist rate. This is becoming more challenging as broadband devices continue to move toward the millimeter-wave band. Conventional wide band spectrum sensing techniques have employed narrowband radio receivers that scan each narrowband in turn across all the spectrum of interest. This implementation means that dynamic radio activity is not readily perceived. Therefore, there is a need for real-time wide-band spectrum sensing to provide reliable spectrum sensing performance.

Compressed sensing (CS for short) techniques have been introduced to achieve real-time spectrum sensing at sub-nyquist rates, which eliminates the need for the complexity and high cost of analog-to-digital converters (ADCs for short) operating at the nyquist rate. Several practical baseband processing architectures have been proposed, including random demodulators, Multi-Coset samplers (Multi-Coset samplers) and Modulated Wideband Converters (MWC) to obtain compressed signals using compressed sensing techniques. The hardware structure of the multi-coset sampler is simpler than that of a modulation broadband converter, and the structure of a filter bank reconstruction system based on an interleaving analog-to-digital converter is inherited. The multi-coset sampler samples various time-shifted versions of the baseband signal with a fraction of the nyquist rate using multiple parallel analog-to-digital converters.

The present invention is directed to realistically implementing a multi-coset sampler, which has not been realized in practice. One major challenge is to control the delay offsets (timing offsets) of each parallel analog-to-digital converter in the multi-coset sampler based on the instantaneous multi-gigahertz (multi-gigahertz) bandwidth signal. The delay skew of each parallel analog-to-digital converter should be synchronized at the nyquist period (i.e., the inverse of the nyquist frequency). For example, if the sampled spectrum has a bandwidth of 2GHz, the length of the delay skew should be around 500ps, and the error tolerance of the skew should be only a fraction of 500ps to minimize errors due to incomplete delays in the obtained samples. Proposals in the literature for implementing multi-coset samplers rely on fixed delay lines of different lengths to achieve time-shifted versions of the baseband signal. However, under some sparse signals, the fixed delay line may suffer from performance degradation. In practice, the delay needs to be reconstructed to obtain the best signal reconstruction performance. The present invention is directed to a multi-coset sampler with reconfigurable delay.

Disclosure of Invention

According to the present invention, there is provided a signal processing apparatus comprising a signal sampling module comprising a signal input unit configured to receive an input signal comprising a multi-band frequency spectrum, a signal distributor configured to distribute the input signal along a plurality of branches, and a plurality of analog-to-digital converters. Each of the branches includes a respective one of the analog-to-digital converters to sample the input signal. The signal processing apparatus further comprises a clock distribution module configured to: generating a plurality of unique and random delays for each branch such that delays in sampling the input signal in each branch at each respective analog-to-digital converter are offset from each other, wherein the plurality of unique and random delays are generated based on the delay values stored in the clock distribution module.

In a preferred embodiment, the signal processing apparatus further includes a delay value generation unit configured to: generating the delay value and updating the delay value stored in the clock distribution module.

In a preferred embodiment, the plurality of unique and random delays are a plurality of phase-shifted clock signals, each of the analog-to-digital converters comprising a clock reference signal input arranged to receive a respective one of the phase-shifted clock signals from the clock distribution module.

In a preferred embodiment, the clock distribution module includes a reference clock signal, and a delay locked loop including a plurality of identical delay gates; wherein a subset of the plurality of identical delay stages is selected as the plurality of phase shifted clock signals according to the stored delay values.

In one embodiment, the clock distribution module includes a clock distribution unit including a clock signal input, a fan-out buffer configured to divide the clock signal input into a plurality of paths, a plurality of count distributors, each of the paths including a respective one of the count distributors, wherein each of the count distributors has a counter value and an initial count value.

In one embodiment, the clock distribution unit includes a phase locked loop having a pre-divider and an in-loop divider, the phase locked loop being connected between the clock signal input and the fan-out buffer.

In one embodiment, each of the plurality of count allocators has a synchronization reset configured to synchronize with the plurality of count allocators.

In one embodiment, the clock signal input comprises a reference source selection multiplexer configured to select between a local reference oscillator and an external clock signal input to derive the clock signal.

In one embodiment, the initial count value of each of the plurality of count assigners is determined based on the stored delay value.

In one embodiment, the clock distribution module includes a master clock distribution unit and a plurality of slave clock distribution units. The reference source selection multiplexer of the master clock distribution unit is configured to select the local reference oscillator as the clock signal input of the master clock distribution unit, and the reference source selection multiplexer of each slave clock distribution unit is configured to select the external clock signal input as the clock signal input of the slave clock distribution unit. An output of the master clock distribution unit is connected to the clock signal input of each of the plurality of slave clock distribution units, and an output of each of the slave clock distribution units corresponds to an output of the clock distribution module. The initial count values of the count distributors of the master clock distribution unit are set to the same value, and the initial count value of each of the count distributors of each of the slave clock distribution units is determined based on the stored delay value.

In one embodiment, transmission lines between the fan-out buffer and each of the outputs of the clock distribution units along each of the paths are length matched.

In one embodiment, the transmission line between the signal splitter and each of the analog-to-digital converters in each of the branches is length matched.

Drawings

The invention is described below with reference to an exemplary embodiment and the accompanying drawings, in which:

fig. 1 shows a signal processing apparatus;

FIG. 2 illustrates a clock distribution module;

FIG. 3 illustrates a master-slave configuration of the clock distribution module of FIG. 2; and

fig. 4 shows another clock distribution module.

Detailed Description

Reliable and efficient sub-nyquist wide-band spectrum sensing in cooperative cognitive radio networks of y.ma, y.gao, y.c. liang and s.cui ("IEEE communications journal of selective area, volume 34, phase 10, page 2750 and 2762, 2016) and" blind multi-band signal reconstruction in m.mishali and y.c. eldar: the general theory of sub-nyquist perception of wide-band and multi-band spectra based on multi-coset models is described in the "IEEE signal processing journal", volume 57, phase 3, page 993-1009, month 3 2009 ") for compressed perception of analog signals.

Referring to the above-mentioned document, the analog signal x (t) is divided evenly into L channels, or blocks. The multi-coset sampler selects a particular sample from each block, each block containing L consecutive samples. In each block, a constant set C of length p describes the index of the p samples actually sampled in each block. Collection

Referred to as a sampling pattern (samplingpattern), where 0 ≦ c₁<…<c_p≤L-1。

For 1< i < p, the measurement sequence of the ith sample sequence is defined as

The sampling phase may be implemented by p uniform sampling sequences (uniform sampling sequences) with period 1/LT, where the ith sampling sequence is offset from the origin by c_iAnd T. Where 1/T is the Nyquist rate. Periodic non-uniform sampling of a multi-coset sampler may be achieved by implementing p parallel cosets (or branches), each coset (or branch) at a point in time (mLT + c)_iT) taking uniform samples, each parallel coset being responsible for a corresponding c_iThe value of (a) is sampled.

To reconstruct the signal, compressed sensing theory states: the randomly constructed choices for the distinct delays correspond to sets

Can be used to successfully achieve reconstruction of the input signal with high probability.

Fig. 1 shows an arrangement of a signal processing device 10 that can be used as a multi-coset sampler. The signal processing device 10 comprises an analog signal sampling module 100. The signal sampling module 100 comprises a signal input unit (not shown) for receiving an input signal. In one embodiment, the input signal is a multi-band signal, the frequency support of which is sparsely distributed over the whole frequency spectrum, i.e. the frequency is at

The spectrum of the range. The signal input unit may be an antenna or any wide band rf receiver, such as a superheterodyne receiver or a direct conversion receiver. The signal sampling module 100 receives an analog input signal and converts it to a digital signal.

The input signal is sent to a signal splitter 101, which signal splitter 101 is arranged to split the input signal along a plurality of

branches

102a, 102b …, etc. In one embodiment, the signal splitter 101 is a power splitter (power splitter) for outputting multiple identical copies of the input signal. In one embodiment, the sampling module 100 optionally includes a low noise amplifier prior to the signal splitter 101 to compensate for energy losses occurring in the signal splitter.

The output of the signal splitter 101 is transmitted along a plurality of

branches

102a, 102b … to a plurality of analog-to-digital converters (ADCs) 103a, 103b …. Each branch 102 sends an input signal to a respective one of the analog-to-digital converters 103. Optionally, the length of the transmission line of each branch 101 is matched. This may ensure that the input signal is sent to each analog to digital converter 103 at the same time. Each analog-to-digital converter 103 samples an input signal and outputs a digital signal. Each analog-to-digital converter 103 may include a clock reference signal input to receive a clock signal. The clock signal received by each analog-to-digital converter 103 determines the delay in sampling the input signal by the analog-to-digital converter.

The signal processing device 10 includes a clock distribution module 300. The clock distribution module 300 generates a plurality of unique and random delays. The clock distribution module 300 provides a unique and random delay to each branch 102. This causes the input signal in each branch 102 to be sampled by the corresponding analog-to-digital converter 103 in each branch with a delay that is offset from the delays at which the input signals are sampled by the other analog-to-digital converters. The clock distribution module 300 may include a memory that stores a delay value used to generate the unique and random delay. In one embodiment, the delay value corresponds to the aforementioned set

Changing the delay value results in a plurality of unique and random delays being changed. This enables the clock distribution block 300 to generate a reconfigurable and controllable delay.

In one embodiment, the clock distribution module 300 is the clock distribution unit 400 shown in FIG. 2. The clock distribution unit 400 comprises a clock signal input unit 410 for providing a clock distribution unit clock signal to the clock distribution unit 400. The clock distribution unit 400 also includes a fan-out buffer 430 for distributing and routing the clock distribution unit clock signal along a plurality of paths 431. This produces multiple identical copies of the clock distribution unit clock signal along each

path

431a, 431b …. The clock distribution unit 400 further comprises a plurality of

count distributors

440a, 440b …. Each

path

431a, 431b … sends a clock signal to a

respective count distributor

440a, 440b ….

Each count assigner 440 has a counter value N and an initial count value between 0 and N-1. At each rising (or falling) edge of the clock signal, the count value of each count distributor 440 is incremented by 1. If the count value is N-1, the value of the count assignor 440 returns to 0 on the next rising edge (or falling edge). Each count assigner 440 generates a rising edge of the output signal at the transition of the counter value from N-1 to 0 and a falling edge count assigner at the transition of the counter value from N/2-1 to N/2 to serve as a frequency assigner, outputting a signal having a frequency of 1/N of the input signal frequency. Each count allocator 440 may be implemented by a synchronous counter formed by a loop of D flip-flops (Dflip-flop). The counter value is determined by the number of stages of the D flip-flops and the feedback logic (i.e., the number of flip-flop states in a cycle).

In one embodiment, each count assigner 440 has the same counter value N, but a different initial count value. The clock distribution unit 400 outputs a plurality of clock signals having the same frequency, which are shifted from each other based on the difference of the initial count values.

The initial count value of each counter allocator 440 is determined according to the delay value stored in the memory 450 of the clock allocation unit 400. Each delay value c is as described by Mishali and Eldar mentioned earlier_iMay take a value between 0 and L-1. However, the counter value N may be different from L. Delay value c_iMay be multiplied by a factor of N/L to obtain an initial count value for each counter allocator 440.

In one embodiment, clock signal input 410 includes an external clock signal input 411, a local reference oscillator 412, and a reference source selection multiplexer 413. In this embodiment, a selection may be made between the local reference oscillator and the external clock signal to derive the clock distribution unit clock signal. The reference source selection multiplexer 413 is any suitable device capable of selecting between a pair of inputs and outputting the selected input to a single output line.

In one embodiment, the clock distribution unit 400 further includes a phase-locked-loop (PLL) 420. A phase locked loop 420 may be disposed between the clock signal input 410 and the fan-out buffer 430. The phase locked loop 420 includes a phase detector 421, a low pass loop filter 422, a voltage controlled oscillator 423, and an in-loop divider 424. The clock distribution unit 400 may also include a prescaler (prescaler) 415, the prescaler 415 preceding the phase locked loop 420. A prescaler and/or phase locked loop may be used as a frequency multiplier to multiply the frequency of the clock signal input and may be implemented as a synchronous counter formed by a D flip-flop loop. The frequency doubling settings of the pre-divider 415 and the in-loop divider 424 may be set individually in advance. The phase locked loop 420 allows the clock distribution module 300 to output a fractional or multiple frequency signal of the clock signal input that is phase aligned with the phase of the clock signal input.

In one embodiment, the plurality of count assigners 440 have a synchronized reset function (synchronized reset function). The synchronous reset function provides each count assignor 440 with its respective initial count value. The synchronous reset function also synchronizes the count distributor 440 to ensure that they all start counting on a common rising (or falling) edge of the clock signal. In one embodiment, the count distributor 440 is a D flip-flop ring counter with asynchronous preset and reset. The assignment of the initial value may be performed by setting a logic value to 1 at preset or reset, which initializes the state of each D flip-flop to 1 or 0, respectively. The initial value of each count splitter 440 is set by a user who has previously input a desired initial count value of each count splitter 440.

In one embodiment, each of the

paths

431a, 431b … is length matched. This is to ensure that the phase-shifted clock signal is generated based on the delay value rather than on the analog delay introduced by the mismatched transmission path lengths.

An exemplary configuration of the clock distribution unit is now described. The input signal has a bandwidth B of 2GHz and is divided into 50 channels L, the number of parallel cosets p being 4. As described by Ma et al on page 2753, the sampling rate of the analog-to-digital converter and the desired output frequency of the clock distribution unit may be set to B/L2 GHz/50 MHz 40 MHz. The reference source selection multiplexer 413 is set to select the local reference oscillator, which operates at 10 MHz; the pre-divider 415 is set to a multiplier of 10; the in-loop divider 424 is set to a multiplier of 40; fan-out buffer 430 divides the clock signal into 4 paths 430a-430 d; and, each of the count assigners 440a-440d is set to a counter value of N-100. Randomly generated delay value c₁-c₄Are 2, 32, 37 and 40, which results in 4 count assignor 430a-430d having initial count values of 4, 64, 74 and 80. The clock signal output by each count distributor 440 may be shown to be equal to c_iand/B. Thus, the clock distribution unit outputs 4 phase-shifted clock signals, which are shifted from the local reference oscillator clock signal by 1ns, 16ns, 18.5ns and 20ns, respectively.

In the embodiment shown in fig. 3, the clock distribution module 300 may be made up of a plurality of clock distribution units 400 connected together in a master-slave configuration. The master clock distribution unit 400M is connected to two slave clock distribution units 400S. The number of outputs per clock distribution unit is 4, but it should be understood that each clock distribution unit may have any number of outputs and there may be any number of slave clock distribution units connected to the master clock distribution unit 400M. The clock distribution module 400, depending on the nature of its design, allows for such configurability. This facilitates the reconfigurability of the delay because both the delay time, and the number of branches of the signal sampling module 100 that can be provided with a delay, are reconfigurable.

The clock distribution unit 400 shown in fig. 3 is generally the same as the clock distribution unit 400 described in fig. 2. However, in the present embodiment, the master clock distribution unit 400M is set such that the reference source selection multiplexer 413M selects the local reference oscillator 412M as the master clock distribution unit clock signal input; also, the reference source selection multiplexer 413S of each of the two slave clock distribution units 400S is arranged to receive the external clock signal 411S.

The initial count value of the count distributor 440M of the master clock distribution unit 400M is set to the same value so that the master clock distribution unit 400M outputs a plurality of synchronized clock signals, all of which have the same phase. Each count distributor 440S of the slave clock distribution unit 400S has an initial count value determined based on the delay value stored in the clock distribution module memory. In the embodiment shown in FIG. 3, the output of the master clock distribution unit 400M is connected to the external clock signal input of each slave clock distribution unit 400S; and the output of the master clock distribution unit 400M is a synchronization signal as part of the synchronous reset function of each of the two slave clock distribution units 400S. This ensures that the slave clock distribution unit 400S has a clock signal that is in phase with the clock signal generated by the master clock distribution unit. In the case where the clock distribution unit 400 has a fixed number of clock signal outputs, connecting a plurality of clock distribution units 400 together makes it possible to make one device scalable.

In another embodiment, the clock distribution module is a clock distribution unit 500 as shown in fig. 4, which adopts a delay-locked-loop (DLL) architecture. The clock distribution unit 500 comprises a reference source oscillator 501 which provides a clock signal to the clock distribution unit 500. The clock distribution unit 500 includes a delay chain 504, and the delay chain 504 is composed of a plurality of delay gates 505a, 505b, 505c … connected in series, which are connected in series in such a manner that an output is input. In one embodiment, the number of delay gates 505 is determined by the number of narrowband channels, L, and is greater than or equal to the number of channels, L, or a multiple of L. The output of the last delay gate in the delay chain 504 and the clock signal from the reference source oscillator 501 are also provided to the phase comparator 502. The phase comparator 502 generates an error signal based on the phase of the last delay gate output compared to the phase of the clock signal of the reference source oscillator. The error signal is provided to a loop filter 503, which loop filter 503 generates a control voltage that is provided to each delay gate 505 in the delay chain 504.

The output of each stage of the delay chain 504 (the output of each delay gate 505a, 505b …) is connected to a multiplexer 506. The multiplexer 506 outputs a subset of the signals from the plurality of delay gates 505 as the phase-shifted clock signal of the clock distribution unit 500. The selection of the signal depends on the delay value stored in the clock distribution unit. The delay step (delay step) of the output of each stage of the delay chain 504 may be calculated as the period of the reference source oscillator 501 divided by the number of delay gates.

In one embodiment, the signal processing apparatus 10 includes a random number generation unit 215. The random number generation unit 215 is configured to: generating a delay value c_iAnd updating the delay values stored in the memory of the clock distribution module 300. The random number generation unit 215 may regenerate the delay value at predetermined time intervals. This may ensure that the signal processing device may accurately sample the input signal without significant performance degradation due to the particular randomly selected delay. Such as e.j. cand, j.romberg and t.tao in "robust uncertainty principle: from the highly incomplete frequency information for the exact reconstruction of the signal "(" IEEE information treaty journal ", Vol.52, No. 2, p.489-509, p.2.2006), the delay value can be a pseudo-random number according to the standard from C! L (C-P)! A uniform random (uniform random) selected from a plurality of possible permutations.

In one embodiment, the signal processing device 10 includes a digital signal recovery module 200. The digital signal recovery module 200 is connected to the analog signal sampling module 100. In one embodiment, the digital signal recovery module 200 may reconstruct the input signal based on the outputs from the plurality of analog-to-digital converters 103. Alternatively or additionally, the digital signal recovery module 200 may determine a power spectrum (i.e., channel occupancy) based on the outputs from the plurality of analog-to-digital converters 103. In practice, the signal reconstruction error increases if the signal-to-noise ratio of the sub-nyquist samples received from the plurality of analog-to-digital converters increases. For reconstruction of the input signal, a low error margin is required for a satisfactory reconstruction of the original input signal. However, even with a high signal-to-noise ratio, the power spectrum and channel occupancy can still be accurately obtained.

In practice, only a finite length of samples can be obtained from each coset, i.e.

Wherein N is 0,1, …, N-1. Where N is the number of samples per coset for each sensing wheel round, and w_i[n]Where N-0, 1, …, N-1 represents the window function for each coset. The frequency domain representation of the analog input signal x (t) is denoted as its fourier transform x (f). Will be provided with

The N-point discrete Fourier transform (abbreviated as DFT) is recorded as

Similarly, the DFT of each coset sample can be linked to

Is represented in the frequency domain

Therein

Is a windowed version of x (t), denoted

Writing

Where w (t) is a continuous time domain representation of the original window function. Discrete time window function w_i[n]Is related to the original continuous time window function w (t) by

According to the correlation period f epsilon [0, B/L ] in the formula (2)]And relationships

The frequency domain index k is selected to be 0,1, …, N-1, and the formula (2) is recombined to

Wherein,

based on equation (4), for each k ═ 0,1, …, N-1, a single-measure-vector (SMV) model expression can be directly written,

then rewriting the equation in vector form

If N column vectors are to be added

And

are respectively stacked into a matrix

And

the linear system (5) can be represented as a multi-measurement-vector (MMV) model,

the baseband processing architecture of the multi-coset sampler is shown in fig. 1.

Measuring from compression using dictionary A

The row sparse matrix is recovered, which is a basic problem in the compressed sensing literature. In particular, for a multi-coset sampler, c should be set_iAre different integers, i.e. c_iE {0,1, …, L-1} and c for i ≠ j_i≠c_jLet dictionary a be a partial fourier basis with recovery performance guaranteed by the minimal mutual coherence between all random structure dictionaries.

The digital signal recovery module 200 recovers information about an input signal by performing a sparse recovery operation. As described by Mishali and Eldar, and Ma et al, the sparse recovery operation is to reconstruct the signal from the sub-nyquist samples using a compressed sensing technique. As mentioned above, only a limited number of samples can be obtained in practice. The sparse recovery operation comprises obtaining M samples from the set of M possible samples given in equation (1). Thus, a sample acquisition frame may include samples acquired in accordance with a given M, where M is 0,1,2, …, M-1. Each sparse recovery operation may occur after a frame is acquired, with a period of M/LT, corresponding to the frame acquisition time. Acquiring samples in frames in this manner can allow the input signal to be acquired and processed in real time. Alternatively, Q consecutive frames may be accumulated into a single frame with a frame acquisition time of QM/LT.

The signal recovery module 200 may include a plurality of frame accumulation units 211, each frame accumulation unit 211 being disposed in each branch 102. Each frame accumulation unit 211 is configured to calculate the sum of consecutive frames, which are converted into one accumulation frame as described above. This may reduce the frame generation rate to the extent that real-time signal reconstruction is practical. The number Q of accumulated frames of the frame accumulation unit 211 may be determined according to the signal processing time of the window function unit 212, the fast fourier transform unit 213, and the sparse recovery and decision module 214. If the acquisition time QM/LT of the accumulated frame is not less than the total signal processing latency (latency) of the window function unit 212, the fast fourier transform unit 213 and the sparse recovery and decision module 214, signal recovery and decision in real time can be achieved.

In one embodiment, signal recovery module 200 includes a plurality of window function units 212. Each branch 102 has a corresponding window function unit 212. Each window function unit 212 is configured to apply a window function to the discrete signal output by the corresponding analog-to-digital converter to mitigate the effects of spectral leakage, particularly energy in the wide-band spectrum that leaks from occupied channels to vacant channels. In one embodiment, window function unit 212 applies a corresponding window function to the acquired data frame. Any suitable window function may be used, such as a hanning window, a hamming window, a keisk window, and/or a chebyshev window.

The signal reconstruction module 200 comprises a plurality of Fast Fourier Transform (FFT) units 213, one fast fourier transform unit 213 for each branch 102. Each fast fourier transform unit 213 is configured to implement the required discrete fourier transform according to the theory in the cited document.

The output of each branch 102 of the signal processing apparatus 10 is provided to a sparse recovery and decision block 214. The sparse recovery and decision module 214 is configured to: during or after signal reconstruction, a determination is made as to whether a particular channel in the spectrum is occupied or clear. The input signal may be first reconstructed and then the channel occupancy (spectral support) determined from the reconstructed signal. Alternatively, the channel occupancy (i.e., spectral support) is determined prior to reconstructing the signal. In some embodiments, the random number is regenerated in each sparse recovery operation.

The above embodiments serve to provide teaching of how a multi-coset sampler can be practically implemented. In particular, embodiments described herein are intended to teach how to implement a multi-coset sampler with reconfigurable delay. Many modifications and variations of the present invention will be apparent to those skilled in the art. The present invention is not limited to the particular manner in which the offset clock signals are generated in the above description, and is intended to cover variations of how the multiple phase offset clock signals are generated, in accordance with the common general knowledge of a person skilled in the art.

Claims

1. A signal processing apparatus comprising:

a signal sampling module, the signal sampling module comprising:

a signal input unit configured to receive an input signal comprising a multi-band frequency spectrum,

a signal splitter configured to split said input signal along a plurality of branches, an

A plurality of analog-to-digital converters, wherein each of the branches includes a respective one of the analog-to-digital converters to sample the input signal; and

a clock distribution module configured to generate a plurality of unique and random delays for each of the branches such that delays in sampling the input signal in each of the branches by each respective analog-to-digital converter are offset from each other;

wherein the plurality of unique and random delays are generated based on delay values stored in the clock distribution module.

2. The apparatus according to claim 1, further comprising a delay value generation unit configured to generate the delay value and update the delay value stored in the clock distribution block.

3. The signal processing apparatus of claim 1 or 2, wherein the plurality of unique and random delays are a plurality of phase-offset clock signals;

wherein each said analogue to digital converter comprises a clock reference signal input arranged to receive a respective said phase-shifted clock signal from said clock distribution module.

4. The signal processing apparatus of claim 3, wherein the clock distribution module comprises:

a reference clock signal; and

a delay locked loop comprising a plurality of identical delay gates, wherein a subset of the plurality of identical delay stages are selected as the plurality of phase-shifted clock signals according to the stored delay values.

5. The signal processing apparatus of claim 3, wherein the clock distribution module comprises a clock distribution unit comprising:

inputting a clock signal;

a fan-out buffer configured to divide the clock signal input into a plurality of paths;

a plurality of count allocators, each of the paths including a respective one of the count allocators, wherein each of the count allocators has a counter value and an initial count value.

6. The signal processing apparatus of claim 5, wherein the clock distribution unit comprises a phase locked loop having a pre-divider and an in-loop divider, the phase locked loop being connected between the clock signal input and the fan-out buffer.

7. The signal processing apparatus of claim 5 or 6, wherein each of the plurality of count dividers has a synchronization reset configured to synchronize with the plurality of count dividers.

8. The signal processing apparatus of any of claims 5 to 7, wherein the clock signal input comprises a reference source selection multiplexer configured to select between a local reference oscillator and an external clock signal input to derive the clock distribution unit clock signal.

9. The signal processing apparatus according to any one of claims 5 to 8, wherein the initial count value of each of the plurality of count assigners is determined based on the stored delay value.

10. The signal processing apparatus of claim 8, wherein the clock distribution module includes a master clock distribution unit and a plurality of slave clock distribution units;

wherein the reference source selection multiplexer of the master clock distribution unit is configured to select the local reference oscillator as the clock signal input of the master clock distribution unit and the reference source selection multiplexer of each of the slave clock distribution units is configured to select the external clock signal input as the clock signal input of the slave clock distribution unit;

wherein an output of the master clock distribution unit is connected to the clock signal input of each of the plurality of slave clock distribution units;

wherein an output of each of the slave clock distribution units corresponds to an output of the clock distribution module;

wherein the initial count values of the count distributors of the master clock distribution unit are set to the same value, and the initial count value of each of the count distributors of each of the slave clock distribution units is determined based on the stored delay value.

11. A signal processing apparatus according to any one of claims 5 to 10, wherein the transmission lines between the fan-out buffer and each of the outputs of the clock distribution unit along each of the paths are length matched.

12. A signal processing apparatus according to any one of claims 1 to 11, wherein the transmission line between the signal divider and each of the analogue to digital converters in each of the branches is length matched.