CN111223879B - Display substrate, manufacturing method thereof and display device - Google Patents
Display substrate, manufacturing method thereof and display device Download PDFInfo
- Publication number
- CN111223879B CN111223879B CN202010128028.9A CN202010128028A CN111223879B CN 111223879 B CN111223879 B CN 111223879B CN 202010128028 A CN202010128028 A CN 202010128028A CN 111223879 B CN111223879 B CN 111223879B
- Authority
- CN
- China
- Prior art keywords
- area
- layer
- display
- conductive layer
- dummy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
- G02F1/13378—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers by treatment of the surface, e.g. embossing, rubbing or light irradiation
- G02F1/133784—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers by treatment of the surface, e.g. embossing, rubbing or light irradiation by rubbing
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
- H10D86/021—Manufacture or treatment of multiple TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/441—Interconnections, e.g. scanning lines
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
Description
技术领域technical field
本发明涉及显示技术领域,尤其涉及一种显示基板及其制造方法、显示装置。The present invention relates to the field of display technology, and in particular, to a display substrate, a manufacturing method thereof, and a display device.
背景技术Background technique
随着平板显示技术的不断进步,液晶显示器已经成功应用于笔记本、显示器、电视机等各种显示设备中。在液晶显示器生产过程中,会因设计或工艺原因导致各种不良现象的发生,这对生产的连续性和生产效率产生了很大的影响。摩擦配向不良(Rubbing Mura)就是其中之一。With the continuous advancement of flat panel display technology, liquid crystal displays have been successfully used in various display devices such as notebooks, monitors, and televisions. In the production process of liquid crystal displays, various undesirable phenomena will occur due to design or process reasons, which have a great impact on the continuity of production and production efficiency. Rubbing Mura is one of them.
液晶显示器生产过程中,需要对基板表面的PI膜(聚酰亚胺薄膜)表面进行摩擦,使其表面形成沟道,以对液晶进行配向。在摩擦配向的过程中,会因为各种原因而导致Rubbing Mura的出现。其中,基板边缘的端差损伤摩擦毛是最主要的原因之一。传统的显示产品中,包括显示区和绑定区,在所述绑定区设有COF(Chip On Flex,or,Chip On Film,常称覆晶薄膜),COF两侧的区域为空白区域,未填充任何材料,在进行摩擦配向工艺时,由于空白区域的存在,存在高度差,摩擦布在经过边框区时,会导致摩擦毛损伤,在摩擦毛损伤的地方,PI膜表面不能有效地形成沟道,从而导致Rubbing Mura的发生。In the production process of the liquid crystal display, it is necessary to rub the surface of the PI film (polyimide film) on the surface of the substrate to form a channel on the surface to align the liquid crystal. In the process of friction alignment, Rubbing Mura will appear due to various reasons. Among them, the end difference at the edge of the substrate damages the friction hair is one of the most important reasons. In traditional display products, including display area and binding area, COF (Chip On Flex, or, Chip On Film, often called chip on film) is arranged in the binding area, and the areas on both sides of COF are blank areas. No material is filled. During the rubbing alignment process, due to the existence of blank areas, there is a height difference. When the rubbing cloth passes through the frame area, the rubbing hair will be damaged. In the place where the rubbing hair is damaged, the surface of the PI film cannot be effectively formed. channel, resulting in the occurrence of Rubbing Mura.
发明内容SUMMARY OF THE INVENTION
本发明的目的在于提供一种显示基板及其制造方法、显示装置,能够减少绑定区的断差,改善摩擦毛的工作环境,极大地降低了摩擦毛的损伤几率,从而使降低RubbingMura的发生几率,提高生产效率。The purpose of the present invention is to provide a display substrate, a method for manufacturing the same, and a display device, which can reduce the break in the binding area, improve the working environment of the friction hair, greatly reduce the damage probability of the friction hair, and reduce the occurrence of Rubbing Mura. chance to improve production efficiency.
本发明所提供的技术方案如下:The technical scheme provided by the present invention is as follows:
一种显示基板,包括衬底基板,所述衬底基板包括相背设置的第一表面和第二表面,所述衬底基板包括显示区和位于所述显示区一侧的绑定区,在所述衬底基板的所述第一表面上、所述绑定区包括第一区域和第二区域,所述第一区域设有覆晶薄膜,所述第二区域为未设置所述覆晶薄膜的区域;A display substrate includes a base substrate, the base substrate includes a first surface and a second surface arranged opposite to each other, the base substrate includes a display area and a binding area on one side of the display area, On the first surface of the base substrate, the binding area includes a first area and a second area, the first area is provided with a flip-chip film, and the second area is not provided with the flip-chip the area of the film;
在所述衬底基板的第一表面上,所述第二区域设有填充结构,所述填充结构与所述覆晶薄膜在垂直于所述第一表面的方向上的高度差小于预定值。On the first surface of the base substrate, the second region is provided with a filling structure, and a height difference between the filling structure and the flip chip film in a direction perpendicular to the first surface is smaller than a predetermined value.
示例性的,所述显示基板在所述显示区内设有多个导电膜层,所述多个导电膜层包括:形成于所述衬底基板的所述第一表面上的金属导电层和ITO导电层;其中所述填充结构包括与所述显示区的导电膜层相同材料制成的伪导电膜层,且所述伪导电膜层与所述显示区内的导电膜层之间绝缘设置。Exemplarily, the display substrate is provided with a plurality of conductive film layers in the display area, and the plurality of conductive film layers include: a metal conductive layer formed on the first surface of the base substrate; ITO conductive layer; wherein the filling structure includes a dummy conductive film layer made of the same material as the conductive film layer in the display area, and the dummy conductive film layer is insulated from the conductive film layer in the display area .
示例性的,所述金属导电层包括栅线金属层;Exemplarily, the metal conductive layer includes a gate line metal layer;
所述ITO导电层包括第一ITO导电层和第二ITO导电层,所述第二ITO导电层形成于所述第一ITO导电层的远离所述第一表面的一侧;The ITO conductive layer includes a first ITO conductive layer and a second ITO conductive layer, and the second ITO conductive layer is formed on a side of the first ITO conductive layer away from the first surface;
其中,所述伪导电膜层包括:Wherein, the dummy conductive film layer includes:
与所述栅线金属层同材质且同层设置的伪栅线金属层,且所述伪栅线金属层与所述显示区的所述栅线金属层绝缘设置;a dummy gate line metal layer with the same material as the gate line metal layer and provided in the same layer, and the dummy gate line metal layer is insulated from the gate line metal layer in the display area;
和/或,与所述第二ITO导电层同材质且同层设置的伪第二ITO导电层,且所述伪第二ITO导电层与所述第二ITO导电层绝缘设置。And/or, a dummy second ITO conductive layer of the same material and disposed on the same layer as the second ITO conductive layer, and the dummy second ITO conductive layer is insulated from the second ITO conductive layer.
示例性的,所述填充结构包括第一部分和第二部分,其中,Exemplarily, the filling structure includes a first part and a second part, wherein,
所述第一部分相对所述第二部分、位于所述第二部分的靠近所述覆晶薄膜的一侧,采用所述伪第二ITO导电层形成;The first part is opposite to the second part and is located on the side of the second part close to the chip on film, and is formed by using the pseudo second ITO conductive layer;
所述第二部分采用所述伪栅线金属层和所述伪第二ITO导电层形成,且所述伪第二ITO导电层位于所述伪栅线金属层的远离所述第一表面的一侧。The second part is formed by using the dummy gate line metal layer and the dummy second ITO conductive layer, and the dummy second ITO conductive layer is located at a portion of the dummy gate line metal layer away from the first surface. side.
示例性的,所述显示基板包括采用栅线金属层形成的定位标记,在靠近所述定位标记的位置,所述填充结构采用所述伪第二ITO导电层形成。Exemplarily, the display substrate includes a positioning mark formed by using a gate line metal layer, and at a position close to the positioning mark, the filling structure is formed by using the dummy second ITO conductive layer.
示例性的,所述伪导电膜层包括平行设置的多个条状结构。Exemplarily, the dummy conductive film layer includes a plurality of strip-like structures arranged in parallel.
示例性的,所述显示基板为阵列基板。Exemplarily, the display substrate is an array substrate.
一种显示装置,包括如上所述的显示基板。A display device includes the above-mentioned display substrate.
一种显示基板的制造方法,包括:A method for manufacturing a display substrate, comprising:
提供一衬底基板,所述衬底基板包括相背设置的第一表面和第二表面,所述衬底基板包括显示区和位于所述显示区一侧的绑定区,所述绑定区包括第一区域和第二区域;A base substrate is provided, the base substrate includes a first surface and a second surface arranged opposite to each other, the base substrate includes a display area and a binding area on one side of the display area, the binding area including the first area and the second area;
在所述衬底基板的所述第一表面上,所述绑定区的所述第一区域内形成覆晶薄膜,在所述第二区域形成填充结构,所述填充结构与所述覆晶薄膜在垂直于所述第一表面的方向上的高度差小于预定值。On the first surface of the base substrate, a chip-on-chip film is formed in the first region of the bonding region, and a filling structure is formed in the second region, and the filling structure and the flip-chip are formed The height difference of the thin film in a direction perpendicular to the first surface is less than a predetermined value.
示例性的,所述方法中,所述在所述衬底基板的所述第一表面上,所述绑定区的所述第一区域内形成覆晶薄膜,在所述第二区域形成填充结构,具体包括:Exemplarily, in the method, on the first surface of the base substrate, a chip-on-chip film is formed in the first region of the bonding region, and a filler is formed in the second region structure, including:
采用同一次构图工艺在所述显示区形成栅线金属层,在所述第二区域形成伪栅线金属层;A gate line metal layer is formed in the display region by the same patterning process, and a dummy gate line metal layer is formed in the second region;
采用同一次构图工艺在所述显示区形成第二ITO导电层,在所述第二区域形成伪第二ITO导电层。The same patterning process is used to form a second ITO conductive layer in the display area, and a dummy second ITO conductive layer is formed in the second area.
本发明所带来的有益效果如下:The beneficial effects brought by the present invention are as follows:
上述方案中,在显示基板的绑定区未设置覆晶薄膜的区域处,设置了填充结构,通过该填充结构来对覆晶薄膜周围的区域进行填充,以使得显示基板的绑定区断差减小,从而改善摩擦毛的工作环境,极大地降低了摩擦毛的损伤几率,降低Rubbing Mura的发生几率,提高产品的良率。In the above solution, a filling structure is provided in the area where the chip-on-chip film is not provided in the binding area of the display substrate, and the area around the chip-on-chip film is filled with the filling structure, so that the bonding area of the display substrate is broken. Reduce the friction hair, thereby improving the working environment of the friction hair, greatly reducing the damage probability of the friction hair, reducing the occurrence probability of Rubbing Mura, and improving the yield of the product.
附图说明Description of drawings
图1表示本发明实施例提供的显示基板的绑定区的局部结构示意图;FIG. 1 is a schematic diagram showing a partial structure of a binding area of a display substrate provided by an embodiment of the present invention;
图2表示图1中B-B向的剖视结构示意图。FIG. 2 is a schematic cross-sectional structure diagram of the B-B direction in FIG. 1 .
具体实施方式Detailed ways
为使本公开实施例的目的、技术方案和优点更加清楚,下面将结合本公开实施例的附图,对本公开实施例的技术方案进行清楚、完整地描述。显然,所描述的实施例是本公开的一部分实施例,而不是全部的实施例。基于所描述的本公开的实施例,本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例,都属于本公开保护的范围。In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present disclosure.
除非另外定义,本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性,而只是用来区分不同的组成部分。同样,“一个”、“一”或者“该”等类似词语也不表示数量限制,而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同,而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接,而是可以包括电性的连接,不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系,当被描述对象的绝对位置改变后,则该相对位置关系也可能相应地改变。Unless otherwise defined, technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. As used in this disclosure, "first," "second," and similar terms do not denote any order, quantity, or importance, but are merely used to distinguish the various components. Likewise, words such as "a," "an," or "the" do not denote a limitation of quantity, but rather denote the presence of at least one. "Comprises" or "comprising" and similar words mean that the elements or things appearing before the word encompass the elements or things recited after the word and their equivalents, but do not exclude other elements or things. Words like "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "Down", "Left", "Right", etc. are only used to represent the relative positional relationship, and when the absolute position of the described object changes, the relative positional relationship may also change accordingly.
针对现有技术中显示基板绑定区的覆晶薄膜周围为空白区域,导致绑定区的断差大,在进行摩擦配向时,易导致摩擦毛损伤而产生摩擦配向不良的问题,本发明实施例提供了一种显示基板及其制造方法、显示装置,能够显示基板的绑定区断差减小,改善摩擦毛的工作环境,极大地降低了摩擦毛的损伤几率,从而使降低Rubbing Mura的发生几率,提高产品的良率。Aiming at the problem in the prior art that there is a blank area around the chip-on-film of the display substrate binding area, which leads to a large break in the binding area, and when frictional alignment is performed, it is easy to cause damage to the friction hairs and cause poor frictional alignment. For example, a display substrate, a method for manufacturing the same, and a display device are provided, which can reduce the breakage of the bonding area of the display substrate, improve the working environment of the friction hair, and greatly reduce the damage probability of the friction hair, thereby reducing the friction of the Rubbing Mura. Occurrence probability, improve product yield.
如图1所示,本发明实施例提供的显示基板包括衬底基板100,所述衬底基板100包括相背设置的第一表面和第二表面,所述衬底基板100包括显示区AA和位于所述显示区AA一侧的绑定区,在所述衬底基板100的所述第一表面上、所述绑定区包括第一区域和第二区域,所述第一区域设有覆晶薄膜(COF)200,所述第二区域为未设置所述覆晶薄膜200的区域;在所述衬底基板100的第一表面上,所述第二区域设有填充结构(dummy填充结构)300,所述填充结构300与所述覆晶薄膜200在垂直于所述第一表面的方向上的高度差小于预定值。As shown in FIG. 1 , a display substrate provided in an embodiment of the present invention includes a
上述方案中,在所述显示基板的绑定区未设置覆晶薄膜200的第二区域处,设置了填充结构300,通过该填充结构300来对覆晶薄膜200周围的空白区域进行填充,以使得显示基板的绑定区断差减小,从而改善摩擦毛的工作环境,极大地降低了摩擦毛的损伤几率,降低Rubbing Mura的发生几率,提高产品的良率。In the above solution, a
需要说明的是,所述填充结构300与所述覆晶薄膜200在垂直于所述第一表面的方向上的高度差小于预定值,其中所述预定值的取值范围并不做限定,可根据实际需要来进行设计,只要满足所述预定值小于覆晶薄膜200与第一表面之间的高度差即可。It should be noted that the height difference between the filling
在本发明所提供的实施例中,所述显示基板在所述显示区AA内设有多个导电膜层,所述多个导电膜层包括:形成于所述衬底基板100的所述第一表面上的金属导电层和ITO导电层等,例如,以所述显示基板为阵列基板为例,所述金属导电层可以包括栅线金属层、栅极金属层(栅极金属层与栅线金属层可以同材料且同层设置)、数据线金属层等;所述ITO导电层可以包括第一ITO导电层(1ITO)、第二ITO导电层(2ITO)等,所述第二ITO导电层形成于所述第一ITO导电层的远离所述第一表面的一侧,例如,以所述显示基板为阵列基板为例,所述第一ITO导电层可以是像素电极层,所述第二ITO电极层可以是COM信号线层等。其中,所述填充结构300可以包括采用与所述显示区AA的导电膜层相同材质制成的伪导电膜层(dummy导电膜层),该伪导电膜层与显示区AA内的导电膜层之间绝缘设置。In the embodiment provided by the present invention, the display substrate is provided with a plurality of conductive film layers in the display area AA, and the plurality of conductive film layers include: the first layer formed on the
采用上述方案,所述填充结构300可以是采用与显示区AA内的金属导电层、或者ITO导电层来形成,这样,可以在制作显示区AA内的金属导电层或ITO导电层的同时,采用同一次构图工艺来形成所述填充结构300。Using the above solution, the filling
需要说明的是,在实际应用中,所述填充结构300也可以是采用其他材料来制成,对此不做限定,例如,也可以是采用绝缘层材料等来形成。但是,采用金属导电层或ITO导电层材料,相较于采用其他材料来说,图案化工艺更简单。It should be noted that, in practical applications, the filling
此外,在一种实施例性的实施例中,所述伪导电膜层包括:In addition, in an exemplary embodiment, the dummy conductive film layer includes:
与所述栅线金属层同材质且同层设置的伪栅线金属层(dummy gate层)310,且所述伪栅线金属层310与所述显示区AA的所述栅线金属层绝缘设置;A dummy gate metal layer (dummy gate layer) 310 with the same material and same layer as the gate line metal layer, and the dummy
和/或,与所述第二ITO导电层同材质且同层设置的伪第二ITO导电层(dummy 2ITO层)320,且所述伪第二ITO导电层320与所述第二ITO导电层绝缘设置。And/or, a dummy second ITO conductive layer (dummy 2ITO layer) 320 with the same material and same layer as the second ITO conductive layer, and the dummy second ITO
采用上述方案,所述填充结构300的伪导电膜层可以是与显示区AA的栅线同层且同材质的伪栅线金属层310,也可以是与所述第二ITO导电层同层且同材质的伪第二ITO导电层320,且可以是伪栅线金属层310和伪第二ITO导电层320中的一个或两个来构成所述填充结构300。With the above solution, the dummy conductive film layer of the filling
采用上述方案,以阵列基板为例,由于显示区AA的栅线金属层和第二ITO导电层的厚度之和与覆晶薄膜200的厚度更为接近,因此,在绑定区的第二区域,优选的,采用栅线金属层和第二ITO导电层来形成所述填充结构300,这样,填充结构300与覆晶薄膜200的高度差值较小,工艺和结构更为简单。此外,需要说明的是,该填充结构300中的伪导电膜层可以仅起到填充作用,与显示区和绑定区的其他导电膜层均绝缘设置,不进行电连接。Using the above solution, taking the array substrate as an example, since the sum of the thicknesses of the gate line metal layer and the second ITO conductive layer in the display area AA is closer to the thickness of the chip on
当然可以理解的是,在实际应用中,针对不同类型和型号的显示产品,也可以根据显示区AA的各膜层厚度等,来采用合适的膜层材料形成所述填充结构300,在此不做限定。Of course, it can be understood that, in practical applications, for different types and models of display products, the filling
此外,在本发明一种示例性的实施例中,如图1和图2所示,所述填充结构300包括第一部分300a和第二部分300b,其中,所述第一部分300a相对所述第二部分300b,位于靠近所述覆晶薄膜200的一侧,采用所述伪第二ITO导电层320形成;所述第二部分300b采用所述伪栅线金属层310和所述伪第二ITO导电层320形成,且所述伪第二ITO导电层320位于所述伪栅线金属层310的远离所述第一表面的一侧。In addition, in an exemplary embodiment of the present invention, as shown in FIG. 1 and FIG. 2 , the filling
采用上述方案,由于所述覆晶薄膜200所在的区域或靠近覆晶薄膜200的位置,存在由所述栅线金属层所形成的结构,在靠近所述覆晶薄膜200的位置仅采用伪第二ITO导电层320来填充,在远离所述覆晶薄膜200的位置采用伪栅线金属层310和所述伪第二ITO导电层320来填充。With the above solution, since the area where the chip on
需要说明的是,上述靠近所述覆晶薄膜200的位置和所述远离所述覆晶薄膜的位置,可根据实际应用来限定该位置,对此并不进行限定。It should be noted that, the positions close to the chip on
在一种示例性的,所述显示基板包括采用栅线金属层形成的定位标记201,在靠近所述定位标记201的位置,所述填充结构300采用所述伪第二ITO导电层320形成。In an example, the display substrate includes an
采用上述方案,所述显示基板包括用于绑定定位的定位标记201,采用栅线金属层形成,因此,为了避免所述伪栅线金属层310距离这部分栅线金属层太近而造成不良影响,例如,距离所述定位标记太近,导致不易识别所述定位标记等,在靠近所述定位标记的位置仅采用伪第二ITO导电层320来填充,在远离所述定位标记的位置采用伪栅线金属层310和所述伪第二ITO导电层320来填充。With the above solution, the display substrate includes the
此外,如图1和图2所示,在一种示例性的实施例中,所述伪导电膜层包括平行设置的多个条状结构。In addition, as shown in FIG. 1 and FIG. 2 , in an exemplary embodiment, the dummy conductive film layer includes a plurality of strip-like structures arranged in parallel.
采用上述方案,所述伪导电膜层为条形光栅结构,这是由于当所述伪导电膜层采用金属层来形成时,金属层为不透光材料,影响透光率,将伪导电膜层设计为条形,可增加透光率。当然可以理解的是,当所述伪导电膜层为透光材料时,例如仅由ITO导电层形成时,也可以不是条形结构。对此不限定。With the above solution, the dummy conductive film layer has a stripe grating structure. This is because when the dummy conductive film layer is formed by a metal layer, the metal layer is an opaque material, which affects the light transmittance. The layers are designed in strips to increase light transmittance. Of course, it can be understood that when the dummy conductive film layer is a light-transmitting material, for example, it is only formed of an ITO conductive layer, it may not be a strip-shaped structure. This is not limited.
此外,需要说明的是,本发明实施例提供的显示基板可以是阵列基板,也可以是其他类型基板,对此并不限定。In addition, it should be noted that the display substrate provided in the embodiment of the present invention may be an array substrate or other types of substrates, which is not limited thereto.
本发明实施例中还提供了一种显示装置,包括本发明实施例提供的显示基板。Embodiments of the present invention further provide a display device, including the display substrate provided by the embodiments of the present invention.
本发明实施例中还提供了一种显示基板的制造方法,用于制造本发明实施例提供的显示基板,所述方法包括如下步骤:The embodiment of the present invention also provides a method for manufacturing a display substrate, which is used for manufacturing the display substrate provided by the embodiment of the present invention, and the method includes the following steps:
步骤S1、提供一衬底基板100,所述衬底基板100包括相背设置的第一表面和第二表面,所述衬底基板100包括显示区AA和位于所述显示区AA一侧的绑定区,所述绑定区包括第一区域和第二区域;Step S1, providing a
步骤S2、在所述衬底基板100的所述第一表面上,所述绑定区的所述第一区域内形成覆晶薄膜200,在所述第二区域形成填充结构300,所述填充结构300与所述覆晶薄膜200在垂直于所述第一表面的方向上的高度差小于预定值。Step S2, on the first surface of the
在所述方法中,所述步骤S2具体包括:In the method, the step S2 specifically includes:
采用同一次构图工艺在所述显示区AA形成导电膜层,在所述第二区域形成伪导电膜层。The same patterning process is used to form a conductive film layer in the display area AA, and a dummy conductive film layer is formed in the second area.
具体的,所述步骤S2包括:Specifically, the step S2 includes:
步骤S21、采用同一次构图工艺在所述显示区AA形成栅线金属层,在所述第二区域形成伪栅线金属层310;Step S21, using the same patterning process to form a gate line metal layer in the display area AA, and form a dummy gate
步骤S22、采用同一次构图工艺在所述显示区AA形成第二ITO导电层,在所述第二区域形成伪第二ITO导电层320。Step S22 , using the same patterning process to form a second ITO conductive layer in the display area AA, and form a dummy second ITO
有以下几点需要说明:The following points need to be noted:
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构,其他结构可参考通常设计。(1) The accompanying drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to general designs.
(2)为了清晰起见,在用于描述本公开的实施例的附图中,层或区域的厚度被放大或缩小,即这些附图并非按照实际的比例绘制。可以理解,当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时,该元件可以“直接”位于另一元件“上”或“下”或者可以存在中间元件。(2) In the drawings for describing the embodiments of the present disclosure, the thicknesses of layers or regions are exaggerated or reduced for clarity, ie, the drawings are not drawn on actual scale. It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element, or Intermediate elements may be present.
(3)在不冲突的情况下,本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。(3) The embodiments of the present disclosure and the features in the embodiments may be combined with each other to obtain new embodiments without conflict.
以上所述,仅为本公开的具体实施方式,但本公开的保护范围并不局限于此,本公开的保护范围应以权利要求的保护范围为准。The above descriptions are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be subject to the protection scope of the claims.
Claims (6)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202010128028.9A CN111223879B (en) | 2020-02-28 | 2020-02-28 | Display substrate, manufacturing method thereof and display device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202010128028.9A CN111223879B (en) | 2020-02-28 | 2020-02-28 | Display substrate, manufacturing method thereof and display device |
Publications (2)
Publication Number | Publication Date |
---|---|
CN111223879A CN111223879A (en) | 2020-06-02 |
CN111223879B true CN111223879B (en) | 2022-10-18 |
Family
ID=70828395
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202010128028.9A Active CN111223879B (en) | 2020-02-28 | 2020-02-28 | Display substrate, manufacturing method thereof and display device |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN111223879B (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113745287B (en) * | 2021-08-16 | 2023-07-28 | 深圳市华星光电半导体显示技术有限公司 | Display device and method for manufacturing the same |
CN114171665B (en) * | 2021-12-09 | 2024-07-16 | 惠州华星光电显示有限公司 | Display panel and preparation method thereof |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN203084394U (en) * | 2013-02-20 | 2013-07-24 | 北京京东方光电科技有限公司 | Array substrate and liquid crystal display |
CN103579219A (en) * | 2012-07-27 | 2014-02-12 | 北京京东方光电科技有限公司 | Planar array substrate, sensor and manufacturing method of planar array substrate |
CN105304649A (en) * | 2015-10-28 | 2016-02-03 | 京东方科技集团股份有限公司 | Array substrate and making method thereof, display panel and display device |
CN106653775A (en) * | 2017-01-04 | 2017-05-10 | 京东方科技集团股份有限公司 | Array substrate, manufacturing process thereof, display panel and display device |
CN206248977U (en) * | 2016-12-16 | 2017-06-13 | 信利半导体有限公司 | A kind of TFT substrate and LCD boxes |
CN109407412A (en) * | 2018-12-18 | 2019-03-01 | 信利半导体有限公司 | Friction matching substrate |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106154613B (en) * | 2016-06-30 | 2018-09-18 | 京东方科技集团股份有限公司 | Display base plate and preparation method thereof, display device |
-
2020
- 2020-02-28 CN CN202010128028.9A patent/CN111223879B/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103579219A (en) * | 2012-07-27 | 2014-02-12 | 北京京东方光电科技有限公司 | Planar array substrate, sensor and manufacturing method of planar array substrate |
CN203084394U (en) * | 2013-02-20 | 2013-07-24 | 北京京东方光电科技有限公司 | Array substrate and liquid crystal display |
CN105304649A (en) * | 2015-10-28 | 2016-02-03 | 京东方科技集团股份有限公司 | Array substrate and making method thereof, display panel and display device |
CN206248977U (en) * | 2016-12-16 | 2017-06-13 | 信利半导体有限公司 | A kind of TFT substrate and LCD boxes |
CN106653775A (en) * | 2017-01-04 | 2017-05-10 | 京东方科技集团股份有限公司 | Array substrate, manufacturing process thereof, display panel and display device |
CN109407412A (en) * | 2018-12-18 | 2019-03-01 | 信利半导体有限公司 | Friction matching substrate |
Also Published As
Publication number | Publication date |
---|---|
CN111223879A (en) | 2020-06-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102629606B (en) | Array substrate and preparation method thereof and display device | |
US20170059919A1 (en) | Display Motherboard and Manufacturing Method Thereof, Display Panel and Display Device | |
US9465256B2 (en) | Liquid crystal display panel and manufacturing method thereof | |
US20160372490A1 (en) | Array substrate and manufacturing method thereof, and display panel | |
KR101799937B1 (en) | Method of fabricating lightweight and thin liquid crystal display device | |
CN206479745U (en) | A kind of array base palte and display device | |
CN105093729B (en) | Array base palte and preparation method thereof, display device | |
CN111223879B (en) | Display substrate, manufacturing method thereof and display device | |
CN103346160B (en) | Array base palte and preparation method thereof, display unit | |
CN110286510B (en) | Multi-signal HVA mode liquid crystal display panel | |
CN104280963A (en) | Array substrate, manufacturing method of array substrate, and display device | |
CN103345095A (en) | TFT-LCD array substrate and display device | |
WO2022141519A1 (en) | Liquid crystal display panel, fabrication method therefor, and display device | |
JP2018508031A (en) | Array substrate and its disconnection repair method | |
WO2015180302A1 (en) | Array substrate and manufacturing method thereof, and display device | |
CN107170757A (en) | A kind of array base palte and preparation method thereof | |
CN110854139B (en) | TFT array substrate, preparation method thereof and display panel thereof | |
US20060082716A1 (en) | Method of producing liquid crystal cells on a silicon substrate and corresponding cells | |
US11101230B2 (en) | Array substrate and chip bonding method | |
CN103633101B (en) | A kind of array structure and preparation method thereof, array base palte and display unit | |
CN103489875B (en) | The manufacture method of array base palte, display unit and array base palte | |
CN105425495A (en) | Array substrate, fabrication method of array substrate, display panel and display device | |
CN105068327A (en) | Array substrate and manufacturing method thereof, display panel and display device | |
WO2019178904A1 (en) | Array substrate and preparation method | |
CN111338136B (en) | Array substrate and display device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |