CN111212285A - Hardware video coding system and control method of hardware video coding system - Google Patents
Hardware video coding system and control method of hardware video coding system Download PDFInfo
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- H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
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- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
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Abstract
The invention provides a hardware video coding system and a control method of the hardware video coding system, wherein the system comprises the following steps: the device comprises an image collector, an image buffer, an encoder, a code stream buffer and a code stream transmitter; the image collector is used for collecting image data and transmitting the image data to the image buffer; the image buffer is used for receiving the image data as first buffer data and transmitting the first buffer data to the encoder when the first buffer data reaches a first buffer amount; the encoder is used for encoding the received first cache data to obtain encoded data and transmitting the encoded data to the code stream cache; the code stream buffer is used for receiving the coded data as second buffer data and transmitting the second buffer data to the code stream transmitter when the second buffer data reaches a second buffer amount; the first buffer amount and/or the second buffer amount are/is smaller than the data amount of one frame of image in the image data, and the time delay of image transmission in a hardware video coding system is reduced.
Description
Technical Field
The present invention relates to the field of hardware video coding, and in particular, to a hardware video coding system and a control method of the hardware video coding system.
Background
Video compression coding and transmission are widely used in various practical scenarios. In some specific video application scenarios, there are strict requirements on the delay of the video coding system, such as: remote medical image transmission, unmanned aerial vehicle image shooting and control, remote video communication. With the development of chip technology, video compression is mostly realized by a hardware encoder in a chip so as to meet the requirements of larger image size and smaller power consumption.
In a hardware video coding system in the prior art, an external memory is mostly used for caching, and a code stream is coded and transmitted according to an image frame mode. In this case, the delay of image transmission in the coding system is 2 frames of image time. If the video is 30 frames per second, the delay is usually 33.33 × 2 to 66.66ms, and the delay time of the image transmission in the hardware video coding system in the prior art is too long to meet the requirement.
Therefore, reducing the delay of image transmission in a hardware video coding system is a problem to be solved in the art.
Disclosure of Invention
The invention provides a hardware video coding system and a control method of the hardware video coding system, which are used for reducing the transmission delay of an image in the hardware video coding system.
In order to solve the above-mentioned problems, as an aspect of the present invention, there is provided a hardware video encoding system including: the device comprises an image collector, an image buffer, an encoder, a code stream buffer and a code stream transmitter;
the image collector is used for collecting image data and transmitting the image data to the image buffer;
the image buffer is used for receiving the image data as first buffer data and transmitting the first buffer data to the encoder when the first buffer data reaches a first buffer amount;
the encoder is used for encoding the received first cache data to obtain encoded data and transmitting the encoded data to the code stream cache;
the code stream buffer is used for receiving the coded data as second buffer data and transmitting the second buffer data to the code stream transmitter when the second buffer data reaches a second buffer amount;
and the first buffer amount and/or the second buffer amount are/is smaller than the data amount of one frame of image in the image data.
Optionally, the second buffer amount is 0, and the code stream buffer immediately transmits the second buffer data to the code stream transmitter after receiving the encoded data.
Optionally, the code stream buffer transmits the second buffer data to the code stream transmitter through the stream mode interface.
Optionally, the stream mode interface adopts a double-ended handshake interface protocol.
Optionally, the image collector is further configured to: the image data is converted into a format corresponding to the encoder before being transmitted to the image buffer.
Optionally, one frame of image in the image data is composed of M lines of data;
the first buffer amount is N rows of data, wherein N is less than M.
Optionally, N is more than or equal to 512 and more than or equal to 16.
The present application further provides a method for controlling a hardware video coding system, including:
the image collector receives the image data and transmits the image data to the image buffer;
the image buffer receives the image data as first buffer data, and transmits the first buffer data to the encoder when the first buffer data reaches a first buffer amount;
the encoder encodes the received first cache data to obtain encoded data, and transmits the encoded data to the code stream cache;
the code stream buffer receives the coded data as second buffer data, and transmits the second buffer data to the code stream transmitter when the second buffer data reaches a second buffer amount;
and the first buffer amount and/or the second buffer amount are/is smaller than the data amount of one frame of image in the image data.
Optionally, the second buffer amount is 0, and the code stream buffer immediately transmits the second buffer data to the code stream transmitter after receiving the encoded data.
Optionally, the code stream buffer transmits the second buffer data to the code stream transmitter through the stream mode interface.
Optionally, the stream mode interface adopts a double-ended handshake interface protocol.
Optionally, before the image data is transmitted to the image buffer by the image collector, the method further includes: the image collector converts the image data into a format corresponding to the encoder.
Optionally, one frame of image in the image data is composed of M lines of data;
the first buffer amount is N rows of data, wherein N is less than M.
Optionally, N is more than or equal to 512 and more than or equal to 16.
The invention provides a hardware video coding system and a control method of the hardware video coding system.
Drawings
FIG. 1 is a block diagram of a hardware video coding system according to an embodiment of the present invention;
fig. 2 is a flowchart of a method for controlling a hardware video coding system according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the specific embodiments of the present invention and the accompanying drawings. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, apparatus, article, or article that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or article.
In the video coding system in the prior art, the image data is collected by the image data collection module and then stored in the external memory according to frames, that is, the buffer memory in the external memory is the data amount of at least 1 frame of image, then the external memory sends the buffered data to the video encoder, that is, the video encoder can encode the image data only by waiting for the external memory to complete the buffer memory of the frame of image, so that the delay of one frame is caused, when the encoder completes the encoding of one frame of image, the encoded image data is transmitted back to the external memory, and then the external memory sends the encoded image data to the sender, the external memory needs to buffer the frame of data fed back first, that is, the sender needs to wait for the buffer memory of the 1 frame of image to complete, that is, the delay of one frame of image is caused, and the reason for delaying the two frames of data is the time consumed by buffering data twice, that is, the delay of the conventional hardware video coding system is the read/write time of 2 frames of images, and in case of 30 frames per second, the delay is usually 33.33 × 2 — 66.66 ms. Such a long delay cannot be allowed in many scenarios.
To this end, the present application provides a hardware video coding system, please refer to fig. 1, the system provided by the present application includes: the system comprises an image collector 10, an image buffer 20, an encoder 30, a code stream buffer 40 and a code stream transmitter 50; the image collector is used for collecting image data and transmitting the image data to the image buffer; the image buffer is used for receiving the image data as first buffer data and transmitting the first buffer data to the encoder when the first buffer data reaches a first buffer amount; the encoder is used for encoding the received first cache data to obtain encoded data and transmitting the encoded data to the code stream cache; the code stream buffer is used for receiving the coded data as second buffer data and transmitting the second buffer data to the code stream transmitter when the second buffer data reaches a second buffer amount; wherein the first buffer amount and/or the second buffer amount is smaller than the data amount of one frame of image in the image data.
Specifically, in the present application, one or both of the first buffer amount and the second buffer amount are smaller than the data amount of one frame of image in the image, so that the delay of image transmission in the hardware video coding system can be reduced. For example: now, to encode a target video, the image collector 10 receives the target video, the target video is composed of multiple frames of images, the data of each frame of image in the target video is image data, the image data is sequentially and continuously transmitted to the image buffer 20 according to the sequence of the images in the video, a first buffer amount preset by the image buffer 20 is smaller than the data amount of one frame of image, for example, the data amount of a half frame of image, at this time, the image collector transmits the half frame of image to the image buffer 20 at one time as the first buffer data, therefore, the delay generated in the hardware video encoding system by the image at this time is the transmission time of the half frame of image, then the image buffer 20 sends the buffered image data to the image encoder for encoding, the image buffer 20 then continues to buffer the remaining image data, then the image encoder 30 encodes the received image data to obtain encoded data, and meanwhile, coding and transmitting to the code stream buffer 40 at the same time, wherein no delay exists in the process, but the code stream transmitter does not work at the moment, the waiting time is equal to the transmission time of the second buffer amount, namely the code stream buffer is waited to buffer the data of the second buffer amount, and then the code stream buffer 40 transmits the second buffer data to the code stream transmitter. The code stream transmitter can be used for transmitting the encoded data to a specified position. The above steps are one step in the whole video encoding and transmitting process, and then the above steps are repeated to encode and transmit the whole target video to the code stream transmitter 50. As can be seen from the above analysis, the delay of the hardware video coding system proposed in the present application depends on the first buffer amount and the second buffer amount, and therefore, the present application sets the first buffer amount to be smaller than the data amount of one frame of image in the image data, or sets the second buffer amount to be smaller than the data amount of one frame of image in the image data, so as to reduce the delay of the image in the hardware video coding system, or adopts the above two setting manners simultaneously, and optionally, the data amounts of the first buffer amount and the second buffer amount and the data amount of two frames of image in the image data are smaller.
Preferably, in some optional embodiments, the second buffer amount is 0, and the code stream buffer transmits the second buffer data to the code stream transmitter immediately after receiving the encoded data.
Specifically, in this embodiment, once the code stream buffer 40 receives the encoded data, the encoded data is immediately transmitted to the code stream transmitter 50, so that the delay can be further reduced, it should be noted that although the second storage amount of the code stream buffer can be set to 0, it is necessary to ensure that the code stream buffer has a certain storage capacity, for example, the storage capacity of the code stream buffer 40 is set to 1KB-1MB, which is because the bandwidth of the encoder is stable for a long time, but the bandwidth fluctuates in a short time, and the bandwidth of the code stream buffer 40 when transmitting to the code stream transmitter 50 is substantially constant, and when the data amount instantaneously transmitted by the encoder exceeds the data amount transmitted from the code stream buffer 40 to the code stream transmitter 50, the code stream buffer 40 needs to temporarily buffer the encoded data to prevent data loss or overflow.
Preferably, in some optional embodiments, the codestream buffer 40 transmits the second buffered data to the codestream transmitter 50 through a streaming mode interface. Specifically, the hardware modules running on the code stream buffer 40 and the code stream transmitter 50 both adopt a stream mode interface, and the two are in communication connection with each other through the interface, and the stream mode interface can play a role in rate adaptation. Specifically, the stream mode interface adopts a double-end handshake interface protocol, and the double-end handshake interface protocol generally has the following 3 groups of signals: data, data valid flag, data response.
Preferably, in some optional embodiments, the image collector is further configured to: converting the image data into a format corresponding to the encoder before transmitting the image data to the image buffer. Thereby being matched with the encoder and preventing the code messy in the encoding process.
Preferably, in some optional embodiments, one frame of image in the image data is composed of M lines of data; the first buffer amount is N rows of data, wherein N is smaller than M. The number of lines of an image of one frame is fixed for an image of a certain size. Such as: for a 720P image, one row has 1280 pixel points, and one frame has 720 rows of data; for a 1080P image, one row has 1920 pixels, and one frame has 1080 lines of data, and optionally, 64 is larger than or equal to N is larger than or equal to 16. The values of the compression algorithms N are different according to different video coding. Such as: algorithms such as VP8, H.264, AV1 and the like need to buffer 16 lines of data; algorithms such as VP9, H.265, AV2 and the like need to buffer 16-64 rows of data. In this process, image grabber 10 transfers image data to image buffer 20 line by line, 1 line of data at a time.
To better illustrate the beneficial effects of the present application, another embodiment is presented below for specific description.
With continued reference to fig. 1, in this embodiment, image data is entered from the image collector and stored directly into the memory by line; this results in a delay of several line data, typically between 200us and 400 us.
After the image line buffer has obtained enough lines, that is, the buffered data reaches the first buffer amount, the encoder, for example: the hardware video encoder starts encoding operation and transmits the encoded data to the code stream buffer in the form of output code stream; this results in a data delay of several bytes, typically 100us to 300 us. After receiving the code stream as the second cache data, the code stream buffer can directly transmit the second cache data to the code stream transmitter through the stream mode interface.
The system structure in the application is divided as follows:
the image collector can be used for receiving image input and converting image data into a format required by the encoder; an image buffer may be used to buffer image data by row. The encoder is used for reading the image data from the image line buffer for compression encoding after waiting for the image line buffer to buffer enough lines, namely after storing the first buffer amount; and the code stream buffer can be used for storing a small amount of data. The storage space needs several bytes to several million bytes, and the specific size is determined according to the bandwidth of the post-stage code stream transmitter and the characteristics of the preceding-stage hardware video encoder; a code stream transmitter: and acquiring code stream data from the code stream buffer through the stream mode interface and transmitting the code stream data.
Video coding systems in the prior art typically buffer, encode, and transmit the video frames. A frame buffer is arranged between the image acquisition and the hardware video encoder, so that the delay of a frame time is caused; there is a frame buffer between the hardware video encoder and the code stream sending module, again resulting in a delay of one frame time.
The hardware video coding system of the application changes the mode of buffering according to image frames, coding and transmission into the following modes: the image memory between the image collector and the encoder only has a plurality of lines of cache (less than the data amount of a frame image), which only causes the time delay of 200 us-400 us; only digital node buffer (less than data amount of one frame image) is arranged between the encoder and the code stream transmitter, and only 100-300 us of delay is caused.
According to the method and the device, the data caching mode among the video processing modules is changed, so that the transmission delay of the image in the video coding system is greatly reduced, and better user experience is achieved.
Referring to fig. 2, the method for controlling a hardware video coding system includes:
the image data is collected by the image collector and transmitted to the image buffer;
the image buffer receives the image data as first buffer data, and transmits the first buffer data to the encoder when the first buffer data reaches a first buffer amount;
the encoder encodes the received first cache data to obtain encoded data, and transmits the encoded data to the code stream cache;
the code stream buffer receives the coded data as second buffer data, and transmits the second buffer data to the code stream transmitter when the second buffer data reaches a second buffer amount;
and the first buffer amount and/or the second buffer amount are/is smaller than the data amount of one frame of image in the image data.
Optionally, the second buffer amount is 0, and the code stream buffer immediately transmits the second buffer data to the code stream transmitter after receiving the encoded data.
Optionally, the code stream buffer transmits the second buffer data to the code stream transmitter through the stream mode interface.
Optionally, the stream mode interface adopts a double-ended handshake interface protocol.
Optionally, before the image data is transmitted to the image buffer by the image collector, the method further includes: the image collector converts the image data into a format corresponding to the encoder.
Optionally, one frame of image in the image data is composed of M lines of data;
the first buffer amount is N rows of data, wherein N is less than M.
Optionally, N is more than or equal to 64 and more than or equal to 16.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (14)
1. A hardware video coding system, comprising: the device comprises an image collector, an image buffer, an encoder, a code stream buffer and a code stream transmitter;
the image collector is used for collecting image data and transmitting the image data to the image buffer;
the image buffer is used for receiving the image data as first buffer data and transmitting the first buffer data to the encoder when the first buffer data reaches a first buffer amount;
the encoder is used for encoding the received first cache data to obtain encoded data and transmitting the encoded data to the code stream cache;
the code stream buffer is used for receiving the coded data as second buffer data and transmitting the second buffer data to the code stream transmitter when the second buffer data reaches a second buffer amount;
wherein the first buffer amount and/or the second buffer amount is smaller than the data amount of one frame of image in the image data.
2. The hardware video coding system of claim 1,
and the second buffer memory is 0, and the code stream buffer transmits the second buffer data to the code stream transmitter immediately after receiving the coded data.
3. The hardware video coding system of claim 2,
and the code stream buffer transmits second buffer data to the code stream transmitter through a stream mode interface.
4. The hardware video coding system of claim 3,
the stream mode interface adopts a double-end handshake interface protocol.
5. The hardware video coding system of any of claims 1-4, wherein the image collector is further configured to: converting the image data into a format corresponding to the encoder before transmitting the image data to the image buffer.
6. Hardware video coding system according to any of claims 1 to 5,
one frame of image in the image data consists of M lines of data;
the first buffer amount is N rows of data, wherein N is smaller than M.
7. The hardware video coding system of claim 6,
512≥N≥16。
8. a method for controlling a hardware video coding system, comprising:
the image collector receives the image data and transmits the image data to the image buffer;
the image buffer receives the image data as first buffer data, and transmits the first buffer data to the encoder when the first buffer data reaches a first buffer amount;
the encoder encodes the received first cache data to obtain encoded data, and transmits the encoded data to the code stream cache;
the code stream buffer receives the coded data as second buffer data, and transmits the second buffer data to a code stream transmitter when the second buffer data reaches a second buffer amount;
wherein the first buffer amount and/or the second buffer amount is smaller than the data amount of one frame of image in the image data.
9. The method of claim 8,
and the second buffer memory is 0, and the code stream buffer transmits the second buffer data to the code stream transmitter immediately after receiving the coded data.
10. The method of claim 9,
and the code stream buffer transmits second buffer data to the code stream transmitter through a stream mode interface.
11. The method of claim 10,
the stream mode interface adopts a double-end handshake interface protocol.
12. The method for controlling a hardware video coding system according to any one of claims 8 to 12, wherein before the image data is transmitted to the image buffer by the image collector, the method further comprises: and the image collector converts the image data into a format corresponding to the encoder.
13. The method for controlling a hardware video coding system according to any one of claims 8 to 13,
one frame of image in the image data consists of M lines of data;
the first buffer amount is N rows of data, wherein N is smaller than M.
14. The method of claim 13,
512≥N≥16。
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Application publication date: 20200529 |