CN111211105A

CN111211105A - Redistribution layer structure and manufacturing method thereof

Info

Publication number: CN111211105A
Application number: CN201811396631.4A
Authority: CN
Inventors: 朱彦瑞; 吴金能; 周信宏; 林俊宏
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 2018-11-22
Filing date: 2018-11-22
Publication date: 2020-05-29

Abstract

The invention provides a rewiring layer structure, comprising: the semiconductor device includes a substrate, a pad, a dielectric layer, a self-aligned structure, a conductive layer and a conductive connector. The pad is disposed on the substrate. The dielectric layer is disposed on the substrate and exposes a portion of the pad. The self-aligned structure is disposed on the dielectric layer. The conductive layer extends from the pad and conformally covers the surface of the self-aligned structure. The conductive connection is disposed on the self-aligned structure. A method of manufacturing a redistribution layer structure is also provided.

Description

Redistribution layer structure and method for manufacturing the same

Technical Field

The present invention relates to semiconductor structures and methods of fabricating the same, and more particularly, to a redistribution layer structure and a method of fabricating the same.

Background

In recent years, the semiconductor industry has grown rapidly due to the increasing integration of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). This increase in integration is mostly due to the continuous reduction of minimum feature sizes, which allows more components to be integrated in a specific area.

These smaller electronic components have smaller areas than conventional packages, and thus require smaller packages. For example, semiconductor chips or dies have more and more input/output (I/O) pads, and a redistribution layer (RDL) may rearrange the positions of the original I/O pads of the semiconductor chip or die around the semiconductor chip or die to increase the number of I/os.

However, in the conventional wafer level packaging process, the UBM layer has a nearly planar structure, so that the contact area between the UBM layer and the solder ball is small and the bonding force is weak, which may cause solder ball peeling or generate an intermetallic compound (IMC) problem. In addition, the abnormal height of the solder balls is also easy to cause the problems of cold solder joint (cold joint) or solder bridge (solder bridge) in the packaging process.

Disclosure of Invention

The invention provides a rewiring structure, comprising: the semiconductor device includes a substrate, a pad, a dielectric layer, a self-aligned structure, a conductive layer and a conductive connector. The pad is disposed on the substrate. The dielectric layer is disposed on the substrate and exposes a portion of the pad. The self-aligned structure is disposed on the dielectric layer. The conductive layer extends from the pad and conformally covers the surface of the self-aligned structure. The conductive connection is disposed on the self-aligned structure.

The invention provides a manufacturing method of a rewiring layer structure. Forming a pad on the substrate. A dielectric layer is formed on a substrate. The dielectric layer has an opening exposing a portion of the pad. A self-aligned structure is formed on the dielectric layer by a first 3D printing technique. And forming a conductive layer by a second 3D printing technology, wherein the conductive layer extends from the connecting pad and conformally covers the surface of the self-alignment structure. Conductive connections are formed on the self-aligned structures.

Based on the above, the self-aligned structure with the recess is formed by the 3D printing technology, so that the contact area between the conductive layer conformally covering the self-aligned structure and the conductive connecting member embedded in the recess is increased, and the problem of peeling or breaking of the conductive connecting member is avoided. Therefore, the invention can greatly increase the structural strength between the conductive layer and the conductive connecting piece in the redistribution layer structure, thereby improving the reliability of the product. In addition, the manufacturing method of the redistribution layer structure has the advantage of simple process steps, so that the commercial competitiveness of the product is improved.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1A to fig. 1D are schematic cross-sectional views illustrating a manufacturing process of a redistribution layer structure according to an embodiment of the invention.

FIG. 2 is an enlarged cross-sectional view of a portion of the self-aligned structure of FIG. 1B.

Fig. 3 is an enlarged cross-sectional view of a portion of the conductive layer of fig. 1C.

Fig. 4 is an enlarged cross-sectional view of a portion of the redistribution layer structure of fig. 1D.

Detailed Description

The present invention will be described more fully with reference to the accompanying drawings of the present embodiments. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. The thickness of layers and regions in the drawings may be exaggerated for clarity. The same or similar element numbers refer to the same or similar elements, and the description thereof will not be repeated in the following paragraphs.

Fig. 1A to fig. 1D are schematic cross-sectional views illustrating a manufacturing process of a redistribution layer structure according to an embodiment of the invention. FIG. 2 is an enlarged cross-sectional view of a portion of the self-aligned structure of FIG. 1B. Fig. 3 is an enlarged cross-sectional view of a portion of the conductive layer of fig. 1C. Fig. 4 is an enlarged cross-sectional view of a portion of the redistribution layer structure of fig. 1D.

Referring to fig. 1A, the present embodiment provides a method for manufacturing a redistribution layer (RDL) structure, which includes the following steps. First, a substrate 100 is provided. In one embodiment, the substrate 100 includes a semiconductor material. Specifically, the substrate 100 may be formed of at least one semiconductor material selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP. In the present embodiment, the substrate 100 may be a silicon substrate. In addition, the substrate 100 may also include a Silicon On Insulator (SOI) substrate. Although it is not shown in fig. 1A that any element is disposed in the substrate 100, the substrate 100 of the present embodiment may have an active element (e.g., a transistor, a diode, etc.), a passive element (e.g., a capacitor, an inductor, a resistor, etc.), or a combination thereof. In other embodiments, the substrate 100 may have, for example, logic devices, memory devices, or a combination thereof.

Next, a pad 102 is formed on the substrate 100. In one embodiment, the material of the pad 102 includes a metal material, such as copper, aluminum, gold, silver, nickel, palladium, or a combination thereof. The forming method of the pad 102 includes a Physical Vapor Deposition (PVD) method, a plating method (plating) method, or a combination thereof. Although only one pad 102 is shown in fig. 1A, the invention is not limited thereto. In other embodiments, the number of the pads 102 can be adjusted as required. In one embodiment, the pads 102 may be electrically connected to devices (not shown) in the substrate 100.

Thereafter, a dielectric layer 104 is formed on the substrate 100. The dielectric layer 104 covers the sidewalls of the pad 102 and covers a portion of the top surface of the pad 102. As shown in fig. 1A, the dielectric layer 104 has an opening 105. The opening 105 exposes another portion of the top surface 102t of the pad 102. In one embodiment, the material of the dielectric layer 104 includes a dielectric material, which may be, for example, silicon oxide, silicon nitride, silicon oxynitride, polyimide, or a combination thereof. The dielectric layer 104 may be formed by PVD (physical vapor deposition), CVD (chemical vapor deposition), or a combination thereof.

Referring to fig. 1B, the self-aligned structure 106 is formed by a three-dimensional (3D) printing technique. In an embodiment, the 3D Printing technology includes an Ink Jet Printing process (Ink Jet Printing process), an Aerosol Jet Printing process (Aerosol Jet Printing process), or a combination thereof. Taking the aerosol spray printing process as an example, an aerosol jet deposition head (aerosol jet deposition head) is used to form an annular propagation nozzle consisting of an outer sheath flow (outer sheath flow) and an inner aerosol-laden carrier flow (inner aerosol-laden carrier flow). In the circular aerosol spray process, an aerosol stream (aerosol stream) of the material to be deposited is focused and deposited on the surface to be formed. The above steps may be referred to as maskless mesoscale Material Deposition (M3D), that is, they may be deposited without the use of a mask.

In this embodiment, as shown in fig. 1B, an insulating ink 204 is ejected onto the dielectric layer 104 by a nozzle 202 of the 3D printing apparatus. In one embodiment, the insulating ink 204 includes an insulating material and a solvent. The insulating material may be, for example, polyimide, Polyurethane (PU), or the like. The solvent may be N-Methyl pyrrolidone (NMP), Propylene Glycol Methyl Ether (PGME), ethylene glycol, and the like. After the curing step, the insulating ink 204 is cured into the self-aligned structure 106. In an alternative embodiment, the curing step includes curing by heating or shining light to volatilize the solvent in the insulating ink 204. In other embodiments, the material of the self-aligned structure 106 includes an insulating polymer, which may be, for example, polyimide (polyimide), Polyurethane (PU), epoxy (SU-8), an adhesive, or a combination thereof. Although only one self-aligned structure 106 is shown in fig. 1B, the invention is not so limited. In other embodiments, the number of self-aligned structures 106 may be adjusted as desired.

Further, as shown in the enlarged view 2 of the portion 107 of the self-aligned structure 106 of fig. 1B, the self-aligned structure 106 includes a top surface 106t and a bottom surface 106B opposite to each other and a sidewall 106s extending to connect the top surface 106t and the bottom surface 106B. The top surface 106t of the self-aligned structure 106 also has a recess 106 r. In one embodiment, as shown in fig. 2, the recessed portion 106r may be an arc surface recessed from the top surface 106t to the bottom surface 106 b. However, the present invention is not limited thereto, and in other embodiments, the recessed portion 106r may be a U-shaped surface, a V-shaped surface, or a surface with various shapes recessed from the top surface 106t to the bottom surface 106 b.

In addition, as shown in fig. 2, the side wall 106s and the bottom surface 106b have an included angle a of less than 90 degrees therebetween. That is, the sidewalls of the self-aligned structure 106 are sloped and tapered sidewalls. When the included angle a is smaller than 90 degrees, it can enhance the adhesion between the self-aligned structure 106 and the dielectric layer 104 therebelow and has the effect of absorbing stress. Although fig. 2 shows the included angle a being smaller than 90 degrees, the invention is not limited thereto, and in other embodiments, the included angle a may be equal to or larger than 90 degrees. On the other hand, a chamfer B is formed between the extension plane of the top surface 106t and the arc surface of the recess 106 r. The cutting angle B can be changed to adjust the size and height of the conductive connection element 110 (shown in fig. 1D) to be formed subsequently. In one embodiment, the included angle a may be between 30 degrees and 70 degrees; and the chamfer angle B may be between 20 degrees and 40 degrees.

Referring to fig. 1C, the conductive layer 108 is formed by a 3D printing technique. In detail, the conductive ink 214 is ejected through the nozzle 212 of the 3D printing apparatus onto the pad 102, the dielectric layer 104 and the self-aligned structure 106 to form the conductive layer 108. In this case, as shown in fig. 1C, the conductive layer 108 extends from the pad 102 and conformally covers the surface of the self-aligned structure 106. Specifically, the conductive layer 108 may include a first portion 108a, a second portion 108b, and a third portion 108 c. The first portion 108a conformally covers and contacts the top surface 102t of the pad 102. The second portion 108b conformally covers and contacts the top surface 106t, the recess 106r, and the sidewalls 106s of the self-aligned structure 106. The third portion 108c is positioned between the first portion 108a and the second portion 108b to connect the first portion 108a and the second portion 108 b. In one embodiment, the first portion 108a may be regarded as an original input/output (I/O) pad for Chip Probing (CP), hereinafter referred to as a test pad 108 a. The second portion 108b may be considered a RDL pad after rerouting such that a conductive connection 110 (shown in fig. 1D) is formed thereon for electrical connection to an external circuit or component, hereinafter RDL pad 108 b. The third portion 108c may then be considered as a trace (trace) connecting between the test pad 108a and the RDL pad 108 b.

In one embodiment, the minimum thickness of the conductive layer 108 may be between 0.5 μm and 5 μm. However, the invention is not limited thereto, and in other embodiments, the thickness of the conductive layer 108 may be increased by printing a build-up layer.

In one embodiment, the conductive ink 214 includes a plurality of conductive particles 115 and a solvent. The solvent includes N-methyl pyrrolidone, propylene glycol methyl ether, ethylene glycol and the like. More specifically, referring to fig. 1C, an enlarged view 3 of a portion 109 of the conductive layer 108, after the curing step, the conductive layer 108 is formed by a plurality of conductive particles 115 contacting each other. In an embodiment, the conductive particles 115 include a plurality of metal nanoparticles, which may be, for example, silver nanoparticles, copper nanoparticles, or a combination thereof. In another embodiment, the conductive particles 115 may have an average particle size between 5nm and 1 μm. The standard deviation of the particle size distribution of the conductive particles 115 may be between 4.5 and 43. In some embodiments, the conductive layer 108 is formed by tightly connecting spherical conductive particles 115 with uniform sizes to achieve uniform conductivity. In other embodiments, the conductive particles 115 may also have different particle sizes.

On the other hand, as shown in fig. 1C and 3, the test pad 108a, the RDL pad 108b, and the trace 108C therebetween share (share) at least one or more of the conductive particles 115. That is, a portion of the conductive particles 115 span across the virtual interface 101 between the test pad 108a and the trace 108 c; while another portion of the conductive particles 115 span the virtual interface 103 between trace 108c and RDL pad 108 b. Note that there is virtually no interface between test pad 108a and trace 108c and between trace 108c and RDL pad 108 b. The

virtual interfaces

101, 103 described herein are defined for clarity to define that the test pads 108a, RDL pads 108b, and traces 108c are integrally formed. So-called integral molding can be regarded as being formed by the same process and the same material. For example, test pads 108a, RDL pads 108b, and traces 108c are formed with the same 3D printing technology and with the same conductive ink 214. Therefore, compared to the conventional UBM layer, the RDL pad 108b of the present embodiment can avoid the problem of IMC cracking (crack) to improve the reliability of the product.

In addition, since the conductive layer 108 conformally covers the surface of the self-aligned structure 106, the RDL pad 108b of the conductive layer 108 also replicates the shape of the recess 106r of the self-aligned structure 106 and has another recess 108 r. In one embodiment, as shown in fig. 3, the recess 108r may be a curved surface recessed from the top surface 108t toward the extending direction of the dielectric layer 104. However, the invention is not limited thereto, and in other embodiments, the recess 108r may be a U-shaped surface, a V-shaped surface or a surface with various shapes recessed from the top surface 108t toward the extending direction of the dielectric layer 104.

Referring to fig. 1D, a conductive connection element 110 is formed on the self-aligned structure 106. Specifically, the conductive connection element 110 may be formed into a desired bump shape by forming a layer of solder on the recess 106r of the self-aligned structure 106 by a method such as evaporation, electroplating, printing, solder transfer, ball-planting, etc., and then performing a reflow step to form the conductive connection element 110 into the desired bump shape. In some embodiments, the material of the conductive connection 110 includes a conductive material, which may be, for example, a solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like conductive material. In the present embodiment, as shown in fig. 1D, the conductive connection member 110 may be a solder ball.

It is noted that, since the self-aligned structure 106 has the recess 106r, the conductive connecting element 110 can be self-aligned or positioned in the recess 106 r. In this case, as shown in the enlarged view 4 of the portion 111 of the redistribution layer structure in fig. 1D, the lower portion 110a of the conductive connection 110 is embedded in the recess 108r of the conductive layer 108 (or the recess 106r of the self-aligned structure 106), and the upper portion 110b of the conductive connection 110 is exposed out of the recess 108r of the conductive layer 108 (or the recess 106r of the self-aligned structure 106). The recess 108r of the conductive layer 108 is located between the recess 106r of the self-aligned structure 106 and the conductive connection 110. In one embodiment, the depth 106d of the recess 106r of the self-aligned structure 106 may be between one third and one quarter of the height 110h of the conductive connection 110. Compared with the conventional UBM layer, the contact area between the conductive layer 108 and the conductive connecting element 110 of the present embodiment is larger, which can greatly increase the structural strength between the conductive layer 108 and the conductive connecting element 110, thereby improving the product reliability. In addition, the depth 106d and the chamfer angle B of the recess 106r can be changed to adjust the size and the height of the conductive connecting element 110. For example, the deeper the depth 106d of the recess 106r and the larger the cutting angle B, the more the lower portion 110a of the conductive connecting element 110 is engaged with the recess 106 r. In this case, the ball height of the upper portion 110b of the conductive connection member 110 is reduced. Otherwise, the ball height of the upper portion 110b of the conductive connection member 110 is increased. Therefore, the present embodiment can prevent the problem of cold solder joint or solder bridging caused by abnormal ball height.

In addition, compared to the conventional packaging process in which processes such as sputtering, electroplating, photolithography, and etching are repeatedly used to form the RDL structure and the UBM layer, the conductive layer 108 (including the test pad 108a, the RDL pad 108b, and the trace 108c) is formed by the 3D printing technique in the embodiment, which can simplify the process steps, reduce the manufacturing cost, and improve the commercial competitiveness of the product.

In summary, the self-aligned structure with the recess is formed by the 3D printing technique, so as to increase the contact area between the conductive layer conformally covering the self-aligned structure and the conductive connecting element embedded in the recess. Therefore, the invention can greatly increase the structural strength between the conductive layer and the conductive connecting piece in the redistribution layer structure, thereby improving the reliability of the product. In addition, the manufacturing method of the redistribution layer structure has the advantage of simple process steps, so that the commercial competitiveness of the product is improved.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A rewiring layer structure, comprising:

pads, arranged on the substrate;

a dielectric layer, disposed on the substrate, and exposing part of the pad;

A self-aligned structure configured on the dielectric layer;

a conductive layer extending from the pads and conformally covering the surface of the self-aligned structure; and

A conductive connector is arranged on the self-aligned structure.

2. The redistribution layer structure of claim 1, wherein the self-aligned structure comprises opposing top and bottom surfaces, the top surface having a recess.

3 . The redistribution layer structure of claim 2 , wherein the self-aligned structure comprises sidewalls extending connecting the top surface and the bottom surface, the sidewalls and the bottom surface having a distance of less than 90 degrees. 4 . angle.

4 . The redistribution layer structure of claim 2 , wherein a portion of the conductive connection member is embedded in the recessed portion of the self-aligned structure, and a portion of the conductive layer is located in the self-aligned structure. 5 . between the recessed portion of the quasi-structure and the conductive connector.

5. The redistribution layer structure of claim 2, wherein the depth of the recessed portion of the self-aligned structure is between one-third and one-quarter of the height of the conductive connection.

6. The redistribution layer structure of claim 1, wherein the conductive layer is composed of a plurality of conductive particles in contact with each other, the plurality of conductive particles comprising a plurality of metal nanoparticles, the plurality of metal nanoparticles Including silver nanoparticles, copper silver nanoparticles, copper nanoparticles, or a combination thereof.

7. The redistribution layer structure of claim 1, wherein the self-aligned structure comprises an insulating polymer comprising polyimide, polyurethane, epoxy, adhesive, or a combination thereof.

8. A method for manufacturing a redistribution layer structure, comprising:

forming pads on the substrate;

forming a dielectric layer on the substrate, the dielectric layer having openings exposing portions of the pads;

forming a self-aligned structure on the dielectric layer by a first 3D printing technique;

forming a conductive layer by a second 3D printing technique, the conductive layer extending from the pads and conformally covering the surface of the self-aligned structure; and

Conductive connections are formed on the self-aligned structures.

9 . The method of manufacturing the redistribution layer structure according to claim 8 , wherein the self-aligned structure comprises a top surface and a bottom surface opposite to each other, and the top surface has a concave portion to embed a part of the conductive connection member. 10 . fit in the recessed portion of the self-aligned structure.

10. The method of manufacturing a redistribution layer structure according to claim 8, wherein forming the conductive layer by the second 3D printing technique comprises using a conductive ink, the conductive ink comprising a plurality of metal nanoparticles, the plurality of metal nanoparticles. The metal nanoparticles include silver nanoparticles, copper silver nanoparticles, copper nanoparticles, or a combination thereof.