CN111211055B - Semiconductor structures and methods of forming them - Google Patents

Abstract

A semiconductor structure and its forming method, wherein the forming method includes: providing a base, the base includes a first region, the first region has a dielectric layer on the surface of the substrate, the first region has a dummy gate opening in the dielectric layer, the There are source and drain doped regions in the substrate on both sides of the dummy gate opening, and the dielectric layer covers the surface of the source and drain doped regions; part of the dielectric layer is removed until the top of the source and drain doped regions are exposed, forming a A contact hole; forming a metal silicide layer on the surface of the source-drain doped region at the bottom of the contact hole; after forming the metal silicide layer, forming a first work function layer at the bottom of the dummy gate opening in the first region. The performance of the semiconductor device formed by the method is better.

Description

Semiconductor structures and methods of forming them

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof.

Background technique

Complementary metal-oxide-semiconductor (CMOS) transistors, as the most basic devices in semiconductor manufacturing, are often widely used in various integrated circuits. Complementary metal oxide semiconductors are divided into NMOS transistors and PMOS transistors according to the main carrier and the doping type during manufacture. Taking the NMOS transistor as an example, the NMOS transistor includes: source and drain doped regions.

In the existing CMOS process, in order to improve the contact resistance between the source-drain doped region and the plug on the source-drain doped region, a metal silicide layer is usually formed on the top surface of the source-drain doped region.

However, the performance of transistors formed by the prior art is still poor.

Contents of the invention

The technical problem solved by the invention is to provide a semiconductor structure and its forming method to improve the performance of semiconductor devices.

In order to solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate includes a first region, the surface of the substrate in the first region has a dielectric layer, and the dielectric layer in the first region There is a dummy gate opening inside, the substrate on both sides of the dummy gate opening has a source-drain doping region, and the dielectric layer covers the surface of the source-drain doping region; part of the dielectric layer is removed until the source-drain doping region is exposed A contact hole is formed in the dielectric layer; a metal silicide layer is formed in the contact hole; after the metal silicide layer is formed, a first function is formed at the bottom of the dummy gate opening in the first region function layer.

Optionally, the method for forming the metal silicide layer includes: forming a metal layer on the surface of the source-drain doped region at the bottom of the contact hole; performing a first annealing treatment to make the metal layer and the top of the source-drain doped region The reaction forms a metal silicide layer.

Optionally, the material of the metal layer includes nickel or titanium.

Optionally, the first annealing process includes: a laser annealing process; parameters of the laser annealing process include: 850 degrees Celsius to 1000 degrees Celsius.

Optionally, when the first region is used to form an NMOS transistor, the material of the first work function layer includes titanium aluminum.

Optionally, before forming the contact hole, the forming method includes: forming a gate dielectric layer and a first sacrificial layer on the surface of the gate dielectric layer at the bottom of the dummy gate opening in the first region; A second sacrificial layer is formed on the surface of the layer; the material of the first sacrificial layer includes amorphous silicon; the material of the second sacrificial layer includes amorphous silicon.

Optionally, after forming the gate dielectric layer and before forming the first sacrificial layer, further include: performing a second annealing process; the second annealing process includes a spike annealing process; parameters of the spike annealing process include: 800 degrees Celsius ~950 degrees Celsius.

Optionally, after forming the first sacrificial layer and before forming the second sacrificial layer, the forming method further includes: performing a third annealing process; the third annealing process includes a spike annealing process; parameters of the spike annealing process include : 850 degrees Celsius to 1000 degrees Celsius.

Optionally, the substrate further includes a second region, the dielectric layer is also located on the substrate surface of the second region, the dummy gate opening is also located in the dielectric layer of the second region, and the dummy source-drain doped region is also Located in the substrate on both sides of the dummy gate opening in the second region; the gate dielectric layer is also located at the bottom of the dummy gate opening in the second region; after forming the gate dielectric layer and before forming the first sacrificial layer, the forming method further includes : forming a second work function film at the bottom of the dummy gate openings in the first region and the second region.

Optionally, the second region is used to form a PMOS transistor; the material of the second work function film includes titanium nitride.

Optionally, after forming the metal silicide layer and before forming the first work function layer, the forming method includes: forming a plug in the contact hole, the plug filling the dummy gate opening; forming the plug After the plug, remove the second sacrificial layer and the first sacrificial layer; after removing the second sacrificial layer and the first sacrificial layer, remove the second work function film in the first region, and form a second work function layer.

Optionally, after forming the first work function layer, the forming method includes: forming a gate layer in the dummy gate opening, the gate layer filling the dummy gate opening.

Correspondingly, the present invention also provides a semiconductor structure, including: a base, the base includes a first region, the first region has a dielectric layer on the surface of the substrate, the first region has a dummy gate opening in the dielectric layer, the There are source and drain doped regions in the substrate on both sides of the dummy gate opening, and the dielectric layer covers the surface of the source and drain doped regions; the contact hole located in the dielectric layer, the bottom of the contact hole exposes the source and drain doped regions. The top surface of the region; the metal silicide layer on the top of the source-drain doping region at the bottom of the contact hole; the first work function layer on the bottom surface of the dummy gate opening.

Optionally, the first region is used to form an NMOS transistor, and the material of the first work function layer includes titanium aluminum.

Optionally, the substrate further includes a second region, the dielectric layer is also located on the substrate surface of the second region, the dummy gate opening is also located in the dielectric layer of the second region, and the source-drain doped region is also located in the second region. In the substrate on both sides of the dummy gate opening.

Optionally, it also includes: a gate dielectric layer located at the bottom of the dummy gate opening in the first region and the dummy gate opening in the second region; a second work function layer located on the surface of the gate dielectric layer in the second region; For forming a PMOS transistor, the material of the second work function layer includes titanium nitride.

Optionally, the semiconductor structure further includes: a plug located on the surface of the metal silicide layer in the contact hole, the plug filling the contact hole; a gate located on the surface of the first work function layer at the bottom of the dummy gate opening layer, the gate layer is filled with dummy gate openings.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following beneficial effects:

In the method for forming a semiconductor structure provided by the technical solution of the present invention, after forming the metal silicide layer, a first work function layer is formed, so that the ions in the first work function layer are not affected by the high temperature in the high temperature process of the metal silicide layer. Therefore, the diffusion of ions in the first work function layer can be prevented, which is beneficial to improve the performance of the semiconductor device.

Further, after forming the gate dielectric layer and before forming the first sacrificial layer, performing a second annealing process is also included. The first sacrificial layer is formed before the contact hole is formed, therefore, the second annealing process is performed before the formation of the first work function layer, so that the ions in the first work function layer are less affected by the second annealing process. It is beneficial to further reduce the diffusion of ions in the first work function layer.

Further, after forming the first sacrificial layer and before forming the second work function layer, performing a third annealing process is also included. Since the second work function layer is formed before forming the contact hole, the third annealing process is performed before forming the first work function layer, so that the ions in the first work function layer are less affected by the third annealing process. It is beneficial to further reduce the diffusion of ions in the first work function layer.

Description of drawings

1 to 3 are structural schematic diagrams of each step of a method for forming a semiconductor structure;

FIG. 4 to FIG. 16 are structural schematic diagrams of each step of a method for forming a semiconductor structure according to an embodiment of the present invention.

Detailed ways

As mentioned in the background, semiconductor devices perform poorly.

1 to 3 are structural schematic diagrams of a semiconductor structure.

Please refer to FIG. 1 , a substrate 100 is provided, the substrate 100 includes an NMOS region, the surface of the NMOS region substrate 100 has a dummy gate structure (not shown in the figure), and the substrate 100 on both sides of the dummy gate structure has a source drain The doped region 101, the substrate 100 and the surface of the source and drain doped region 101, and the sidewall of the dummy gate structure have a dielectric layer 102, and the dielectric layer 102 exposes the top surface of the dummy gate structure; remove the dummy gate structure , forming a dummy gate opening 103 in the dielectric layer 102 .

Please refer to FIG. 2 , a gate dielectric layer 104 is formed on the bottom surface of the dummy gate opening 103 (see FIG. 1 ); a first work function layer 105 is formed on the surface of the gate dielectric layer 104 and a The gate layer 106 is filled with dummy gate openings 103 .

Please refer to FIG. 3 , after the gate layer 103 is formed, part of the dielectric layer 102 is removed until the top surface of the source-drain doped region 101 is exposed, and a contact hole 106 is formed in the dielectric layer 102; A metal silicide layer 107 is formed on the surface of the source-drain doped region 101 at the bottom of 106 .

In the above method, the NMOS region is used to form an NMOS transistor, the material of the first work function layer 105 includes titanium aluminum, and the first work function layer 105 is used to adjust the threshold voltage of the NMOS transistor. The method for forming the metal silicide layer 107 includes: forming a metal layer on the sidewall and bottom surface of the contact hole 106; performing annealing treatment to make the metal layer react with the top of the source-drain doped region 101 to form a metal silicide Layer 107.

However, the annealing treatment tends to drive aluminum ions to diffuse into the gate dielectric layer 104 , so that the dielectric constant of the gate dielectric layer 104 is reduced, and the gate dielectric layer 104 is easily broken down, which is not conducive to improving the performance of the semiconductor device.

Moreover, the substrate 100 also includes other devices, such as: PMOS transistors (not shown in the figure), if aluminum ions diffuse into the PMOS transistors, the threshold voltage of the PMOS transistors will be affected, which is not conducive to improving the performance of the PMOS transistors.

To solve the technical problem, the present invention provides a method for forming a semiconductor structure, comprising: after forming the metal silicide layer, forming a first work function layer on the bottom surface of the dummy gate opening in the first region. The method can reduce the diffusion of ions in the first work function layer and improve the performance of the semiconductor device.

In order to make the above objects, features and beneficial effects of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

FIG. 4 to FIG. 16 are structural schematic diagrams of each step of a method for forming a semiconductor structure according to an embodiment of the present invention.

4, a substrate 200 is provided, the substrate 200 includes a first region A, the surface of the substrate 200 in the first region A has a dummy gate structure 203, and the substrate 200 on both sides of the dummy gate structure 203 has a source drain The doped region 206 , the substrate 200 , the surfaces of the source and drain doped regions 206 , and the sidewalls of the dummy gate structure 203 have a dielectric layer 208 , and the dielectric layer 208 exposes the top surface of the dummy gate structure 203 .

In this embodiment, the base 200 includes: a substrate 201 and a fin 202 on the substrate 201 .

In other embodiments, when the semiconductor device is a planar MOS transistor, the substrate is a planar semiconductor substrate.

In this embodiment, the step of forming the substrate 200 includes: providing an initial substrate, the initial substrate has a first mask layer, and the first mask layer exposes part of the top surface of the initial substrate; The first mask layer is a mask, and the initial substrate is etched to form a substrate 201 and fins 202 on the substrate 201 .

In other embodiments, the method for forming the base includes: providing a substrate; and epitaxially forming the fin on the surface of the substrate.

In this embodiment, the material of the initial substrate is silicon. Correspondingly, the material of the substrate 201 and the fin portion 202 is silicon. In other embodiments, the material of the initial substrate includes: germanium, silicon germanium, silicon-on-insulator, or germanium-on-insulator. Correspondingly, the material of the substrate includes: germanium, silicon germanium, silicon-on-insulator or germanium-on-insulator. Materials for the fins include germanium, silicon germanium, silicon-on-insulator, or germanium-on-insulator.

The material of the first mask layer includes silicon nitride, and the formation process of the first mask layer includes: a chemical vapor deposition process. The first mask layer is used to form a mask for the substrate 201 and the fin portion 202 .

Using the first mask layer as a mask, the process of etching the initial substrate includes: one or both of a dry etching process and a wet etching process.

The base 200 also has an isolation structure (not shown) covering part of the fin 202 , the top surface of the isolation structure is lower than the top surface of the fin 202 and covers part of the fin 202 side wall.

The material of the isolation structure includes: silicon oxide. In other embodiments, the material of the isolation structure may also be silicon oxynitride, silicon nitride.

The isolation structure is used to realize electrical isolation between different semiconductor devices.

The first region A is used to form NMOS transistors.

In this embodiment, the substrate 200 further includes a second region B for forming a PMOS transistor, the dielectric layer 208 is also located on the surface of the substrate 200 in the second region B, and the dummy gate structure 203 Also located in the second region B, the source-drain doped region 206 is also located in the substrate 200 on both sides of the dummy gate structure 203 in the second region B.

In other embodiments, the substrate includes only the first region. The dummy gate structure 203 spans the fin portion 202, and the dummy gate structure 203 includes a dummy gate dielectric layer (not shown in the figure) and a dummy gate layer (not shown in the figure) located on the surface of the dummy gate dielectric layer. ).

The material of the dummy gate dielectric layer includes silicon oxide, and the material of the dummy gate layer includes silicon.

The sidewall of the dummy gate structure 203 has a first sidewall 204, and the first sidewall 204 is used to define the position of the lightly doped region. The material of the first sidewall 204 includes silicon nitride.

The sidewall of the first sidewall 204 has a second sidewall 205 , and the second sidewall 205 is used for the location of the source-drain doping region 206 .

The method for forming the source-drain doped region 206 includes: forming source-drain openings in the fins 202 on both sides of the dummy gate structure 203, the first sidewall 204 and the second sidewall 205; An epitaxial layer is formed in the epitaxial layer; doping ions are doped into the epitaxial layer to form a source-drain doped region 206 .

The material of the epitaxial layer and the conductivity type of dopant ions are related to the type of transistor.

In this embodiment, the first region A is used to form an NMOS transistor, the material of the epitaxial layer includes silicon carbide or silicon, and the dopant ions are N-type ions. The second region B is used to form a PMOS transistor, the material of the epitaxial layer includes silicon germanium or silicon, and the dopant ions are P-type ions.

After forming the source-drain doped region 206 and before forming the dielectric layer 208 , the forming method further includes: forming a stop layer 207 on the top of the source-drain doped region 206 .

The material of the stop layer 207 includes silicon nitride, and the stop layer 207 is used as a stop layer for subsequent formation of contact holes in the dielectric layer 208 on the top of the source-drain doped region 206, which is beneficial to protect the source-drain doped region 206 of the top surface.

In this embodiment, the stop layer 207 also covers the surface of the isolation structure and the sidewall of the second sidewall 205 .

In other embodiments, the stop layer only covers the top surface of the source-drain doped region.

The forming method of the dielectric layer 208 includes: forming a dielectric film on the top surface of the stop layer 207 and the dummy gate structure 203; planarizing the dielectric film until the top surface of the dummy gate layer is exposed to form a dielectric layer 208 .

The material of the dielectric film includes silicon oxide or silicon oxynitride. Correspondingly, the material of the dielectric layer 208 includes silicon oxide or silicon oxynitride. The forming process of the dielectric film includes a physical vapor deposition process or a chemical vapor deposition process.

The process of planarizing the dielectric film includes: a chemical mechanical polishing process.

Referring to FIG. 5 , the dummy gate structure 203 (see FIG. 4 ) is removed, and a dummy gate opening 209 is formed in the dielectric layer 208 .

The method for removing the dummy gate structure 203 includes: removing the dummy gate layer; after removing the dummy gate layer, removing the dummy gate dielectric layer.

The process of removing the dummy gate layer includes: one or a combination of dry etching process and wet etching process.

The process for removing the dummy gate dielectric layer includes: one or a combination of dry etching process and wet etching process.

The dummy gate opening 209 in the first region A is used to subsequently accommodate the gate dielectric layer, the first work function layer on the gate dielectric layer, and the gate layer on the surface of the first work function layer; the dummy gate opening 209 in the second region B The gate opening 209 is used to subsequently accommodate the gate dielectric layer, the second work function layer on the surface of the gate dielectric layer, and the gate layer on the surface of the second work function layer.

Referring to FIG. 6 , an interface layer (not shown in the figure) is formed on the surface of the fin portion 202 at the bottom of the dummy gate opening 209 ; a gate dielectric layer 210 is formed on the surface of the interface layer.

The material of the interface layer includes silicon oxide. The formation process of the interface layer includes a chemical oxidation process, and the parameters of the chemical oxidation process include: the oxidizing agent includes hydrogen peroxide.

The interface layer is used to improve the interface state between the gate dielectric layer 210 and the fin portion 202 .

The gate dielectric layer 210 is made of high dielectric constant (dielectric constant K greater than 3.9) material. In this embodiment, the material of the gate dielectric layer 210 is hafnium oxide. In other embodiments, the material of the gate dielectric layer includes: La ₂ O ₃ , HfSiON, HfAlO ₂ , ZrO ₂ , Al ₂ O ₃ or HfSiO ₄ .

After the gate dielectric layer 210 is formed, a second annealing treatment is also performed. The second annealing process includes a spike annealing process, and parameters of the spike annealing process include: 800 degrees Celsius to 950 degrees Celsius.

The interface layer formed by the chemical oxidation process has many defects, and the second annealing treatment is used to repair the defects in the interface layer, so that the interface state between the interface layer and the gate dielectric layer 210, and the interface layer and the fin 202 All are good, which is conducive to improving the performance of semiconductor devices.

Referring to FIG. 7 , a second work function film 211 is formed on the surface of the gate dielectric layer 210 .

The second work function film 211 is used to subsequently form a second work function layer on the surface of the gate dielectric layer 210 at the bottom of the dummy gate opening 209 in the second region B. The second work function layer is used to adjust the threshold voltage of the PMOS transistor.

The material of the second work function film 211 includes titanium nitride.

Referring to FIG. 8 , a first sacrificial layer 212 is formed on the surface of the second work function film 211 .

The material of the first sacrificial layer 212 includes amorphous silicon, and the formation process of the first sacrificial layer 212 includes: a chemical vapor deposition process or a physical vapor deposition process.

After forming the first sacrificial layer 212 , it further includes: performing a third annealing treatment, the process of the third annealing treatment includes: a spike annealing process, and the parameters of the spike annealing process include: 850 degrees Celsius to 1000 degrees Celsius.

The third annealing process is beneficial for the first sacrificial layer 212 to absorb oxygen in the gate dielectric layer 210, which is conducive to ensuring the dielectric constant of the gate dielectric layer 210, thereby preventing the gate dielectric layer 210 from being broken down, and is conducive to improving the performance of the semiconductor device. performance.

The thickness of the first sacrificial layer 212 is 35 Ř110 Å.

The significance of selecting the thickness of the first sacrificial layer 212 is: if the thickness of the first sacrificial layer 212 is too thin, the ability of the first sacrificial layer 212 to balance the oxygen content in the gate dielectric layer 210 is weak, so that the dielectric layer 210 It is difficult to ensure the electrical constant, which is not conducive to the performance of semiconductor devices; if the thickness of the first sacrificial layer 212 is too thick, since the amorphous silicon material is prone to atomic agglomeration during the third annealing process, it is not conducive to subsequent process removal.

Referring to FIG. 9 , a second sacrificial layer 213 is formed on the surface of the first sacrificial layer 212 , and the second sacrificial layer 213 is filled with the dummy gate opening 209 (see FIG. 8 ).

The forming method of the second sacrificial layer 213 includes: forming a second sacrificial film on the surface of the first sacrificial layer 212; planarizing the second sacrificial film until the top surface of the dielectric layer 208 is exposed, and A second sacrificial layer 213 is formed in the gate opening 209 .

The material of the second sacrificial film includes amorphous silicon, and correspondingly, the material of the second sacrificial layer 213 includes amorphous silicon. The formation process of the second sacrificial film includes a chemical vapor deposition process or a physical vapor deposition process.

The process of planarizing the second sacrificial film includes: a chemical mechanical polishing process.

During the process of planarizing the second sacrificial film, the first sacrificial layer 212 , the second work function film 211 and the gate dielectric layer 210 on the surface of the dielectric layer 208 are also removed.

Referring to FIG. 10 , after forming the second sacrificial layer 213 , part of the dielectric layer 208 is removed until the top surface of the source-drain doped region 206 is exposed, and a contact hole 214 is formed in the dielectric layer 208 .

The method for forming the contact hole 214 includes: forming a second mask layer (not shown in the figure) on the surface of the dielectric layer 208 and the second sacrificial layer 213, and the second mask layer exposes source-drain doping Part of the dielectric layer 208 on the top of the impurity region 206; using the second mask layer as a mask, etch the dielectric layer 208 and the stop layer 207 until the top surface of the source-drain doped region is exposed. A contact hole 214 is formed in layer 208 and stop layer 207 .

The material of the second mask layer includes silicon nitride or titanium nitride, and the second mask layer is used to define the size and position of the contact hole 214 .

The contact hole 214 is used for subsequently accommodating the metal silicide layer and a plug located on the surface of the metal silicide layer.

Referring to FIG. 11 , a metal silicide layer 215 is formed on top of the source-drain doped region 206 at the bottom of the contact hole 214 .

The method for forming the metal silicide layer 215 includes: forming a metal layer (not shown in the figure) on the surface of the source-drain doped region 206 at the bottom of the contact hole 214; performing a first annealing process to make the metal layer and The top of the source-drain doped region 206 reacts to form a metal silicide layer 215 .

The material of the metal layer includes nickel or titanium, and correspondingly, the material of the metal silicide layer 215 includes nickel silicon compound or titanium silicon compound. The metal silicide layer 215 is used to reduce the contact resistance between the subsequent plug and the source-drain doped region 206 .

The forming process of the metal layer includes: a chemical vapor deposition process or a physical vapor deposition process.

The first annealing process includes: a laser annealing process, and the parameters of the laser annealing process include: 850 degrees Celsius to 1000 degrees Celsius.

When performing the first annealing process, the first work function layer is not formed on the surface of the dummy gate dielectric layer 210 at the bottom of the dummy gate opening 209 in the first region A, therefore, the subsequent first work function layer is not affected by the first annealing process, so that The ions in the first work function layer are not easily affected by the first annealing process, so the ions in the first work function layer are not easy to diffuse into the gate dielectric layer 210, which is beneficial to ensure the dielectric constant of the gate dielectric layer 210 and prevent the gate dielectric Layer 210 is broken down. Moreover, the ions in the first work function layer are not easy to diffuse into the second region B, so that the threshold voltage of the device in the second region B is not affected by the ions in the first work function layer, which is conducive to improving the second region B. device performance.

Referring to FIG. 12 , after the metal silicide layer 215 is formed, a plug 216 is formed in the contact hole 214 (see FIG. 11 ), and the plug 216 fills the contact hole 214 .

The method for forming the plug 216 includes: forming a plug film on the surface of the dielectric layer 208 and in the contact hole 214 ; removing part of the plug film, and forming the plug 216 in the contact hole 214 .

The material of the plug film is metal. The plug film is used to form the plug 216, therefore, the material of the plug 216 is metal.

In this embodiment, the material of the plug film is tungsten, and correspondingly, the material of the plug 216 is tungsten. In other embodiments, the material of the plug film includes aluminum or copper, and correspondingly, the material of the plug includes aluminum or copper.

The formation process of the plug film includes: a chemical vapor deposition process or a physical vapor deposition process.

The process of removing part of the plug film includes a chemical mechanical polishing process.

Referring to FIG. 13 , after the plug 216 is formed, the second sacrificial layer 213 and the first sacrificial layer 212 are removed.

The process of removing the second sacrificial layer 213 and the first sacrificial layer 212 includes one or a combination of a dry etching process and a wet etching process.

Removing the second sacrificial layer 213 and the first sacrificial layer 212 facilitates subsequent formation of the second work function layer and the gate layer.

Please refer to FIG. 14, after removing the second sacrificial layer 213 and the first sacrificial layer 212, a third sacrificial layer 250 is formed in the dummy gate opening 209 in the second region B; after forming the third sacrificial layer 250, the first sacrificial layer is removed The second work function film 211 is formed on the sidewall and bottom of the dummy gate opening 209 in the first region A, and the second work function layer 251 is formed on the sidewall and bottom of the dummy gate opening 209 in the second region B.

The material of the third sacrificial layer 250 includes bottom anti-reflection material. The third sacrificial layer 250 is used to prevent the second work function film 211 in the second region B from being removed, which is conducive to the subsequent formation of a second work function layer on the surface of the gate dielectric layer 210 at the bottom of the dummy gate opening 209 in the second region B 251.

The process of removing the second work function film 211 on the sidewall and bottom of the dummy gate opening 209 in the first region A includes: one or a combination of a dry etching process and a wet etching process.

The second work function layer 251 is used to improve the threshold voltage of the device in the second region B.

Referring to FIG. 15 , the first work function layer 217 is formed on the surface of the second work function layer 251 and the gate dielectric layer 210 .

After forming the second work function layer 251 and before forming the first work function layer 217 , the forming method further includes: removing the third sacrificial layer 250 .

The process of removing the third sacrificial layer 250 includes: an ashing process.

The material of the first work function layer 217 includes titanium aluminum. The first work function layer 217 is used to improve the threshold voltage of the device in the first region A, and the first region A is used to form an NMOS transistor.

Referring to FIG. 16 , a gate layer 218 is formed on the surface of the first work function layer 217 , and the gate layer 218 is filled with dummy gate openings 209 (see FIG. 15 ).

The forming method of the gate layer 218 includes: forming a gate material film on the surface of the dielectric layer 208 and the first work function layer 217, the gate material film filling the dummy gate opening 209; removing part of the gate material film, A gate layer 218 is formed in the dummy gate opening 209 until the top surface of the dielectric layer 208 is exposed.

The material of the gate material film is metal, and correspondingly, the material of the gate layer 218 is metal. In this embodiment, the material of the gate material film is aluminum, and correspondingly, the material of the gate layer 218 is aluminum. In other embodiments, the material of the gate material film includes: Al, Cu, Ag, Au, Ni, Ti, W, WN or WSi, and correspondingly, the material of the gate layer includes: Al, Cu, Ag, Au, Ni, Ti, W, WN or WSi.

Correspondingly, the present invention also provides a semiconductor structure, please continue to refer to FIG. 15, including:

The substrate 200, the substrate 200 includes a first region A, the surface of the substrate 200 in the first region A has a dielectric layer 208, and the dielectric layer 208 in the first region A has a dummy gate opening 209, and the dummy gate opening 209 has two There is a source-drain doped region 206 in the substrate 200 on the side, and the dielectric layer 208 covers the surface of the source-drain doped region 206;

A contact hole 214 (see FIG. 11 ) located in the dielectric layer 208, the bottom of the contact hole 214 exposes the top surface of the source-drain doped region 206;

a metal silicide layer 215 located on the top of the source-drain doped region 206 at the bottom of the contact hole 214;

The first work function layer 217 is located on the bottom surface of the dummy gate opening 209 .

The first region A is used to form an NMOS transistor, and the material of the first work function layer 217 includes titanium aluminum.

The substrate 200 also includes a second region B, the dielectric layer 208 is also located on the surface of the substrate 200 in the second region B, the dummy gate opening 209 is also located in the dielectric layer 208 in the second region B, and the source-drain doped region 206 is also located in the substrate 200 on both sides of the dummy gate opening 209 in the second region B.

It also includes: a gate dielectric layer 210 located at the bottom of the dummy gate opening 209 in the first region A and the dummy gate opening 209 in the second region B; a second Work function layer 251 ; the second region B is used to form a PMOS transistor, and the material of the second work function layer 211 includes titanium nitride.

The semiconductor structure further includes: a plug 216 located on the surface of the metal silicide layer 215 at the bottom of the contact hole 214 ; and a gate layer 218 located on the surface of the first work function layer 217 at the bottom of the dummy gate opening 209 .

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (17)

1. A method for forming a semiconductor structure, comprising: A substrate is provided, the substrate includes a first region, the substrate surface of the first region has a dielectric layer, a dummy gate opening is provided in the dielectric layer, source and drain doped regions are provided in the substrate on both sides of the dummy gate opening, and The dielectric layer covers the surface of the source-drain doped region; Form a gate dielectric layer and a first sacrificial layer on the surface of the gate dielectric layer at the bottom of the dummy gate opening in the first region; after forming the first sacrificial layer, perform a third annealing process; after the third annealing process, forming a second sacrificial layer on the surface of the first sacrificial layer; the first sacrificial layer is used to absorb oxygen in the gate dielectric layer; removing part of the dielectric layer until the top surface of the source-drain doped region is exposed, and forming a contact hole in the dielectric layer; forming a metal silicide layer on the surface of the source-drain doped region at the bottom of the contact hole; After the metal silicide layer is formed, a plug is formed in the contact hole, and the plug is filled with a dummy gate opening; after the plug is formed, the second sacrificial layer and the first sacrificial layer are removed; the second sacrificial layer is removed layer and the first sacrificial layer, a first work function layer is formed at the bottom of the dummy gate opening in the first region. 2. The method for forming a semiconductor structure according to claim 1, wherein the method for forming the metal silicide layer comprises: forming a metal layer on the surface of the source-drain doped region at the bottom of the contact hole; performing the first an annealing process to make the metal layer react with the top of the source-drain doped region to form a metal silicide layer. 3. The method for forming a semiconductor structure according to claim 2, wherein the material of the metal layer comprises nickel or titanium. 4 . The method for forming a semiconductor structure according to claim 2 , wherein the first annealing process comprises: a laser annealing process; parameters of the laser annealing process include: 850 degrees Celsius to 1000 degrees Celsius. 5. The method for forming a semiconductor structure according to claim 1, wherein when the first region is used to form an NMOS transistor, the material of the first work function layer includes titanium aluminum. 6. The method for forming a semiconductor structure according to claim 1, wherein the material of the first sacrificial layer comprises amorphous silicon; the material of the second sacrificial layer comprises amorphous silicon. 7. The method for forming a semiconductor structure according to claim 6, further comprising: performing a second annealing process after forming the gate dielectric layer and before forming the first sacrificial layer; the second annealing process includes Spike annealing process; the parameters of the spike annealing process include: 800 degrees Celsius to 950 degrees Celsius. 8. The method for forming a semiconductor structure according to claim 6, wherein after forming the first sacrificial layer and before forming the second sacrificial layer, the forming method further comprises: performing a third annealing process; the third The annealing process includes a spike annealing process; parameters of the spike annealing process include: 850 degrees Celsius to 1000 degrees Celsius. 9. The method for forming a semiconductor structure according to claim 6, wherein the substrate further includes a second region, the dielectric layer is also located on the surface of the substrate in the second region, and the dummy gate opening is also located in the second region. In the dielectric layer of the second region, the source-drain doped region is also located in the substrate on both sides of the dummy gate opening in the second region; the gate dielectric layer is also located at the bottom of the dummy gate opening in the second region; the gate dielectric is formed After forming the first sacrificial layer and before forming the first sacrificial layer, the forming method further includes: forming a second work function film at the bottom of the dummy gate openings in the first region and the second region. 10. The method for forming a semiconductor structure according to claim 9, wherein the second region is used to form a PMOS transistor; the material of the second work function film includes titanium nitride. 11. The method for forming a semiconductor structure according to claim 9, wherein after forming the metal silicide layer and before forming the first work function layer, the forming method comprises: forming an interposer in the contact hole The plug is filled with the dummy gate opening; after removing the second sacrificial layer and the first sacrificial layer, the second work function film in the first region is removed, and a second work function film is formed at the bottom of the dummy gate opening in the second region layer. 12. The method for forming a semiconductor structure according to claim 1, wherein after forming the first work function layer, the forming method comprises: forming a gate layer in the dummy gate opening, the gate The electrode layer is filled with dummy gate openings. 13. A semiconductor structure, characterized in that it is formed by the method for forming a semiconductor structure according to any one of claims 1 to 12; the semiconductor structure comprises: A substrate, the substrate includes a first region, the substrate surface of the first region has a dielectric layer, the dielectric layer of the first region has dummy gate openings, and the substrate on both sides of the dummy gate opening has source-drain doping regions in the substrate , and the dielectric layer covers the surface of the source-drain doped region; A contact hole located in the dielectric layer, the bottom of the contact hole exposes the top surface of the source-drain doped region; a metal silicide layer on top of the source-drain doped region at the bottom of the contact hole; A first work function layer located at the bottom of the dummy gate opening. 14. The semiconductor structure according to claim 13, wherein the first region is used to form an NMOS transistor, and the material of the first work function layer comprises titanium aluminum. 15. The semiconductor structure according to claim 13, wherein the substrate further comprises a second region, the dielectric layer is also located on the surface of the substrate in the second region, and the dummy gate opening is also located in the dielectric layer of the second region. In the layer, the source-drain doped region is also located in the substrate on both sides of the dummy gate opening in the second region. 16. The semiconductor structure according to claim 15, further comprising: a gate dielectric layer located at the bottom of the dummy gate opening in the first region and the dummy gate opening in the second region; The second work function layer; the second region is used to form a PMOS transistor, and the material of the second work function layer includes titanium nitride. 17. The semiconductor structure according to claim 13, further comprising: a plug located on the surface of the metal silicide layer in the contact hole, the plug filling the contact hole; A gate layer on the surface of the first work function layer at the bottom of the gate opening, the gate layer is filled with dummy gate openings.