CN111180521B - A semiconductor structure and manufacturing method for reducing switching loss - Google Patents

Abstract

The invention relates to a semiconductor structure capable of reducing switching loss and a manufacturing method thereof. The semiconductor comprises a drain electrode, a first conductive type substrate and a first conductive type epitaxial layer which are sequentially stacked from bottom to top; forming a plurality of second conductivity type body regions in the first conductivity type epitaxial layer, wherein the plurality of second conductivity type body regions are distributed at intervals; heavily doping in the second conductive type body region to form a first conductive type second source region, and heavily doping in the second conductive type body region at one side of the first conductive type second source region to form a first conductive type first source region; a control gate structure is arranged between the adjacent first conductive type first source region and the first conductive type second source region; a virtual grid structure is arranged on one side of the first conductive type second source region far away from the first conductive type first source region; depositing an insulating medium layer on the upper surface of the semiconductor structure for reducing the switching loss; and forming a connecting hole downwards from the upper surface of the insulating medium layer at the middle position of the first conductive type first source region, wherein the connecting hole downwards extends into the first conductive type first source region.

Description

A semiconductor structure and manufacturing method for reducing switching loss

Technical Field

The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a semiconductor structure and a manufacturing method for reducing switching loss.

Background technique

As we all know, in the application of MOS device products, the power loss of the device itself is composed of conduction loss and switching loss. In the high-voltage and high-frequency working environment, the power loss is mainly switching loss, and the switching loss is mainly determined by the parasitic capacitance of the device.

In conventional design, in order to reduce the switching loss of the device in a high-voltage and high-frequency working environment, that is, to reduce the parasitic capacitance of the device, the characteristic on-resistance Rsp of the device will increase, that is, the conduction loss will increase;

As shown in Figure 12, taking the existing N-type super junction planar gate MOS device as an example, there is a gate oxide layer under the control gate. The width of the existing structure control gate is relatively wide, and the overlapping area with the first source region and the second conductive type body region is relatively wide. The overlapping area forms CgsN+ and CgsP of the MOS device input capacitance Ciss respectively. The overlapping area between the conductive polysilicon and the P-type body region 05 is a conductive channel, which is an important component of the device input capacitance Ciss. Ciss=Cgs+Cgd. When the overlapping area is wider, the input capacitance of the product will increase, and then Qg will also increase, which will cause the switching loss of the device to increase, affecting the quality factor of the product.

Summary of the invention

The purpose of the invention is to overcome the problems of excessive gate charge and excessive device switching loss in the prior art, and to provide a semiconductor structure and a manufacturing method thereof for reducing switching loss. The device manufacturing method is compatible with existing semiconductor processes.

To achieve the above technical objectives, the technical solution of the present invention is: as a first aspect of the present invention, a semiconductor structure for reducing switching loss is provided, characterized in that it includes a drain, a first conductive type substrate and a first conductive type epitaxial layer stacked in sequence from bottom to top;

A plurality of second conductivity type body regions are formed in the first conductivity type epitaxial layer, the plurality of second conductivity type body regions are spaced apart, and each second conductivity type body region extends downward from the upper surface of the first conductivity type epitaxial layer; the second conductivity type body region is heavily doped to form a first conductivity type second source region, and the second conductivity type body region on one side of the first conductivity type second source region is heavily doped to form a first conductivity type first source region;

A control gate structure is provided between adjacent first conductive type first source regions and first conductive type second source regions; a dummy gate structure is provided on a side of the first conductive type second source region away from the first conductive type first source region;

An insulating dielectric layer is deposited on the upper surface of the semiconductor structure for reducing switching loss; a connection hole is formed downward from the upper surface of the insulating dielectric layer at the middle position of the first conductive type first source region, the connection hole extends downward to the first conductive type first source region, and finally enters the second conductive type body region;

The connection hole is filled with metal, and the metal also covers the surface of the insulating dielectric layer to form a source metal layer.

Optionally, for an N-type power semiconductor device, the first conductivity type is N-type conductivity, and the second conductivity type is P-type conductivity; for a P-type power semiconductor device, the first conductivity type is P-type conductivity, and the second conductivity type is N-type conductivity.

Optionally, the control gate structure and the dummy gate structure are both planar gate structures;

The gate oxide layer of the control gate structure is arranged at the upper surface of the second conductive type body region between the first conductive type first source region and the first conductive type second source region; the gate conductive polysilicon of the control gate structure is arranged on the gate oxide layer of the control gate structure;

The gate oxide layer of the dummy gate structure is arranged on a surface of the first conductive type second source region on a side away from the first conductive type first source region; the gate conductive polysilicon of the dummy gate structure is arranged on the gate oxide layer of the dummy gate structure.

Optionally, the control gate structure is a trench gate structure, and the dummy gate structure is a planar gate structure;

A control gate trench is provided in the second conductive type body region between the first conductive type first source region and the first conductive type second source region; the control gate trench is filled with gate conductive polysilicon of the control gate structure; and a gate oxide layer of the control gate structure is provided between the gate conductive polysilicon of the control gate structure and the inner wall of the control gate trench;

The gate oxide layer of the dummy gate structure is arranged on a surface of the first conductive type second source region on a side away from the first conductive type first source region; the gate conductive polysilicon of the dummy gate structure is arranged on the gate oxide layer of the dummy gate structure.

Optionally, both the control gate structure and the dummy gate structure are trench gate structures;

A control gate trench is provided in the second conductive type body region between the first conductive type first source region and the first conductive type second source region; the control gate trench is filled with gate conductive polysilicon of the control gate structure; and a gate oxide layer of the control gate structure is provided between the gate conductive polysilicon of the control gate structure and the inner wall of the control gate trench;

A virtual gate trench is opened in the first conductive type epitaxial layer on the side of the first conductive type second source region away from the first conductive type first source region; the virtual gate trench is filled with gate conductive polysilicon of the virtual gate structure; and a gate oxide layer of the virtual gate structure is provided between the gate conductive polysilicon of the virtual gate structure and the inner wall of the virtual gate trench.

Optionally, the control gate structure is a planar gate structure, and the dummy gate structure is a trench gate structure;

The gate oxide layer of the control gate structure is arranged at the upper surface of the second conductive type body region between the first conductive type first source region and the first conductive type second source region; the gate conductive polysilicon of the control gate structure is arranged on the gate oxide layer of the control gate structure;

A virtual gate trench is opened in the first conductive type epitaxial layer on the side of the first conductive type second source region away from the first conductive type first source region; the virtual gate trench is filled with gate conductive polysilicon of the virtual gate structure; and a gate oxide layer of the virtual gate structure is provided between the gate conductive polysilicon of the virtual gate structure and the inner wall of the virtual gate trench.

Optionally, a gate driving voltage is applied to the control gate structure, a high potential is applied to the dummy gate structure, and the dummy gate structure, the first conductive type second source region and the first conductive type epitaxial layer form an enhancement MOSFET.

Optionally, a gate driving voltage is applied to the control gate structure, a zero potential is applied to the dummy gate structure, and the dummy gate structure, the first conductive type second source region and the first conductive type epitaxial layer form a depletion-type MOSFET.

Optionally, the width of the control gate structure is smaller than the width of the dummy gate structure.

As a second aspect of the present invention, a method for manufacturing a semiconductor structure with reduced switching loss is provided, comprising the following steps:

Step 1: providing a first conductive type substrate, and growing a first conductive type epitaxial layer on the first conductive type substrate;

Step 2: selectively etching the first conductive type epitaxial layer to form a plurality of deep trenches extending downward from the upper surface of the first conductive type epitaxial layer, wherein the plurality of deep trenches are spaced apart;

Step 3: filling the deep trench with second conductivity type silicon to form a second conductivity type column;

Step 4: injecting second conductivity type impurities into the upper end of the second conductivity type column and annealing to form a second conductivity type body region;

Step 5: thermally growing a gate oxide layer on the control gate region and the dummy gate region and depositing gate conductive polysilicon, and forming a control gate structure and a dummy gate structure respectively after selective etching;

Step 6: heavily doping the second conductivity type body region to form a first conductivity type second source region after activation; heavily doping the second conductivity type body region on one side of the first conductivity type second source region to form a first conductivity type first source region; so that the control gate structure is located between the adjacent first conductivity type first source region and the first conductivity type second source region, and the dummy gate structure is located on a side of the first conductivity type second source region away from the first conductivity type first source region;

Step seven: depositing an insulating dielectric layer on the upper surface of the semiconductor structure for reducing switching losses; opening a connection hole downward from the upper surface of the insulating dielectric layer at the middle position of the first source region of the first conductive type, the connection hole extending downward to the first source region of the first conductive type, and finally entering the second conductive type body region; filling the connection hole with metal, the metal also covering the surface of the insulating dielectric layer to form a source metal layer.

From the above, it can be seen that the semiconductor structure and manufacturing method for reducing switching loss provided by the present invention have the following advantages compared with the prior art:

1) As shown in FIG. 12, a traditional planar gate super junction power MOSFET is shown. The device only has a control gate, and a gate oxide layer is provided below the control gate. The width of the control gate of the existing structure is relatively wide, and the overlapping area with the first source region and the second conductive type body region is relatively wide. The overlapping area respectively forms CgsN+ and CgsP of the MOS device input capacitance Ciss. The overlapping area between the conductive polysilicon and the P-type body region is a conductive channel, which is an important component of the device input capacitance Ciss. Ciss=Cgs+Cgd. When the overlapping area is relatively wide, the input capacitance of the product will be increased. The present invention greatly reduces the width of the control gate by adding a virtual gate with a high potential, and significantly reduces the overlapping area between the control gate and the second conductive type body region, and finally eliminates Cgd, i.e., Miller capacitance, which significantly increases the switching speed of the device, eliminates the hidden danger of gate voltage oscillation on the Miller platform, and suppresses the generation of EMI. As shown in FIG19 , it is a comparison diagram of the turn-on waveforms of the structure of the present invention and the traditional structure when performing a resistive switch test. As shown in FIG20 , it is a comparison diagram of the turn-off waveforms of the structure of the present invention and the traditional structure when performing a resistive switch test. It can be clearly seen from the figure that under the same current conditions, the structure of the present invention has an extremely fast switching speed compared with the traditional structure, and there is almost no Miller platform, which has an absolute advantage.

2) The structure of the present invention does not affect the DC parameters of the device. As shown in Figure 16, it is a current path diagram when the device is turned on when the control gate and the virtual gate of the present invention are both trench gates. The current first flows through the side wall of the virtual gate, then passes through the first source region, then flows through the bottom of the trench of the control gate, and then flows through the second source region. Finally, the current enters the source metal. Compared with the traditional structure, the current has an additional path of flowing through the bottom of the trench of the control gate. Since the channel resistance in the superjunction device can be ignored, the on-resistance of the structure of the present invention is equivalent to that of the traditional structure. As shown in Figure 17, it is a potential distribution diagram of the device when the control gate and the virtual gate of the present invention are both trench gates when it is subjected to a withstand voltage, and as shown in Figure 18, it is a potential distribution diagram of the traditional trench gate superjunction when it is subjected to a withstand voltage. There is no obvious difference in the potential distribution of the two.

2) The manufacturing process of the present invention is compatible with the existing process and reduces the manufacturing cost.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic cross-sectional view of a structure in which both the control gate and the virtual gate are planar gates (corresponding to Embodiment 1) according to the present invention.

FIG2 is a schematic cross-sectional view of a structure in which the control gate is a trench gate and the virtual gate is a planar gate (corresponding to Embodiment 2) according to the present invention.

FIG3 is a schematic cross-sectional view of a structure in which both the control gate and the dummy gate are trench gates (corresponding to Embodiment 3) according to the present invention.

FIG4 is a schematic cross-sectional view of a structure in which the virtual gate is a trench gate and the control gate is a planar gate (corresponding to Embodiment 4) according to the present invention.

FIG5 is a system application diagram of the device of the present invention.

FIG. 6 is a schematic cross-sectional view of the structure of forming an epitaxial layer.

FIG. 7 is a schematic cross-sectional view of a structure in which a deep trench is formed.

FIG. 8 is a schematic cross-sectional view of a structure in which a P-type column is formed.

FIG. 9 is a schematic cross-sectional view of a structure in which a P-type body region is formed.

FIG. 10 is a schematic cross-sectional view of the structure of forming a gate oxide layer.

FIG. 11 is a schematic cross-sectional view of the structure for forming a control gate and a dummy gate.

FIG. 12 is a schematic cross-sectional structural diagram of forming a first source region and a second source region.

FIG. 13 is a schematic cross-sectional view of a conventional structure.

FIG. 14 is a schematic cross-sectional view of a novel VDMOS (corresponding to Embodiment 5) in which the structure of the present invention is applied to a conventional VDMOS.

FIG. 15 is a schematic cross-sectional view of a novel IGBT (corresponding to Embodiment 6) in which the structure of the present invention is applied to a conventional IGBT.

FIG16 is a current path diagram of the device when the control gate and the dummy gate are both trench gates according to the present invention and the device is turned on.

FIG17 is a potential distribution diagram of the device under withstand voltage when both the control gate and the dummy gate are trench gates according to the present invention.

FIG. 18 is a diagram showing the potential distribution of a conventional trench gate super junction when subjected to a withstand voltage.

FIG. 19 is a comparison diagram of the turn-on waveforms of the structure of the present invention and the traditional structure when performing a resistive switch test.

FIG. 20 is a comparison diagram of the turn-off waveforms of the structure of the present invention and the traditional structure when performing a resistive switch test.

01—drain metal; 02—N-type silicon substrate; 03—N-type column; 04—P-type column; 05—P-type body region; 06—virtual gate trench 06; 07—control gate trench; 08—control gate; 09—virtual gate; 10—gate oxide layer; 11—insulating dielectric layer; 12—second source region; 13—first source region; 14—source metal layer; 15—P-type collector region; 16—N-type buffer layer; 17—collector metal; 18—second emitter region; 19—first emitter region; 20—emitter metal; 21—deep trench.

Detailed ways

In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings. The same parts are represented by the same figure numerals. It should be noted that the words "front", "rear", "left", "right", "up" and "down" used in the following description refer to the directions in the accompanying drawings. The words "inside" and "outside" used refer to the direction toward or away from the geometric center of a specific component, respectively.

A first aspect of the present invention provides a semiconductor structure for reducing switching losses, which includes the following embodiments. It should be explained that for N-type power semiconductor devices, the first conductivity type described in this document is N-type conductivity, and the second conductivity type is P-type conductivity; for P-type power semiconductor devices, the first conductivity type described in this document is P-type conductivity, and the second conductivity type is N-type conductivity.

Example 1

1 , a semiconductor structure for reducing switching losses is shown, taking an N-type planar superjunction power semiconductor device as an example, including a drain 01, an N-type substrate 02 and an N-type epitaxial layer 03 stacked in sequence from bottom to top; the material of the drain 01 is preferably metal, and the material of the N-type substrate 02 can be silicon.

A plurality of P-type columns 04 are provided in the N-type epitaxial layer 03 . The plurality of P-type columns 04 are distributed at intervals, and each of the P-type columns 04 extends downward from the upper surface of the N-type epitaxial layer 03 .

The upper end of the P-type column 04 forms a P-type body region 05 , the P-type body region 05 is heavily doped to form an N-type first source region 13 , and the P-type body regions 05 on both sides of the N-type first source region 13 are heavily doped to form an N-type second source region 12 .

A control gate structure 08 is provided between the adjacent N-type first source region 13 and the N-type second source region 12; and a dummy gate structure 09 is provided on the side of the N-type second source region 12 away from the N-type first source region 13. Specifically, the control gate structure 08 and the dummy gate structure 09 are both planar gate structures; wherein the control gate structure 08 and the dummy gate structure 09 both include a gate oxide layer 10 and gate conductive polysilicon. The gate oxide layer 10 of the control gate structure 08 is provided on the upper surface of the P-type body region 05 between the N-type first source region 13 and the N-type second source region 12; and the gate conductive polysilicon of the control gate structure 08 is provided on the gate oxide layer 10 of the control gate structure 08. The gate oxide layer 10 of the dummy gate structure 09 is provided on the side surface of the N-type second source region 12 (the surface of the N-type epitaxial layer 03); and the gate conductive polysilicon of the dummy gate structure 09 is provided on the gate oxide layer 10 of the dummy gate structure 09.

An insulating dielectric layer 11 is deposited on the upper surface of the semiconductor structure for reducing switching loss; a connection hole is formed downward from the upper surface of the insulating dielectric layer 11 at the middle position of the N-type first source region 13, and the connection hole extends downward to the N-type first source region 13 and finally enters the P-type body region 05;

The connection hole is filled with metal, and the metal also covers the surface of the insulating dielectric layer 11 to form a source metal layer 14 .

It should be explained that the width of the control gate structure 08 described above is smaller than that of the dummy gate structure 09 described above.

It can be understood from the above description and Figure 1 that a heavily doped N-type first source region 13 is formed below the control gate structure 08 on one side close to the connection hole, the N-type first source region 13 is on the surface of the P-type body region 05, and the N-type first source region 13 is electrically connected to the source metal layer 14; the heavily doped N-type second source region 12 is provided below the side of the control gate structure 08 away from the connection hole, that is, below both sides of the dummy gate structure 09; the N-type second source region 12 is on the upper surface of the P-type body region 05, and is not in contact with the first source region 13 and the N-type epitaxial layer 03.

Example 2

2 , a semiconductor structure for reducing switching losses is shown, taking an N-type planar superjunction power semiconductor device as an example, including a drain 01, an N-type substrate 02 and an N-type epitaxial layer 03 stacked in sequence from bottom to top; the material of the drain 01 is preferably metal, and the material of the N-type substrate 02 can be silicon.

A plurality of P-type columns 04 are provided in the N-type epitaxial layer 03 . The plurality of P-type columns 04 are distributed at intervals, and each of the P-type columns 04 extends downward from the upper surface of the N-type epitaxial layer 03 .

The upper end of the P-type column 04 forms a P-type body region 05 , the P-type body region 05 is heavily doped to form an N-type first source region 13 , and the P-type body regions 05 on both sides of the N-type first source region 13 are heavily doped to form an N-type second source region 12 .

A control gate structure 08 is provided between the adjacent N-type first source region 13 and the N-type second source region 12; a dummy gate structure 09 is provided on the side of the N-type second source region 12 away from the N-type first source region 13. Specifically, the control gate structure 08 is a trench gate structure, and the dummy gate structure 09 is a planar gate structure; that is, a control gate trench 07 is opened in the P-type body region 05 between the N-type first source region 13 and the N-type second source region 12; the control gate trench 07 is filled with the gate conductive polysilicon of the control gate structure 08; a gate oxide layer 10 of the control gate structure 08 is provided between the gate conductive polysilicon of the control gate structure 08 and the inner wall of the control gate trench 07; the gate oxide layer 10 of the dummy gate structure 09 is provided on the surface of one side of the N-type second source region 12; and the gate conductive polysilicon of the dummy gate structure 09 is provided on the gate oxide layer 10 of the dummy gate structure 09.

An insulating dielectric layer 11 is deposited on the upper surface of the semiconductor structure for reducing switching loss; a connection hole is formed downward from the upper surface of the insulating dielectric layer 11 at the middle position of the N-type first source region 13, and the connection hole extends downward to the N-type first source region 13 and finally enters the P-type body region 05;

The connection hole is filled with metal, and the metal also covers the surface of the insulating dielectric layer 11 to form a source metal layer 14 .

It should be explained that the width of the control gate structure 08 described above is smaller than that of the dummy gate structure 09 described above.

It can be understood from the above description and Figure 2 that the control gate trench 07 is located between the N-type first source region 13 and the N-type second source region 12, and the heavily doped N-type second source region 12 is provided on the side of the control gate structure 08 away from the connecting hole, that is, below the two sides of the dummy gate structure 09; the side walls on both sides of the control gate trench 07 are in contact with the N-type first source region 13 and the N-type second source region 12 respectively, and the gate oxide layer 10 covers the inner wall of the control gate trench 07.

Example 3

3 , a semiconductor structure for reducing switching losses is shown, taking an N-type planar superjunction power semiconductor device as an example, including a drain 01, an N-type substrate 02 and an N-type epitaxial layer 03 stacked in sequence from bottom to top; the material of the drain 01 is preferably metal, and the material of the N-type substrate 02 can be silicon.

A plurality of P-type columns 04 are provided in the N-type epitaxial layer 03 . The plurality of P-type columns 04 are distributed at intervals, and each of the P-type columns 04 extends downward from the upper surface of the N-type epitaxial layer 03 .

The upper end of the P-type column 04 forms a P-type body region 05 , the P-type body region 05 is heavily doped to form an N-type first source region 13 , and the P-type body regions 05 on both sides of the N-type first source region 13 are heavily doped to form an N-type second source region 12 .

A control gate structure 08 is provided between the adjacent N-type first source region 13 and the N-type second source region 12 ; and a dummy gate structure 09 is provided on a side of the N-type second source region 12 away from the N-type first source region 13 . Specifically, the control gate structure 08 and the dummy gate structure 09 are both trench gate structures; a control gate trench 07 is opened in the P-type body region 05 between the N-type first source region 13 and the N-type second source region 12; the control gate trench 07 is filled with gate conductive polysilicon of the control gate structure 08; a gate oxide layer 10 of the control gate structure 08 is provided between the gate conductive polysilicon of the control gate structure 08 and the inner wall of the control gate trench 07; a dummy gate trench 06 is opened in the N-type epitaxial layer 03 on one side of the N-type second source region 12; the dummy gate trench 06 is filled with gate conductive polysilicon of the dummy gate structure 09; and a gate oxide layer 10 of the dummy gate structure 09 is provided between the gate conductive polysilicon of the dummy gate structure 09 and the inner wall of the dummy gate trench 06.

An insulating dielectric layer 11 is deposited on the upper surface of the semiconductor structure for reducing switching loss; a connection hole is formed downward from the upper surface of the insulating dielectric layer 11 at the middle position of the N-type first source region 13, and the connection hole extends downward to the N-type first source region 13 and finally enters the P-type body region 05;

The connection hole is filled with metal, and the metal also covers the surface of the insulating dielectric layer 11 to form a source metal layer 14 .

It should be explained that the width of the control gate structure 08 described above is smaller than that of the dummy gate structure 09 described above.

It can be understood from the above description and Figure 3 that the control gate trench 07 is located between the N-type first source region 13 and the N-type second source region 12, and the heavily doped N-type second source region 12 is provided on the side of the control gate structure 08 away from the connecting hole, that is, on both sides of the dummy gate structure 09; the side walls on both sides of the control gate trench 07 are in contact with the N-type first source region 13 and the N-type second source region 12 respectively, and the dummy gate trench 06 is in contact with the N-type second source region 12; the gate oxide layer 10 covers the inner wall of the control gate trench 07.

Example 4

4 , a semiconductor structure for reducing switching losses is shown, taking an N-type planar superjunction power semiconductor device as an example, including a drain 01, an N-type substrate 02 and an N-type epitaxial layer 03 stacked in sequence from bottom to top; the material of the drain 01 is preferably metal, and the material of the N-type substrate 02 can be silicon.

A plurality of P-type columns 04 are provided in the N-type epitaxial layer 03 . The plurality of P-type columns 04 are distributed at intervals, and each of the P-type columns 04 extends downward from the upper surface of the N-type epitaxial layer 03 .

The upper end of the P-type column 04 forms a P-type body region 05 , the P-type body region 05 is heavily doped to form an N-type first source region 13 , and the P-type body regions 05 on both sides of the N-type first source region 13 are heavily doped to form an N-type second source region 12 .

A control gate structure 08 is provided between the adjacent N-type first source region 13 and the N-type second source region 12; a dummy gate structure 09 is provided on the side of the N-type second source region 12 away from the N-type first source region 13. Specifically, the control gate structure 08 is a planar gate structure, and the dummy gate structure 09 is a trench gate structure; the gate oxide layer 10 of the control gate structure 08 is provided on the upper surface of the P-type body region 05 between the N-type first source region 13 and the N-type second source region 12; the gate conductive polysilicon of the control gate structure 08 is provided on the gate oxide layer 10 of the control gate structure 08; a dummy gate trench 06 is provided in the N-type epitaxial layer 03 on one side of the N-type second source region 12; the gate conductive polysilicon of the dummy gate structure 09 is filled in the dummy gate trench 06; and the gate oxide layer 10 of the dummy gate structure 09 is provided between the gate conductive polysilicon of the dummy gate structure 09 and the inner wall of the dummy gate trench 06.

An insulating dielectric layer 11 is deposited on the upper surface of the semiconductor structure for reducing switching loss; a connection hole is formed downward from the upper surface of the insulating dielectric layer 11 at the middle position of the N-type first source region 13, and the connection hole extends downward to the N-type first source region 13 and finally enters the P-type body region 05;

The connection hole is filled with metal, and the metal also covers the surface of the insulating dielectric layer 11 to form a source metal layer 14 .

It should be explained that the width of the control gate structure 08 described above is smaller than that of the dummy gate structure 09 described above.

It can be understood from the above description and Figure 4 that a heavily doped N-type first source region 13 is formed below the control gate structure 08 on one side close to the connection hole, the N-type first source region 13 is on the surface of the P-type body region 05, and the N-type first source region 13 is electrically connected to the source metal layer 14; a heavily doped N-type second source region 12 is provided below the side of the control gate structure 08 away from the connection hole, and the virtual gate trench 06 is in contact with the N-type second source region 12; the N-type second source region 12 is on the upper surface of the P-type body region 05, and is not in contact with the first source region 13 and the N-type epitaxial layer 03.

Example 5

14 , a semiconductor structure for reducing switching losses is shown, taking an N-type planar VDMOS as an example, including a drain 01, an N-type substrate 02 and an N-type epitaxial layer 03 stacked in sequence from bottom to top; the material of the drain 01 is preferably metal, and the material of the N-type substrate 02 can be silicon.

A plurality of P-type body regions 05 are formed in the N-type epitaxial layer 03, and the plurality of P-type body regions 05 are distributed at intervals, and each of the P-type body regions 05 extends downward from the upper surface of the N-type epitaxial layer 03; the P-type body regions 05 are heavily doped to form an N-type first source region 13, and the P-type body regions 05 on both sides of the N-type first source region 13 are heavily doped to form an N-type second source region 12.

A control gate structure 08 is provided between the adjacent N-type first source region 13 and the N-type second source region 12; and a dummy gate structure 09 is provided on the side of the N-type second source region 12 away from the N-type first source region 13. Specifically, the control gate structure 08 and the dummy gate structure 09 are both planar gate structures; wherein the control gate structure 08 and the dummy gate structure 09 both include a gate oxide layer 10 and gate conductive polysilicon. The gate oxide layer 10 of the control gate structure 08 is provided on the upper surface of the P-type body region 05 between the N-type first source region 13 and the N-type second source region 12; and the gate conductive polysilicon of the control gate structure 08 is provided on the gate oxide layer 10 of the control gate structure 08. The gate oxide layer 10 of the dummy gate structure 09 is provided on the side surface of the N-type second source region 12 (the surface of the N-type epitaxial layer 03); and the gate conductive polysilicon of the dummy gate structure 09 is provided on the gate oxide layer 10 of the dummy gate structure 09.

An insulating dielectric layer 11 is deposited on the upper surface of the semiconductor structure for reducing switching loss; a connection hole is formed downward from the upper surface of the insulating dielectric layer 11 at the middle position of the N-type first source region 13, and the connection hole extends downward to the N-type first source region 13 and finally enters the P-type body region 05;

The connection hole is filled with metal, and the metal also covers the surface of the insulating dielectric layer 11 to form a source metal layer 14 .

It should be explained that the width of the control gate structure 08 described above is smaller than that of the dummy gate structure 09 described above.

It can be understood from the above description and Figure 1 that a heavily doped N-type first source region 13 is formed below the control gate structure 08 on one side close to the connection hole, the N-type first source region 13 is on the surface of the P-type body region 05, and the N-type first source region 13 is electrically connected to the source metal layer 14; the heavily doped N-type second source region 12 is provided below the side of the control gate structure 08 away from the connection hole, that is, below both sides of the dummy gate structure 09; the N-type second source region 12 is on the upper surface of the P-type body region 05, and is not in contact with the first source region 13 and the N-type epitaxial layer 03.

Example 6

15 , a semiconductor structure for reducing switching losses is shown, taking IGBT as an example, including a collector electrode metal 17 , a P-type collector region 15 , an N-type buffer layer 16 and an N-type epitaxial layer 03 stacked in sequence from bottom to top.

A plurality of P-type body regions 05 are formed in the N-type epitaxial layer 03, and the plurality of P-type body regions 05 are distributed at intervals, and each of the P-type body regions 05 extends downward from the upper surface of the N-type epitaxial layer 03; the P-type body regions 05 are heavily doped to form an N-type first emitter region 19, and the P-type body regions 05 on both sides of the N-type first emitter region 19 are heavily doped to form an N-type second emitter region 18.

A control gate structure 08 is provided between the adjacent N-type first emitter region 19 and the N-type second emitter region 18; and a dummy gate structure 09 is provided on the side of the N-type second emitter region 18 away from the N-type first emitter region 19. Specifically, the control gate structure 08 and the dummy gate structure 09 are both planar gate structures; wherein the control gate structure 08 and the dummy gate structure 09 both include a gate oxide layer 10 and gate conductive polysilicon. The gate oxide layer 10 of the control gate structure 08 is provided on the upper surface of the P-type body region 05 between the N-type first emitter region 19 and the N-type second emitter region 18; and the gate conductive polysilicon of the control gate structure 08 is provided on the gate oxide layer 10 of the control gate structure 08. The gate oxide layer 10 of the dummy gate structure 09 is provided on the side surface of the N-type second emitter region 18 (the surface of the N-type epitaxial layer 03); and the gate conductive polysilicon of the dummy gate structure 09 is provided on the gate oxide layer 10 of the dummy gate structure 09.

An insulating dielectric layer 11 is deposited on the upper surface of the semiconductor structure for reducing switching loss; a connection hole is formed downward from the upper surface of the insulating dielectric layer 11 at the middle position of the N-type first emitter region 19, and the connection hole extends downward into the N-type first emitter region 19;

The connection hole is filled with metal, and the metal also covers the surface of the insulating dielectric layer 11 to form an emitter metal 20 .

It should be explained that the width of the control gate structure 08 described above is smaller than that of the dummy gate structure 09 described above.

It can be understood from the above description and Figure 1 that a heavily doped N-type first emitter region 19 is formed below the control gate structure 08 on one side close to the connecting hole, the N-type first emitter region 19 is on the surface of the P-type body region 05, and the N-type first emitter region 19 is electrically connected to the emitter metal 20; the heavily doped N-type second emitter region 18 is provided below the side of the control gate structure 08 away from the connecting hole, that is, below both sides of the dummy gate structure 09; the N-type second emitter region 18 is on the upper surface of the P-type body region 05, and has no contact with the first emitter region 19 and the N-type epitaxial layer 03.

As a second aspect of the present invention, a method for manufacturing a semiconductor structure with reduced switching loss comprises the following steps:

Step 1: providing a first conductive type substrate, and growing a first conductive type epitaxial layer on the first conductive type substrate;

Step 2: selectively etching the first conductive type epitaxial layer to form a plurality of deep trenches 21 extending downward from the upper surface of the first conductive type epitaxial layer, wherein the plurality of deep trenches 21 are spaced apart from each other;

Step 3: Filling the deep trench 21 with silicon of the second conductivity type to form a column of the second conductivity type;

Step 4: injecting second conductivity type impurities into the upper end of the second conductivity type column and annealing to form a second conductivity type body region;

Step 5: thermally grow a gate oxide layer 10 on the control gate region and the dummy gate region and deposit gate conductive polysilicon, and selectively etch to form a control gate structure 08 and a dummy gate structure 09 respectively;

Step 6: heavily doping the second conductivity type body region to form the first conductivity type second source region 12 after activation; heavily doping the second conductivity type body region on one side of the first conductivity type second source region 12 to form the first conductivity type first source region 13; so that the control gate structure 08 is located between the adjacent first conductivity type first source region 13 and the first conductivity type second source region 12, and the dummy gate structure 09 is located on the side of the first conductivity type second source region 12 away from the first conductivity type first source region 13;

Step seven: depositing an insulating dielectric layer 11 on the upper surface of the semiconductor structure for reducing switching losses; opening a connection hole downward from the upper surface of the insulating dielectric layer 11 at the middle position of the first conductive type first source region 13, and extending downward into the first conductive type first source region 13; filling the connection hole with metal, and the metal also covers the surface of the insulating dielectric layer 11 to form a source metal layer 14.

Based on the above embodiments, the working principle of the present invention is:

5 , for Embodiments 1 to 4, the dummy gate structure 09 , the N-type second source region 12 and the N-type epitaxial layer 03 form a first enhancement mode MOS; and the control gate structure 08 , the N-type first source region 13 and the N-type second source region 12 form a second enhancement mode MOS.

When the device is working, a gate driving voltage is applied to the control gate structure 08, a high potential is applied to the dummy gate structure 09, and the dummy gate structure 09, the N-type second source region 12 and the N-type epitaxial layer 03 form an enhancement MOSFET.

When a zero potential is applied to the control gate structure 08, the second enhancement MOS is turned off, and the high potential of the virtual gate structure 09 causes the first enhancement MOS to be temporarily turned on, which causes the potential of the N-type second source region 12 to gradually rise; when the potential of the virtual gate structure 09 is higher than the potential of the N-type second source region 12 by exactly one threshold value of the first enhancement MOS, the first enhancement MOS enters the off state and remains in the off state throughout the entire period.

When a high potential is applied to the control gate structure 08, the second enhancement MOS is turned on, which causes the potential of the N-type second source region 12 to drop rapidly to zero potential. When the potential of the virtual gate structure 09 is higher than the potential of the N-type second source region 12 by a threshold of the first enhancement MOS, the first enhancement MOS enters the turn-on state and the entire device enters the on state.

Referring to Fig. 16, it is a current path diagram when the device is turned on when both the control gate structure 08 and the dummy gate structure 09 of the present invention are trench gates. The current first flows through the sidewall of the dummy gate junction trench, then passes through the N-type first source region 13, then flows through the bottom of the control gate trench 07, and then flows through the N-type second source region 12. Finally, the current enters the source metal. Compared with the traditional structure, the current has an additional path flowing through the bottom of the control gate trench 07. Since the channel resistance in the super junction device can be ignored, the on-resistance of the structure of the present invention is equivalent to that of the traditional structure. As shown in Fig. 17, it is a potential distribution diagram of the device when the control gate and the dummy gate of the present invention are both trench gates when the device is subjected to a withstand voltage, and as shown in Fig. 18, it is a potential distribution diagram of the traditional trench gate super junction when it is subjected to a withstand voltage. There is no obvious difference in the potential distribution of the two.

As shown in Figure 13, a traditional planar gate super junction power MOSFET is shown. The device only has a control gate, and a gate oxide layer is provided below the control gate. The width of the control gate of the existing structure is relatively wide, and the overlapping area with the first source region 13 and the second conductive type body region is relatively wide. The overlapping area respectively forms CgsN+ and CgsP of the MOS device input capacitance Ciss. The overlapping area between the conductive polysilicon and the P-type body region 05 is a conductive channel, which is an important component of the device input capacitance Ciss. Ciss=Cgs+Cgd. When the overlapping area is relatively wide, the input capacitance of the product will be increased. The present invention greatly reduces the width of the control gate by adding a virtual gate with a high potential, and significantly reduces the overlapping area between the control gate and the second conductive type body region, and finally eliminates Cgd, i.e., Miller capacitance. This significantly increases the switching speed of the device, eliminates the hidden danger of gate voltage oscillation on the Miller platform, and suppresses the generation of EMI. As shown in FIG19 , it is a comparison diagram of the turn-on waveforms of the structure of the present invention and the traditional structure when performing a resistive switch test. As shown in FIG20 , it is a comparison diagram of the turn-off waveforms of the structure of the present invention and the traditional structure when performing a resistive switch test. It can be clearly seen from the figure that under the same current conditions, the structure of the present invention has an extremely fast switching speed compared with the traditional structure, and there is almost no Miller platform, which has an absolute advantage.

Those skilled in the art should understand that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit of the present invention should be included in the protection scope of the present invention.

Claims (8)

1. A semiconductor structure for reducing switching loss is characterized by comprising a drain electrode (01), a first conductive type substrate and a first conductive type epitaxial layer which are sequentially stacked from bottom to top;

Forming a plurality of second conductivity type body regions in the first conductivity type epitaxial layer, wherein the second conductivity type body regions are distributed at intervals, and each second conductivity type body region extends downwards from the upper surface of the first conductivity type epitaxial layer; the second conductive type body region is heavily doped to form a first conductive type second source region (12), and the second conductive type body region at one side of the first conductive type second source region (12) is heavily doped to form a first conductive type first source region (13);

A control gate structure (08) is arranged between the adjacent first conductive type first source region (13) and the first conductive type second source region (12); a virtual grid structure (09) is arranged on one side of the first conductive type second source region (12) away from the first conductive type first source region (13);

Depositing an insulating medium layer (11) on the upper surface of the semiconductor structure for reducing the switching loss; forming a connecting hole downwards from the upper surface of the insulating medium layer (11), wherein the connecting hole downwards extends into the first conductive type first source region (13) and finally enters the second conductive type body region;

Filling metal in the connecting hole, wherein the metal also covers the surface of the insulating medium layer (11) to form a source metal layer (14);

-applying a gate drive voltage on the control gate structure (08), a zero potential being applied on the dummy gate structure (09), the first conductivity type second source region (12) and the first conductivity type epitaxial layer forming a depletion MOSFET;

the width of the control gate structure (08) is smaller than the width of the dummy gate structure (09).

2. The switching loss reducing semiconductor structure of claim 1 wherein for an N-type power semiconductor device, said first conductivity type is N-type conductivity and said second conductivity type is P-type conductivity; for a P-type power semiconductor device, the first conductivity type is P-type conductivity and the second conductivity type is N-type conductivity.

3. The switching loss reducing semiconductor structure of claim 1, wherein the control gate structure (08) and dummy gate structure (09) are planar gate structures;

-a gate oxide layer (10) of said control gate structure (08) at an upper surface of said second conductivity type body region between said first conductivity type first source region (13) and first conductivity type second source region (12); the grid conductive polysilicon of the control grid structure (08) is arranged on the grid oxide layer (10) of the control grid structure (08);

the gate oxide layer (10) of the virtual gate structure (09) is arranged on one side surface of the first conductive type second source region (12) far away from the first conductive type first source region (13); the grid conductive polysilicon of the virtual grid structure (09) is arranged on the grid oxide layer (10) of the virtual grid structure (09).

4. The semiconductor structure for reducing switching losses according to claim 1, wherein the control gate structure (08) is a trench gate structure and the dummy gate structure (09) is a planar gate structure;

-providing a control gate trench (07) in said second conductivity type body region between said first conductivity type first source region (13) and first conductivity type second source region (12); the control gate trench (07) is filled with gate conductive polysilicon of the control gate structure (08); a gate oxide layer (10) of the control gate structure (08) is arranged between the gate conductive polysilicon of the control gate structure (08) and the inner wall of the control gate trench (07);

the gate oxide layer (10) of the virtual gate structure (09) is arranged on one side surface of the first conductive type second source region (12) far away from the first conductive type first source region (13); the grid conductive polysilicon of the virtual grid structure (09) is arranged on the grid oxide layer (10) of the virtual grid structure (09).

5. The switching loss reducing semiconductor structure of claim 1, wherein the control gate structure (08) and the dummy gate structure (09) are trench gate structures;

-providing a control gate trench (07) in said second conductivity type body region between said first conductivity type first source region (13) and first conductivity type second source region (12); the control gate trench (07) is filled with gate conductive polysilicon of the control gate structure (08); a gate oxide layer (10) of the control gate structure (08) is arranged between the gate conductive polysilicon of the control gate structure (08) and the inner wall of the control gate trench (07);

A virtual gate groove (06) is arranged in the first conductive type epitaxial layer at one side of the first conductive type second source region (12) far away from the first conductive type first source region (13); the virtual gate groove (06) is filled with grid conductive polysilicon of the virtual gate structure (09); and a gate oxide layer (10) of the virtual gate structure (09) is arranged between the gate conductive polysilicon of the virtual gate structure (09) and the inner wall of the virtual gate groove (06).

6. The semiconductor structure for reducing switching losses according to claim 1, wherein the control gate structure (08) is a planar gate structure and the dummy gate structure (09) is a trench gate structure;

-a gate oxide layer (10) of said control gate structure (08) at an upper surface of said second conductivity type body region between said first conductivity type first source region (13) and first conductivity type second source region (12); the grid conductive polysilicon of the control grid structure (08) is arranged on the grid oxide layer (10) of the control grid structure (08);

A virtual gate groove (06) is arranged in the first conductive type epitaxial layer at one side of the first conductive type second source region (12) far away from the first conductive type first source region (13); the virtual gate groove (06) is filled with grid conductive polysilicon of the virtual gate structure (09); and a gate oxide layer (10) of the virtual gate structure (09) is arranged between the gate conductive polysilicon of the virtual gate structure (09) and the inner wall of the virtual gate groove (06).

7. A semiconductor structure for reducing switching losses according to any one of claims 1 to 6, characterized in that a gate driving voltage is applied to the control gate structure (08), a high potential is applied to the dummy gate structure (09), and the dummy gate structure (09), the first conductivity type second source region (12) and the first conductivity type epitaxial layer form an enhancement MOSFET.

8. The manufacturing method of the semiconductor structure for reducing the switching loss is characterized by comprising the following steps of:

Step one: providing a first conductive type substrate, and growing a first conductive type epitaxial layer on the first conductive type substrate;

Step two: selectively etching the first conductive type epitaxial layer to form a plurality of deep trenches (21) extending downwards from the upper surface of the first conductive type epitaxial layer, wherein the plurality of deep trenches (21) are distributed at intervals;

Step three: filling a second conductive type semiconductor into the deep trench (21) to form a second conductive type column;

Step four: injecting second conductivity type impurities into the upper end parts of the second conductivity type columns and annealing to form second conductivity type body regions;

Step five: forming a gate oxide layer (10) by thermal growth, depositing gate conductive polysilicon, and forming a control gate structure (08) and a virtual gate structure (09) respectively after selective etching;

Step six: heavily doping in the second conductivity type body region, forming a first conductivity type second source region (12) after activation; heavily doping in a second conductivity type body region on one side of the first conductivity type second source region (12) to form a first conductivity type first source region (13); such that the control gate structure (08) is located between adjacent first conductivity type first source regions (13) and first conductivity type second source regions (12), the dummy gate structure (09) being located on a side of the first conductivity type second source regions (12) remote from the first conductivity type first source regions (13);

Step seven: depositing an insulating medium layer (11) on the upper surface of the semiconductor structure for reducing the switching loss; a connecting hole is formed downwards from the upper surface of the insulating medium layer (11) at the middle position of the first conductive type first source region (13), and extends downwards into the first conductive type first source region (13) and finally enters the second conductive type body region; and filling metal in the connecting hole, and forming a source metal layer (14) on the surface of the insulating medium layer (11) by covering the metal.