CN111177990A

CN111177990A - Method, device and system for realizing logic optimization in FPGA (field programmable Gate array) logic synthesis

Info

Publication number: CN111177990A
Application number: CN201911375726.2A
Authority: CN
Inventors: 刘奎; 王宁; 王维; 王勇麟; 宋宁; 刘建华
Original assignee: Gowin Semiconductor Corp
Current assignee: Gowin Semiconductor Corp
Priority date: 2019-12-27
Filing date: 2019-12-27
Publication date: 2020-05-19
Anticipated expiration: 2039-12-27
Also published as: CN111177990B

Abstract

The invention discloses a method, a device and a system for realizing logic optimization in FPGA logic synthesis, which comprise the following steps: the back-end processing device judges whether a logic optimization result in the synthesized netlist is matched with the back-end requirement or not after reading the synthesized netlist; if not, generating logic optimization guide information to be provided for the front-end logic synthesis device; when the logic optimization guide information is obtained, the front-end logic synthesis device executes logic optimization operation on a logic optimization result in the synthesized netlist according to the logic optimization guide information to obtain a target logic optimization result, and generates a new synthesized netlist according to the target logic optimization result, wherein the synthesized netlist generated by the front-end logic synthesis device is used for being provided for the back-end processing device. Therefore, the invention can guide the logic optimization direction in FPGA logic synthesis for many times through the back-end requirement, thereby not only improving the universality and the optimization efficiency of the logic optimization control mode, but also improving the matching degree of the result after logic optimization and the back-end requirement.

Description

Method, device and system for realizing logic optimization in FPGA (field programmable Gate array) logic synthesis

Technical Field

The invention relates to the technical field of FPGA (field programmable gate array), in particular to a method, a device and a system for realizing logic optimization in FPGA logic synthesis.

Background

The Design process of an FPGA (Field-Programmable Gate Array) is a process of developing an FPGA chip by using EDA (electronic Design Automation) development software and a programming tool. The development process of the EDA development software mainly comprises a front-end logic synthesis process and a back-end layout and wiring process, a time sequence analysis process, a power consumption analysis process and the like, logic optimization is an important means for improving the front-end logic synthesis quality, and the purposes of reducing logic resources, logic levels, power consumption and the like can be achieved through corresponding operations.

Practice shows that the current logic optimization modes all adopt universal logic optimization algorithms, the universal logic optimization algorithms cannot meet logic optimization requirements designed by different users, the universality is poor, and meanwhile, the problem that the matching degree of the logic optimization results and rear-end requirements is low exists.

Disclosure of Invention

The technical problem to be solved by the invention is to provide a method, a device and a system for realizing logic optimization in FPGA logic synthesis, which can guide logic optimization through a back-end requirement, have high universality and improve the matching degree of a logic optimization result and the back-end requirement.

In order to solve the above technical problem, a first aspect of the embodiments of the present invention discloses a method for implementing logic optimization in FPGA logic synthesis, where the method includes:

the back-end processing device reads the synthesized netlist generated by the front-end logic synthesis device and judges whether a logic optimization result in the synthesized netlist is matched with a predetermined back-end requirement or not; when the logic optimization result in the synthesized netlist is judged to be not matched with the back-end requirement, logic optimization guide information is generated and used for being provided for the front-end logic synthesis device;

when the logic optimization guide information generated by the back-end processing device is acquired, the front-end logic synthesis device executes logic optimization operation on a logic optimization result in the synthesized netlist according to the logic optimization guide information to obtain a target logic optimization result, and generates a new synthesized netlist according to the target logic optimization result;

wherein the synthesized netlist generated by the front-end logic synthesis device is used for providing to the back-end processing device.

As an optional implementation manner, in the first aspect of the embodiment of the present invention, the logic optimization guidance information includes at least one location area in the synthesized netlist on which a logic optimization operation needs to be performed and/or a logic optimization direction of each location area in the at least one location area in the synthesized netlist on which a logic optimization operation needs to be performed.

As an optional implementation manner, in the first aspect of the embodiment of the present invention, the performing, by the front-end logic synthesis apparatus, a logic optimization operation on the logic optimization result in the synthesized netlist according to the logic optimization guide information to obtain a target logic optimization result includes:

when the logic optimization guidance information comprises the logic optimization direction of each position area in at least one position area which needs to execute logic optimization operation in the synthesized netlist, the front-end logic synthesis device screens a logic optimization algorithm matched with the logic optimization direction of each position area from a predetermined logic optimization algorithm set;

and the front-end logic comprehensive device executes logic optimization operation on the position area according to the screened logic optimization algorithm matched with the logic optimization direction of each position area to obtain a target logic optimization result.

As an optional implementation manner, in the first aspect of the embodiment of the present invention, the position area is determined by the back-end processing apparatus based on at least one of a power consumption requirement, a level requirement, a logic occupation requirement, a timing requirement, a fan-out number requirement, and a requirement of a partial netlist structure of the back-end processing apparatus.

As an optional implementation manner, in the first aspect of the embodiment of the present invention, the determining, by the back-end processing device, whether a logic optimization result in the synthesized netlist matches a predetermined back-end requirement includes:

the back-end processing device determines the matching degree of the logic optimization result in the synthesized netlist and the predetermined back-end requirement;

and the back-end processing device judges whether the matching degree is greater than or equal to a matching degree threshold value, and when the matching degree is not greater than or equal to the matching degree threshold value, the logic optimization result in the synthesized netlist is determined to be not matched with the back-end requirement.

As an optional implementation manner, in the first aspect of the embodiment of the present invention, after the back-end processing device reads the synthesized netlist generated by the front-end logic synthesis device, the method further includes:

the back-end processing device counts accumulated interaction parameters of the back-end processing device and the front-end logic synthesis device;

the back-end processing device judges whether the accumulated interactive parameters meet the logic optimization ending condition;

and when the accumulated interactive parameters are judged not to meet the logic optimization ending condition, the back-end processing device executes the step of judging whether the logic optimization result in the synthesized netlist is matched with the predetermined back-end requirement or not.

As an optional implementation manner, in the first aspect of this embodiment of the present invention, the method further includes:

when the accumulated interaction parameters are judged to meet the logic optimization ending condition, the back-end processing device determines a first priority corresponding to the logic optimization ending condition and a second priority corresponding to the back-end requirement;

the back-end processing device compares the first priority with the second priority to obtain a comparison result;

and when the comparison result shows that the first priority is not greater than the second priority, the back-end processing device executes a step of judging whether a logic optimization result in the synthesized netlist is matched with a predetermined back-end requirement.

The second aspect of the embodiments of the present invention discloses a front-end logic synthesis device, which includes:

the generating module is used for generating a synthesized netlist;

the detection module is used for detecting whether logic optimization guiding information generated by the back-end processing device for the synthesized netlist is acquired or not;

the optimization module is used for executing logic optimization operation on a logic optimization result in the synthesized netlist according to the logic optimization guide information to obtain a target logic optimization result when the detection module detects and acquires the logic optimization guide information generated by the back-end processing device;

the generating module is further used for generating a new synthesized netlist according to the target logic optimization result;

the synthesized netlist generated by the generation module is used for being provided to the back-end processing device, so that the back-end processing device judges whether a logic optimization result in the synthesized netlist matches with a predetermined back-end requirement, and the logic optimization guide information is generated by the back-end processing device when the logic optimization result in the synthesized netlist is judged not to match with the back-end requirement.

As an optional implementation manner, in the second aspect of the embodiment of the present invention, the logic optimization guidance information includes at least one location area in the synthesized netlist on which a logic optimization operation needs to be performed and/or a logic optimization direction of each location area in the at least one location area in the synthesized netlist on which a logic optimization operation needs to be performed.

As an optional implementation manner, in a second aspect of the embodiment of the present invention, the optimization module includes:

the screening submodule is used for screening a logic optimization algorithm matched with the logic optimization direction of each position region from a predetermined logic optimization algorithm set when the logic optimization guide information comprises the logic optimization direction of each position region in at least one position region which needs to execute logic optimization operation in the synthesized netlist;

and the optimization submodule is used for executing logic optimization operation on each position area according to the screened logic optimization algorithm matched with the logic optimization direction of each position area to obtain a target logic optimization result.

As an optional implementation manner, in the second aspect of the embodiment of the present invention, the position area is determined by the back-end processing apparatus based on at least one of a power consumption requirement, a hierarchy requirement, a logic occupation requirement, a timing requirement, a fan-out number requirement, and a partial netlist structure requirement of the back-end processing apparatus.

A third aspect of the present invention discloses a back-end processing apparatus, including:

the reading module is used for reading a synthesized netlist generated by the front-end logic synthesis device;

the judging module is used for judging whether a logic optimization result in the synthesized netlist is matched with a predetermined back-end requirement or not;

and the logic optimization guiding module is used for generating logic optimization guiding information when the judging module judges that the logic optimization result in the synthesized netlist is not matched with the back-end requirement, and the logic optimization guiding information is used for being provided for the front-end logic synthesis device so as to trigger the front-end logic synthesis device to execute logic optimization operation on the logic optimization result in the synthesized netlist according to the logic optimization guiding information to obtain a target logic optimization result and generate a new synthesized netlist according to the target logic optimization result.

As an optional implementation manner, in the third aspect of the embodiment of the present invention, the logic optimization guidance information includes at least one location area in the synthesized netlist where a logic optimization operation needs to be performed and/or a logic optimization direction of each location area in the at least one location area in the synthesized netlist where a logic optimization operation needs to be performed.

As an optional implementation manner, in the third aspect of the embodiment of the present invention, the position area is determined by the back-end processing apparatus based on at least one of a power consumption requirement, a level requirement, a logic occupation requirement, a timing requirement, a fan-out number requirement, and a requirement of a partial netlist structure of the back-end processing apparatus.

As an optional implementation manner, in the third aspect of the embodiment of the present invention, a specific manner of determining, by the determining module, whether the logic optimization result in the synthesized netlist matches a predetermined back-end requirement is as follows:

determining the matching degree of a logic optimization result in the synthesized netlist and a predetermined back-end requirement;

and judging whether the matching degree is greater than or equal to a matching degree threshold value, and when the matching degree is not greater than or equal to the matching degree threshold value, determining that the logic optimization result in the synthesized netlist is not matched with the back-end requirement.

As an optional implementation manner, in the third aspect of the embodiment of the present invention, the back-end processing apparatus further includes:

the statistical module is used for counting the accumulated interaction parameters of the read module and the front-end logic synthesis device after the read module reads the synthesized netlist generated by the front-end logic synthesis device;

and the judging module is further configured to judge whether the accumulated interaction parameter meets a logic optimization ending condition, and execute the operation of judging whether a logic optimization result in the synthesized netlist matches a predetermined back-end requirement when the accumulated interaction parameter is judged not to meet the logic optimization ending condition.

a determining module, configured to determine a first priority corresponding to the logical optimization ending condition and a second priority corresponding to the backend requirement when the determining module determines that the accumulated interaction parameter meets the logical optimization ending condition;

and the comparison module is used for comparing the first priority with the second priority to obtain a comparison result, and when the comparison result shows that the first priority is not greater than the second priority, the judgment module is triggered to execute the operation of judging whether the logic optimization result in the synthesized netlist is matched with the predetermined back-end requirement or not.

The fourth aspect of the present invention discloses another front-end logic synthesis apparatus, where the front-end logic synthesis apparatus includes:

a memory storing executable program code;

a processor coupled with the memory;

the processor calls the executable program code stored in the memory to execute the steps executed by the front-end logic synthesis device in the implementation method for logic optimization in FPGA logic synthesis disclosed by the first aspect of the embodiment of the invention.

A fifth aspect of the present invention discloses another back-end processing apparatus, including:

a memory storing executable program code;

a processor coupled with the memory;

the processor calls the executable program code stored in the memory to execute the steps executed by the back-end processing device in the implementation method for logic optimization in FPGA logic synthesis disclosed by the first aspect of the embodiment of the invention.

A sixth aspect of the present invention discloses a computer storage medium, where a computer instruction is stored, and when the computer instruction is called, the computer instruction is used to execute steps executed by a front-end logic synthesis apparatus in the implementation method for logic optimization in FPGA logic synthesis disclosed in the first aspect of the present invention.

A seventh aspect of the present invention discloses a computer storage medium, where a computer instruction is stored, and when the computer instruction is called, the computer instruction is used to execute steps executed by a back-end processing device in the implementation method for logic optimization in FPGA logic synthesis disclosed in the first aspect of the present invention.

The eighth aspect of the present invention discloses a system for implementing logic optimization in FPGA logic synthesis, where the system includes a front-end logic synthesis device disclosed in the second aspect of the present invention and a back-end processing device disclosed in the third aspect of the present invention.

Compared with the prior art, the embodiment of the invention has the following beneficial effects:

by implementing the embodiment of the invention, whether the logic optimization result in the synthesized netlist meets the back-end requirement can be judged after the back-end processing device reads the synthesized netlist, and if not, the logic optimization guide information provided for the front-end logic synthesis device is generated so that the front-end logic synthesis device optimizes the logic optimization result in the synthesized netlist and generates a new synthesized netlist, thus the multiple iterative optimization of the logic optimization result in the synthesized netlist can be realized according to the logic optimization guide information provided by the back-end processing device, the universality and the optimization efficiency of a logic optimization mode are improved, the matching degree of the logic optimized result and the back-end requirement is also improved, and the quality of logic synthesis is further improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic flow chart of a method for implementing logic optimization in FPGA logic synthesis according to an embodiment of the present invention;

FIG. 2 is a schematic flow chart of another method for implementing logic optimization in FPGA logic synthesis according to the embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a front-end logic synthesis apparatus according to an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of another front-end logic synthesis apparatus disclosed in the embodiments of the present invention;

FIG. 5 is a schematic structural diagram of another front-end logic synthesis apparatus according to the disclosure;

fig. 6 is a schematic structural diagram of a back-end processing apparatus according to an embodiment of the disclosure;

FIG. 7 is a schematic structural diagram of another back-end processing apparatus disclosed in the embodiments of the present invention;

FIG. 8 is a schematic structural diagram of another back-end processing apparatus according to the disclosure of the present invention;

FIG. 9 is a schematic structural diagram of another back-end processing apparatus according to the disclosure of the present invention;

fig. 10 is a schematic structural diagram of an implementation system for logic optimization in FPGA logic synthesis disclosed in the embodiment of the present invention.

Detailed Description

In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terms "first," "second," and the like in the description and claims of the present invention and in the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, apparatus, article, or article that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or article.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

The invention discloses a method, a device and a system for realizing logic optimization in FPGA (field programmable gate array) logic synthesis, which can realize repeated iterative optimization of a logic optimization result in a synthesized netlist according to logic optimization guide information fed back by a back-end processing device, thereby not only improving the universality and the optimization efficiency of a logic optimization mode, but also improving the matching degree of the result after logic optimization and the back-end requirement, and further being beneficial to improving the quality of logic synthesis.

The following are detailed below.

Example one

Referring to fig. 1, fig. 1 is a schematic flow chart illustrating a method for implementing logic optimization in FPGA logic synthesis according to an embodiment of the present invention. Therein, the method described in fig. 1 may be applied in an EDA development tool comprising at least a front-end logic synthesis means and a back-end processing means. As shown in fig. 1, the method for implementing logic optimization in FPGA logic synthesis may include the following operations:

101. and the back-end processing device reads the synthesized netlist generated by the front-end logic synthesis device.

In this embodiment of the present invention, optionally, the reading, by the back-end processing device, the synthesized netlist generated by the front-end logic synthesis device may include:

the back-end processing device receives the synthesized netlist sent by the front-end logic synthesis device; or,

the back-end processing device reads the synthesized netlist generated by the front-end logic synthesis device from the storage device which stores the synthesized netlist generated by the front-end logic synthesis device directly or according to the copying operation/cutting operation of an operator; or,

the back-end processing device reads the synthesized netlist generated by the front-end logic synthesis device from the memory data block in which the synthesized netlist generated by the front-end logic synthesis device is stored, and optionally, the memory data block may be a shared memory data block.

It should be noted that, in an implementation manner in which the back-end processing device receives the synthesized netlist sent by the front-end logic synthesis device, after the front-end logic synthesis device generates the synthesized netlist, the generated synthesized netlist may be directly sent to the back-end processing device, or the generated synthesized netlist may be sent to the back-end processing device according to a sending instruction triggered by an operator, or the generated synthesized netlist may be sent to the back-end processing device according to a synthesized netlist obtaining instruction sent by the back-end processing device, which is not limited in the embodiment of the present invention.

In the embodiment of the present invention, the synthesized netlist read by the back-end processing device may be a synthesized netlist (also referred to as an initial synthesized netlist) initially generated by the front-end logic synthesis device, or may be a synthesized netlist currently generated by the front-end logic synthesis device, where the synthesized netlist currently generated by the front-end logic synthesis device is obtained by optimizing a logic optimization result in a newly generated synthesized netlist before the current time by the front-end logic synthesis device, and the current time is a time when the synthesized netlist is currently generated by the front-end logic synthesis device.

102. The back-end processing device judges whether the logic optimization result in the synthesized netlist matches with the predetermined back-end requirement, and when the judgment result in the step 102 is yes, the process can be ended; when the judgment result of step 102 is no, step 103 may be triggered to be executed.

In the embodiment of the present invention, the predetermined back-end requirement may be pre-entered into the back-end processing device by a developer, or may be obtained by the back-end processing device through automatic analysis after the back-end processing device reads the synthesized netlist, which is not limited in the embodiment of the present invention.

Optionally, the back-end processing device performs layout and routing, timing analysis, power consumption optimization and the like after reading the synthesized netlist, each position region of the synthesized netlist is involved in the process, if a certain position region needs smaller logic occupation, or needs smaller number of levels, or needs smaller number of fan-outs, or needs a simpler netlist structure and the like, the back-end processing device feeds back the position region and the expected logic optimization direction to the front-end logic synthesis device, and after repeating for many times, if the back-end processing device finds that the optimizable condition does not exist, the read logic optimization result in the synthesized netlist is considered to be matched with the back-end requirement.

103. The back-end processing device generates logic optimization guidance information, which is used for providing the logic optimization guidance information to the front-end logic synthesis device.

In the embodiment of the present invention, optionally, after the back-end processing device generates the logic optimization guidance information, the logic optimization guidance information may be directly fed back to the corresponding front-end logic synthesis device, so as to improve the efficiency of the front-end logic synthesis device acquiring the logic optimization guidance information and further improve the logic optimization efficiency; or after the back-end processing device generates the logic optimization guidance information, the logic optimization guidance information can be provided to the corresponding front-end logic synthesis device by an operator in a cutting/copying mode, so that the mode that the operator confirms that the back provides the logic optimization guidance information to the front-end logic synthesis device is beneficial to improving the accuracy of the logic optimization guidance information acquired by the front-end logic synthesis device and further improving the accuracy of the logic optimization; or, after the back-end processing device generates the logic optimization guidance information, the logic optimization guidance information may also be uploaded to the shared storage data block by the back-end processing device, and acquired from the shared storage data block by the front-end logic synthesis device, which is not limited in the embodiment of the present invention.

In this embodiment of the present invention, optionally, after the back-end processing device generates the logic optimization guidance information or while generating the logic optimization guidance information, an information attribute corresponding to the logic optimization guidance information may also be generated, where the information attribute may include an information identifier unique to the logic optimization guidance information, and further optionally, at least one of a generation time of the logic optimization guidance information, a netlist identifier unique to a synthesized netlist on which the logic optimization guidance information is generated, identification information of a front-end logic synthesis device to which the logic optimization guidance information is directed, and a generation sequence of the logic optimization guidance information may also be included, which is not limited in the embodiment of the present invention. Therefore, the information attribute generating mode can not only provide a source tracing basis for the logic optimization guide information so as to facilitate operators to quickly and accurately inquire the logic optimization guide information, but also improve the accuracy of the logic optimization guide information acquired by the front-end logic comprehensive device by taking the information attribute as a basis.

Still further optionally, the information attribute of the logic optimization guidance information generated by the back-end processing device may be provided to the front-end logic synthesis device along with the logic optimization guidance information.

In this embodiment of the present invention, optionally, the logic optimization guidance information may include at least one location area in the synthesized netlist that needs to perform the logic optimization operation and/or a logic optimization direction of each location area in the at least one location area in the synthesized netlist that needs to perform the logic optimization operation, and optionally, the at least one location area is determined by the back-end processing device based on at least one of a power consumption requirement, a hierarchy requirement, a logic occupation requirement, a timing requirement, a fan-out number requirement, and a local netlist structure requirement of the back-end processing device. Therefore, accurate logic optimization guiding information can be provided for the front-end logic comprehensive device, and the optimization efficiency and the optimization accuracy of the logic can be improved. Further optionally, when the number of the position areas in the synthesized netlist that need to perform the logic optimization operation exceeds a predetermined number threshold, the logic optimization guiding information may further include a logic optimization priority corresponding to each position area or a logic optimization order corresponding to each position area, so that the front-end logic synthesis apparatus determines the content of the priority optimization according to the logic optimization priority/logic optimization order corresponding to each position area that needs to be optimized when the resources are insufficient during the logic optimization. The higher the logic optimization priority/the earlier the logic optimization sequence, the higher the importance of the content to be optimized in the corresponding position area, and under the condition of insufficient resources, the front-end logic synthesis device preferentially optimizes the content to be optimized in the position area with the higher priority/the earlier the logic optimization sequence, so as to ensure the efficiency and accuracy of logic optimization on the part of content. For example, the location area includes at least one of an optimization area of functional requirements, an optimization area of hierarchical requirements, and an optimization area of logical occupancy requirements.

104. And when the logic optimization guide information generated by the back-end processing device is acquired, the front-end logic synthesis device executes logic optimization operation on the logic optimization result in the synthesized netlist according to the logic optimization guide information to obtain a target logic optimization result.

As an alternative embodiment, the performing, by the front-end logic synthesis apparatus, a logic optimization operation on the logic optimization result in the synthesized netlist according to the logic optimization guidance information to obtain the target logic optimization result may include:

when the logic optimization guiding information comprises the logic optimization direction of each position area in at least one position area which needs to execute the logic optimization operation in the synthesized netlist, the front-end logic synthesis device screens a logic optimization algorithm matched with the logic optimization direction of each position area from a predetermined logic optimization algorithm set;

and the front-end logic synthesis device executes logic optimization operation on each position area according to the screened logic optimization algorithm matched with the logic optimization direction of each position area to obtain a target logic optimization result.

Therefore, the optional implementation method can screen the logic optimization algorithm matched with the logic optimization direction of each position region based on the logic optimization direction of each position region, so that the universality of the logic optimization method provided by the embodiment of the invention is improved, and the optimization efficiency of iterative optimization of the logic optimization result in the synthesized netlist is improved.

105. And the front-end logic synthesis device generates a new synthesized netlist according to the target logic optimization result.

In the embodiment of the present invention, the synthesized netlist generated by the front-end logic synthesis apparatus is used to be provided to the back-end processing apparatus, so as to trigger the back-end processing apparatus to continue to execute step 101.

Optionally, after the front-end logic synthesis device generates the synthesized netlist or while generating the synthesized netlist, the netlist attribute of the synthesized netlist can be generated, the netlist attribute comprises a unique netlist mark of the synthesized netlist, and further optionally, the generation sequence of the synthesized netlist, the generation time of the synthesized netlist, at least one of the information attribute of the logic optimization guidance information according to which the synthesized netlist is generated and the identification information of the front-end logic synthesis device which generates the synthesized netlist can be included, so that a traceability basis can be provided for the generated synthesized netlist, and the traceability accuracy and traceability efficiency can be improved. Furthermore, the netlist attribute of the synthesized netlist generated by the front-end logic synthesis device can be provided to the back-end processing device along with the synthesized netlist, so that when the back-end processing device reads the synthesized netlist and the netlist attribute of the synthesized netlist, the effectiveness judgment can be performed on the read synthesized netlist according to the netlist attribute of the synthesized netlist, the accuracy and the reliability of judging whether the read synthesized netlist meets the back-end requirement or not can be improved, and the situation that unnecessary operation is executed due to the fact that the read synthesized netlist is invalid can be reduced.

In an optional embodiment, the method for implementing logic optimization in FPGA logic synthesis may further include the following operations:

the back-end processing device obtains a front-end logic comprehensive identification which is only corresponding to the front-end logic comprehensive device for generating the currently read synthesized netlist and the priority corresponding to the front-end logic comprehensive identification, wherein each synthesized netlist read by the back-end processing device at the same time has the front-end logic comprehensive device corresponding to the synthesized netlist, and different front-end logic comprehensive identifications correspond to different front-end logic comprehensive devices.

Wherein the method may further comprise the operations of:

and when different synthesized netlists generated by different front-end logic synthesis devices are read at the same time and the logic optimization judgment resources of the rear-end processing device are insufficient, the rear-end processing device executes logic optimization judgment operation on the corresponding synthesized netlists according to the priority corresponding to each front-end logic synthesis identifier and the sequence of the priorities from top to bottom.

Therefore, according to the optional embodiment, when a plurality of different synthesized netlists are read and the logic optimization judgment resources are insufficient, the logic optimization judgment can be performed on the synthesized netlists according to the sequence of the front-end logic comprehensive identification priorities from top to bottom, so that the logic optimization judgment efficiency of the synthesized netlists corresponding to the front-end logic comprehensive identifications with higher priorities is improved, and the corresponding logic optimization efficiency is further improved.

In another alternative embodiment, after completing step 101, the back-end processing device may further perform the following operations:

the back-end processing device executes the target operation on the read synthesized netlist to obtain an operation result corresponding to the target operation;

the back-end processing device determines the back-end requirement of the back-end processing device according to the operation result corresponding to the target operation.

In the embodiment of the present invention, optionally, the target operation may include at least one of a place and route operation, a timing analysis operation, a power consumption analysis operation, a local area analysis operation, and a critical path analysis operation. And the back-end processing device can perform corresponding operation on the synthesized netlist after reading the synthesized netlist generated by the front-end logic synthesis device so as to intelligently analyze according to an operation result to obtain a back-end requirement, so that a judgment basis is provided for subsequently judging whether a logic optimization result in the synthesized netlist meets the back-end requirement, and the accuracy of a judgment result for judging whether the logic optimization result in the synthesized netlist meets the back-end requirement is improved.

In yet another alternative embodiment, after the back-end processing device generates the logic optimization guidance information, the method may further include the following operations:

and the back-end processing device compares whether the currently generated logic optimization guiding information is the same as the latest generated logic optimization guiding information before the currently generated logic optimization guiding information to obtain a comparison result.

In the embodiment of the invention, when the comparison result is yes, that is, when the comparison result indicates that the currently generated logic optimization guide information is the same as the logic optimization guide information which is newly generated before the currently generated logic optimization guide information, the process can be ended, that is, the generated logic optimization guide information is not required to be provided to the front-end logic synthesis device; when the comparison result is negative, that is, when the comparison result indicates that the currently generated logic optimization guidance information is different from the logic optimization guidance information newly generated before the currently generated logic optimization guidance information, the generated logic optimization guidance information needs to be provided to the front-end logic synthesis apparatus. Furthermore, the back-end processing device can set an attribute label matched with the comparison result for the currently generated logic optimization guidance information according to the comparison result, and the attribute label is used for visually indicating whether the currently generated logic optimization guidance information needs to be provided for the front-end logic synthesis device, so that the accuracy of providing the logic optimization guidance information for the front-end logic synthesis device is improved, and the accuracy of logic optimization of the front-end logic synthesis device is improved.

Further optionally, when the comparison result is yes, the back-end processing device may also perform the following operations:

the back-end processing device determines the back-end requirement of the back-end processing device according to the operation result corresponding to the target operation, and triggers the execution of the step 102.

As a further alternative, when the comparison result is yes, before the back-end processing device re-determines the back-end requirement, the back-end processing device may further perform the following operations:

the back-end processing device judges whether the comparison frequency for continuously comparing the currently generated logic optimization guidance information with the logic optimization guidance information which is newly generated before the currently generated logic optimization guidance information and is provided to the front-end logic synthesis device exceeds a preset frequency threshold value, if not, the back-end processing device determines the back-end requirement of the back-end processing device according to the operation result corresponding to the target operation and triggers the execution of the operation of the step 102, and if yes, the process can be ended. The mode of setting the comparison times constraint condition can reduce the occurrence of low logic optimization efficiency caused by determining the back end requirement for multiple times by the back end processing device.

Therefore, the optional embodiment can reduce the occurrence of the situation that the front-end logic synthesis device is guided to repeatedly execute the same logic optimization operation, improve the reliability and the accuracy of the logic optimization guidance information provided by the front-end logic synthesis device, and improve the efficiency and the accuracy of the logic optimization to a certain extent.

Therefore, the implementation of the method for implementing logic optimization in FPGA logic synthesis described in fig. 1 can implement further iterative optimization of the logic optimization result in the synthesized netlist according to the logic optimization guidance information provided by the back-end processing device, which not only improves the universality and optimization efficiency of the logic optimization mode, but also improves the matching degree between the result after logic optimization and the back-end requirement, thereby being beneficial to improving the quality of logic synthesis. In addition, a traceability basis can be provided for the logic optimization guidance information so as to facilitate operators to quickly and accurately inquire the logic optimization guidance information, and the accuracy of the logic optimization guidance information acquired by the front-end logic comprehensive device can be improved by taking the information attribute as a basis. In addition, a source tracing basis can be provided for the generated synthesized netlist, and the source tracing accuracy and the source tracing efficiency are improved. In addition, the situation that the front-end logic synthesis device is guided to repeatedly execute the same logic optimization operation can be reduced, the reliability and the accuracy of the logic optimization guidance information provided by the front-end logic synthesis device are improved, and the efficiency and the accuracy of the logic optimization are improved to a certain extent.

Example two

Referring to fig. 2, fig. 2 is a schematic flow chart of another method for implementing logic optimization in FPGA logic synthesis according to the embodiment of the present invention. Therein, the method described in fig. 2 can be applied in an EDA development tool, which comprises at least a front-end logic synthesis means and a back-end processing means. As shown in fig. 2, the method for implementing logic optimization in FPGA logic synthesis may include the following operations:

201. the front-end logic synthesis device reads the user design, and executes logic synthesis operation and logic optimization operation on the read user design to obtain a synthesized netlist.

202. The front-end logic synthesis device provides the synthesized netlist generated by the front-end logic synthesis device to the back-end processing device.

203. And the back-end processing device reads the synthesized netlist generated by the front-end logic synthesis device and counts the accumulated interactive parameters between the synthesized netlist and the front-end logic synthesis device.

Optionally, the accumulated interaction parameter may include accumulated interaction duration and/or accumulated interaction times of the back-end processing device and the front-end logic synthesis device, and when the accumulated interaction duration and the accumulated interaction times are included at the same time, the accumulated interaction duration and the accumulated interaction times both have priorities corresponding to the accumulated interaction duration and the accumulated interaction times, where when the accumulated interaction parameter with a higher priority first satisfies the corresponding logic optimization end condition, the determination result in step 204 is yes.

Further optionally, the starting timing time of the accumulated interaction duration is a time when the back-end processing device acquires the initial synthesized netlist generated by the front-end logic synthesis device, or the starting timing time of the accumulated interaction duration is a time when the back-end processing device first generates logic optimization guide information after acquiring the initial synthesized netlist generated by the front-end logic synthesis device.

Further optionally, the accumulated interaction times are total times of generating logic optimization guidance information in a time period from a first time to a current time, or the accumulated interaction times are total times of acquiring a synthesized netlist in a time period from a second time to the current time; the first time is earlier than the time when the back-end processing device generates the logic optimization guidance information corresponding to the initial synthesized netlist, and the second time is earlier than the time when the back-end processing device acquires the initial synthesized netlist.

204. The back-end processing device judges whether the accumulated interactive parameters meet the logic optimization ending condition, and if the judgment result in the step 204 is negative, the step 205 is triggered to be executed; when the determination result in step 204 is yes, the process may be ended.

It should be noted that, in an alternative embodiment, when the determination result in step 205 is yes, the back-end processing device may also trigger to perform the following operations:

the back-end processing device determines a first priority corresponding to the logic optimization ending condition and a second priority corresponding to the back-end requirement;

when the comparison result indicates that the first priority is not greater than the second priority, the back-end processing device executes step 205; when the comparison result indicates that the first priority is higher than the second priority, the process may be ended.

205. And the back-end processing device determines the matching degree of the logic optimization result in the synthesized netlist and the predetermined back-end requirement.

As an alternative embodiment, the determining, by the back-end processing device, a matching degree of the logic optimization result in the synthesized netlist with the predetermined back-end requirement may include:

the back-end processing device determines the total number of demands included in a demand set corresponding to the back-end demands;

the back-end processing device determines all the target requirements which can be met by the read logic optimization result in the synthesized netlist from the requirement set, and determines the quantity of all the target requirements;

and the back-end processing device determines the ratio of the number of all target demands to the total number of demands included in the demand set as the matching degree of the logic optimization result and the back-end demand in the synthesized netlist.

Further optionally, before the back-end processing device determines the total number of the demands included in the demand set corresponding to the back-end demand, the back-end processing device may further perform the following operations:

the back-end processing device determines the requirement with the highest priority in a requirement set corresponding to the back-end requirement, and judges whether the logic optimization result in the synthesized netlist meets the requirement with the highest priority; when the requirement with the highest priority is judged not to be met, triggering to execute the step 207; when the requirement with the highest priority is judged to be met, the operation of determining the total quantity of the requirements included in the requirement set corresponding to the back-end requirement is performed.

As can be seen, this alternative embodiment can determine the matching degree of the logic optimization result in the synthesized netlist and the backend requirement based on the ratio of the total number of requirements included in the requirement set and the number of all target requirements that can be met by the logic optimization result in the synthesized netlist. In addition, before the matching degree is calculated according to the related quantity, whether the logic optimization result in the synthesized netlist meets the requirement of the highest priority can be judged, if not, the matching degree does not need to be calculated, and the efficiency of generating the logic optimization guide information is improved.

206. The back-end processing device determines whether the matching degree is greater than or equal to the threshold of the matching degree, and if yes in step 206, the process may be ended; when the judgment result in the step 206 is negative, the step 207 is triggered to be executed.

The matching degree threshold may be manually set by a developer/operator, or may be determined intelligently according to development requirements of the developer/operator, which is not limited in the embodiment of the present invention.

207. The back-end processing device generates logic optimization guidance information.

208. The back-end processing device provides the generated logic optimization guidance information to the front-end logic synthesis device.

209. And when the logic optimization guide information generated by the back-end processing device is acquired, the front-end logic synthesis device executes logic optimization operation on the logic optimization result in the synthesized netlist according to the logic optimization guide information to obtain a target logic optimization result.

210. The front-end logic synthesis device generates a new synthesized netlist according to the target logic optimization result, and triggers execution of step 202.

Therefore, by implementing the embodiment of the invention, whether the logic optimization result in the synthesized netlist needs to be optimized can be judged according to the matching degree of the logic optimization result in the synthesized netlist and the back-end requirement, and a judgment basis is provided for judging whether the logic optimization result in the synthesized netlist needs to be optimized. In addition, whether the accumulated interactive parameters of the back-end processing device and the front-end logic synthesis device meet the logic optimization end condition or not can be judged after the synthesized netlist is read, and therefore the situation of infinite logic optimization can be reduced by setting the logic optimization end condition. In other optional embodiments, diversified judgment bases can be further provided for the end of logic optimization by setting priorities for the backend requirements and the logic optimization end conditions respectively, operators can set the priorities adaptively according to actual requirements, the backend requirements can be set to be high priorities if higher-quality logic comprehensive results are required, and the logic optimization end conditions can be set to be high priorities if the logic comprehensive results are improved in quality.

In an alternative embodiment, before performing step 204, the method may further comprise the operations of:

the back-end processing device judges whether the read synthesized netlist is the synthesized netlist initially generated by the front-end logic synthesis device, and when the judgment result is yes, the step 205 can be directly triggered and executed; when the determination result is negative, the execution of step 204 may be triggered.

In another alternative embodiment, before performing step 204, the method may further comprise the operations of:

the back-end processing device determines a target netlist mark uniquely corresponding to the read synthesized netlist, judges the effectiveness of the read synthesized netlist according to the target netlist mark, and triggers to execute the step 204 when the judgment result is yes; and when the judgment result is negative, ending the process.

Further, before executing the target netlist identifier uniquely corresponding to the read synthesized netlist, the back-end processing device may further execute the operation of determining whether the read synthesized netlist is the synthesized netlist initially generated by the front-end logic synthesis device, and when the determination result is yes, may directly trigger to execute step 205; when the determination result is negative, the execution of step 204 may be triggered.

In yet another alternative embodiment, before performing step 204, the back-end processing device may further perform the following operations:

the back-end processing device acquires the read netlist parameters of the synthesized netlist, wherein the netlist parameters can include the generation sequence of the synthesized netlist or the generation duration of the synthesized netlist, the generation sequence of the synthesized netlist corresponds to the total times of generating the synthesized netlist by the front-end logic synthesis device, and the generation duration of the synthesized netlist is equal to the time length from the time of generating the initial synthesized netlist by the front-end logic synthesis device to the time of generating the current synthesized netlist;

and the back-end processing device judges whether the netlist parameters of the read synthesized netlist are in a predetermined parameter range, and if so, triggers to execute the step 204.

The optional steps executed after the step 203 is executed and before the step 204 is executed may be unified into a scheme that the back-end processing apparatus determines whether the read synthesized netlist meets the logic optimization determination condition.

Further optionally, the netlist parameters of the synthesized netlist are provided to the back-end processing device by the front-end logic synthesis device when the newly generated synthesized netlist is provided to the back-end processing device, so that the statistical operation of the back-end processing device can be simplified, and the logic optimization judgment efficiency of the back-end processing device can be improved.

Therefore, the implementation of the method for implementing logic optimization in FPGA logic synthesis described in fig. 2 can implement optimization of the logic optimization result in the synthesized netlist according to the logic optimization guidance information fed back by the back-end processing device, which not only improves the universality and optimization efficiency of the logic optimization mode, but also improves the matching degree of the result after logic optimization and the back-end requirement, thereby being beneficial to improving the quality of logic synthesis. In addition, whether the logic optimization result in the synthesized netlist needs to be optimized or not can be judged according to the matching degree of the logic optimization result in the synthesized netlist and the back-end requirement, and judgment basis is provided for judging whether the logic optimization result in the synthesized netlist needs to be optimized or not. In addition, whether the accumulated interactive parameters of the back-end processing device and the front-end logic synthesis device meet the logic optimization end condition or not can be judged after the synthesized netlist is read, and therefore the situation of infinite logic optimization can be reduced by setting the logic optimization end condition. In other optional embodiments, diversified judgment bases can be further provided for the end of logic optimization by setting priorities for the back-end requirements and the logic optimization end conditions respectively, and the operators can perform adaptive setting according to actual requirements.

EXAMPLE III

The embodiment of the invention discloses another method for realizing logic optimization in FPGA logic synthesis, which is applied to a front-end logic synthesis device of an EDA development tool and can comprise the following operations:

the front-end logic synthesis device generates a synthesized netlist;

the front-end logic synthesis device detects whether logic optimization guide information generated by the back-end processing device for the synthesized netlist is acquired;

when the logic optimization guiding information generated by the back-end processing device is obtained through detection, the front-end logic synthesis device executes logic optimization operation on a logic optimization result in the synthesized netlist according to the logic optimization guiding information to obtain a target logic optimization result;

and the front-end logic synthesis device generates a new synthesized netlist according to the target logic optimization result.

The synthesized netlist generated by the front-end logic synthesis device is used for being provided to the back-end processing device, so that the back-end processing device judges whether a logic optimization result in the synthesized netlist is matched with a predetermined back-end requirement, and the logic optimization guide information is generated by the back-end processing device when the logic optimization result in the synthesized netlist is judged to be not matched with the back-end requirement.

In an alternative embodiment, the logic optimization guidance information includes at least one location area in the synthesized netlist where the logic optimization operation needs to be performed and/or a logic optimization direction of each location area in the at least one location area in the synthesized netlist where the logic optimization operation needs to be performed.

In another alternative embodiment, the performing, by the front-end logic synthesis apparatus, a logic optimization operation on the logic optimization result in the synthesized netlist according to the logic optimization guide information to obtain the target logic optimization result may include:

Optionally, the position area is determined by the back-end processing device based on at least one of a power consumption requirement, a level requirement, a logic occupation requirement, a timing requirement, a fan-out number requirement, and a requirement of the local netlist structure of the back-end processing device.

In the embodiment of the present invention, please refer to the detailed description in the first embodiment and the second embodiment for the other detailed description of the front-end logic synthesis apparatus, which will not be described again in the embodiment of the present invention.

Therefore, the implementation of the embodiment of the invention can realize the repeated iterative optimization of the logic optimization result in the synthesized netlist according to the logic optimization guide information fed back by the back-end processing device, thereby not only improving the universality and the optimization efficiency of the logic optimization mode, but also improving the matching degree of the result after the logic optimization and the back-end requirement, and further being beneficial to improving the quality of the logic synthesis.

Example four

The embodiment of the invention discloses another method for realizing logic optimization in FPGA logic synthesis, which is applied to a back-end processing device of an EDA development tool and can comprise the following operations:

the back-end processing device reads the synthesized netlist generated by the front-end logic synthesis device;

the back-end processing device judges whether the read logic optimization result in the synthesized netlist is matched with the predetermined back-end requirement or not;

and when the logic optimization result in the synthesized netlist is judged to be not matched with the back-end requirement, the back-end processing device generates logic optimization guide information, and the logic optimization guide information is used for being provided for the front-end logic synthesis device so as to trigger the front-end logic synthesis device to execute logic optimization operation on the logic optimization result in the synthesized netlist according to the logic optimization guide information to obtain a target logic optimization result and generate a new synthesized netlist according to the target logic optimization result.

Optionally, the logic optimization guidance information includes at least one location area in the synthesized netlist where the logic optimization operation needs to be performed and/or a logic optimization direction of each location area in the at least one location area in the synthesized netlist where the logic optimization operation needs to be performed. Further optionally, the location area is determined by the back-end processing device based on at least one of a power consumption requirement, a level requirement, a logic occupation requirement, a timing requirement, a fan-out number requirement, and a local netlist structure requirement of the back-end processing device.

In an alternative embodiment, the determining, by the back-end processing device, whether the logic optimization result in the synthesized netlist matches the predetermined back-end requirement may include:

and the back-end processing device judges whether the matching degree is greater than or equal to the matching degree threshold value, and when the matching degree is not greater than or equal to the matching degree threshold value, the logic optimization result in the synthesized netlist is determined to be not matched with the back-end requirement.

In this optional embodiment, further optionally, after the back-end processing device reads the synthesized netlist generated by the front-end logic synthesis device, the back-end processing device may further perform the following operations:

the back-end processing device counts the accumulated interaction parameters between the back-end processing device and the front-end logic comprehensive device;

the back-end processing device judges whether the accumulated interactive parameters meet the logic optimization ending condition or not;

and when judging that the accumulated interactive parameters do not meet the logic optimization ending condition, the back-end processing device executes the step of judging whether the logic optimization result in the synthesized netlist is matched with the predetermined back-end requirement or not.

Still further optionally, the method may further comprise the operations of:

when the accumulated interaction parameters are judged to meet the logic optimization ending condition, the back-end processing device determines a first priority corresponding to the logic optimization ending condition and a second priority corresponding to a back-end requirement;

and when the comparison result shows that the first priority is not greater than the second priority, the back-end processing device executes the step of judging whether the logic optimization result in the synthesized netlist is matched with the predetermined back-end requirement or not.

In another alternative embodiment, the reading of the synthesized netlist generated by the front-end logic synthesis device by the back-end processing device may comprise:

the back-end processing device reads a synthesized netlist initially generated by the front-end logic synthesis device; or,

and the back-end processing device reads the synthesized netlist generated by the front-end logic synthesis device.

The synthesized netlist generated currently by the front-end logic synthesis is generated by optimizing a logic optimization result in the synthesized netlist generated latest before the current moment by the front-end logic synthesis device, and the current moment is the moment when the front-end logic synthesis device generates the synthesized netlist currently.

In yet another alternative embodiment, the back-end processing device may further perform the following operations:

after the back-end processing device reads the synthesized netlist generated by the front-end logic synthesis device, determining a target netlist identifier uniquely corresponding to the read synthesized netlist;

the back-end processing device judges the effectiveness of the read comprehensive netlist according to the target netlist mark; and when the read synthesized netlist is judged to be effective, triggering and executing whether the logic optimization result in the read synthesized netlist is matched with the predetermined back-end requirement or not.

In this optional embodiment, the back-end processing device may further determine, after reading the post-synthesis netlist generated by the front-end logic synthesis device, whether the read post-synthesis netlist is the post-synthesis netlist initially generated by the front-end logic synthesis device; when the read synthesized netlist is judged to be the synthesized netlist initially generated by the front-end logic synthesis device, triggering and executing the step of judging whether the logic optimization result in the synthesized netlist read by the reading module is matched with the predetermined back-end requirement or not; and triggering and executing the step of determining the unique corresponding target netlist identifier of the read synthesized netlist when the read synthesized netlist is judged not to be the synthesized netlist initially generated by the front-end logic synthesis device.

It should be noted that, in the embodiment of the present invention, for other descriptions of the back-end processing device, including but not limited to other steps executed by the back-end processing device, specific contents and specific functions of information exchanged between the back-end processing device and the front-end logic synthesis device, and a specific implementation manner when the back-end processing device executes a certain step, please refer to the detailed descriptions in the first to second embodiments, and the detailed descriptions in the embodiment of the present invention are not repeated.

Therefore, by implementing the embodiment of the invention, the back-end processing device can intelligently determine whether to guide the front-end logic synthesis device to execute the logic optimization operation on the logic optimization result in the synthesized netlist according to the judgment result of whether the logic optimization result in the synthesized netlist is matched with the back-end requirement or not, so that the repeated iterative optimization of the logic optimization result in the synthesized netlist is realized, the universality and the optimization efficiency of a logic optimization mode are improved, the matching degree of the result after the logic optimization and the back-end requirement is also improved, and the quality of the logic synthesis is further improved.

EXAMPLE five

Referring to fig. 3, fig. 3 is a schematic structural diagram of a front-end logic synthesis apparatus according to an embodiment of the present invention. As shown in fig. 3, the front-end logic synthesis apparatus may include:

and a generating module 301, configured to generate a synthesized netlist.

A detecting module 302, configured to detect whether logic optimization guidance information generated by the back-end processing apparatus for the synthesized netlist is obtained.

And an optimizing module 303, configured to, when the detecting module 302 detects and acquires the logic optimization guidance information generated by the back-end processing device, perform a logic optimization operation on the logic optimization result in the synthesized netlist according to the logic optimization guidance information to obtain a target logic optimization result.

The generating module 301 is further configured to generate a new synthesized netlist according to the target logic optimization result.

The synthesized netlist generated by the generating module 301 is used to be provided to a back-end processing device, so that the back-end processing device determines whether a logic optimization result in the synthesized netlist matches with a predetermined back-end requirement, and the logic optimization guidance information is generated by the back-end processing device when determining that the logic optimization result in the synthesized netlist does not match with the back-end requirement.

In an alternative embodiment, as shown in fig. 4, the optimization module 303 may include:

the screening submodule 3031 is configured to, when the logic optimization guidance information includes the logic optimization direction of each location area in at least one location area that needs to perform the logic optimization operation in the synthesized netlist, screen a logic optimization algorithm that matches the logic optimization direction of each location area from a predetermined set of logic optimization algorithms.

And the optimization submodule 3032 is configured to perform a logic optimization operation on each location region according to the screened logic optimization algorithm matched with the logic optimization direction of the location region, so as to obtain a target logic optimization result.

Therefore, the front-end logic synthesis device described in fig. 4 can implement multiple iterative optimization of the logic optimization result in the synthesized netlist according to the logic optimization guidance information provided by the back-end processing device, thereby not only improving the universality and the optimization efficiency of the logic optimization mode, but also improving the matching degree of the result after the logic optimization and the back-end requirement, and further being beneficial to improving the quality of logic synthesis.

EXAMPLE six

Referring to fig. 5, fig. 5 is a schematic structural diagram of another front-end logic synthesis apparatus according to an embodiment of the present invention. As shown in fig. 5, the front-end logic synthesis apparatus may include:

a memory 401 storing executable program code;

a processor 402 coupled with the memory 401;

the processor 402 calls the executable program code stored in the memory 401 to execute the steps executed by the front-end logic synthesis apparatus for implementing logic optimization in FPGA logic synthesis disclosed in any one of the first to third embodiments of the present invention.

EXAMPLE seven

Referring to fig. 6, fig. 6 is a schematic structural diagram of a back-end processing device according to an embodiment of the present invention. As shown in fig. 6, the back-end processing apparatus may include:

and a reading module 501, configured to read a synthesized netlist generated by the front-end logic synthesis apparatus.

A judging module 502, configured to judge whether the logic optimization result in the synthesized netlist read by the reading module 501 matches a predetermined back-end requirement.

And a logic optimization guidance module 503, configured to generate logic optimization guidance information when the judgment module 502 judges that the logic optimization result in the synthesized netlist is not matched with the back-end requirement, where the generated logic optimization guidance information is used to be provided to a front-end logic synthesis device, so as to trigger the front-end logic synthesis device to perform logic optimization operation on the logic optimization result in the synthesized netlist according to the logic optimization guidance information to obtain a target logic optimization result, and generate a new synthesized netlist according to the target logic optimization result.

In an alternative embodiment, the specific way for the reading module 502 to read the synthesized netlist generated by the front-end logic synthesis apparatus is as follows:

reading a synthesized netlist initially generated by a front-end logic synthesis device; or,

and reading a synthesized netlist currently generated by the front-end logic synthesis device.

In another alternative embodiment, the specific way for the determining module 502 to determine whether the logic optimization result in the synthesized netlist matches the predetermined back-end requirement is as follows:

and judging whether the matching degree is greater than or equal to a matching degree threshold value, and determining that the logic optimization result in the synthesized netlist is not matched with the back-end requirement when the matching degree is not greater than or equal to the matching degree threshold value.

In this optional embodiment, further optionally, as shown in fig. 7, the back-end processing apparatus may further include:

a counting module 504, configured to count accumulated interaction parameters of the front-end logic synthesis device after the reading module 501 reads the synthesized netlist generated by the front-end logic synthesis device.

Preferably, after the reading module 501 reads the synthesized netlist generated by the front-end logic synthesis apparatus, the statistical module 504 may be triggered to start.

The determining module 502 is further configured to determine whether the accumulated interaction parameter meets a logic optimization ending condition, and when it is determined that the accumulated interaction parameter does not meet the logic optimization ending condition, perform the above operation of determining whether the logic optimization result in the synthesized netlist matches a predetermined back-end requirement.

Still further optionally, as shown in fig. 7, the back-end processing apparatus may further include:

the determining module 505 is configured to determine a first priority corresponding to the logic optimization ending condition and a second priority corresponding to the backend requirement when the determining module 502 determines that the accumulated interaction parameter meets the logic optimization ending condition.

A comparing module 506, configured to compare the first priority with the second priority to obtain a comparison result, and when the comparison result indicates that the first priority is not greater than the second priority, trigger the determining module 502 to perform the operation of determining whether the logic optimization result in the synthesized netlist matches the predetermined back-end requirement.

In yet another alternative embodiment, as shown in fig. 8, the back-end processing apparatus may further include:

the obtaining module 507 is configured to obtain a target netlist identifier uniquely corresponding to the read synthesized netlist after the reading module 501 reads the synthesized netlist generated by the front-end logic synthesis device.

The judging module 502 may also be configured to judge validity of the read synthesized netlist according to the target netlist identifier; when the read synthesized netlist is judged to be valid, whether the logic in the synthesized netlist read by the reading module 501 is matched with the predetermined back-end requirement is triggered and executed.

In this optional embodiment, further optionally, the judging module 502 is further configured to, after the reading module 501 reads the post-synthesis netlist generated by the front-end logic synthesis device, judge whether the read post-synthesis netlist is the post-synthesis netlist initially generated by the front-end logic synthesis device; when the read synthesized netlist is judged to be the synthesized netlist initially generated by the front-end logic synthesis device, the operation of judging whether the logic optimization result in the synthesized netlist read by the reading module 501 is matched with the predetermined back-end requirement is triggered and executed.

The obtaining module 507 is specifically configured to:

after the reading module 501 reads the synthesized netlist generated by the front-end logic synthesis device and when the judging module 502 judges that the read synthesized netlist is not the synthesized netlist initially generated by the front-end logic synthesis device, a target netlist identifier uniquely corresponding to the read synthesized netlist is determined.

It can be seen that, by implementing the back-end processing device described in any one of fig. 6 to 8, the back-end processing device can provide logic optimization guidance information to the front-end logic synthesis device to implement multiple iterative optimization of the logic optimization result in the synthesized netlist, which not only improves the universality and optimization efficiency of the logic optimization mode, but also improves the matching degree of the result after logic optimization and the back-end requirement, thereby being beneficial to improving the quality of logic synthesis.

Example eight

Referring to fig. 9, fig. 9 is a schematic structural diagram of another back-end processing device according to an embodiment of the disclosure. As shown in fig. 9, the back-end processing apparatus may include:

a memory 601 in which executable program code is stored;

a processor 602 coupled to a memory 601;

the processor 602 calls the executable program code stored in the memory 601 to execute the steps executed by the back-end processing device in the implementation of the logic optimization in the FPGA logic synthesis disclosed in the first embodiment, the second embodiment, or the fourth embodiment of the present invention.

Example nine

Referring to fig. 10, fig. 10 is a schematic structural diagram of a system for implementing logic optimization in FPGA logic synthesis according to an embodiment of the present invention. As shown in fig. 10, the system may include a front-end logic synthesis device and a back-end processing device, where a detailed description of a specific structure and a function of the front-end logic synthesis device is provided with reference to the detailed description of the fifth embodiment, and a detailed description of a specific structure and a function of the back-end processing device is provided with reference to the detailed description of the seventh embodiment, which are not repeated in this embodiment of the present invention.

Example ten

The embodiment of the invention discloses a computer storage medium, which stores a computer instruction, and the computer instruction is used for steps executed by a front-end logic synthesis device in the method for realizing logic optimization in FPGA logic synthesis disclosed in any one of the first embodiment to the third embodiment of the invention when being called.

EXAMPLE eleven

The embodiment of the invention discloses a computer storage medium, which stores a computer instruction, and the computer instruction is used for steps executed by a back-end processing device in the method for realizing logic optimization in FPGA logic synthesis disclosed in the first embodiment, the second embodiment or the fourth embodiment of the invention when being called.

The above-described embodiments of the apparatus are merely illustrative, and the modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, may be located in one place, or may be distributed on a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.

Through the above detailed description of the embodiments, those skilled in the art will clearly understand that the embodiments may be implemented by software plus a necessary general hardware platform, and may also be implemented by hardware. Based on such understanding, the above technical solutions may be embodied in the form of a software product, which may be stored in a computer-readable storage medium, wherein the storage medium includes a Read-Only Memory (ROM), a Random Access Memory (RAM), a Programmable Read-Only Memory (PROM), an Erasable Programmable Read-Only Memory (EPROM), a One-time Programmable Read-Only Memory (OTPROM), an Electrically Erasable rewritable Read-Only Memory (EEPROM), a compact disc-Read-Only Memory (CD-ROM) or other magnetic disk memories, a magnetic tape Memory, a magnetic disk, a magnetic tape Memory, a magnetic tape, and a magnetic tape, Or any other medium which can be used to carry or store data and which can be read by a computer.

Finally, it should be noted that: the method, the device and the system for implementing logic optimization in FPGA logic synthesis disclosed in the embodiments of the present invention are only preferred embodiments of the present invention, and are only used for illustrating the technical solutions of the present invention, not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art; the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for realizing logic optimization in FPGA logic synthesis is characterized by comprising the following steps:

2. The method according to claim 1, wherein the logic optimization guidance information includes at least one location area in the synthesized netlist where a logic optimization operation needs to be performed and/or a logic optimization direction of each location area in the at least one location area in the synthesized netlist where a logic optimization operation needs to be performed.

3. The method for implementing logic optimization in FPGA logic synthesis according to claim 2, wherein the front-end logic synthesis device performs logic optimization operation on the logic optimization result in the synthesized netlist according to the logic optimization guide information to obtain a target logic optimization result, including:

4. The method according to claim 2 or 3, wherein the location area is determined by the back-end processing device based on at least one of power consumption requirements, hierarchy requirements, logic occupation requirements, timing requirements, fan-out number requirements, and local netlist structure requirements of the back-end processing device.

5. The method for implementing logic optimization in FPGA logic synthesis according to any one of claims 1 to 3, wherein the determining, by the back-end processing device, whether the logic optimization result in the synthesized netlist matches a predetermined back-end requirement includes:

6. The method for implementing logic optimization in FPGA logic synthesis according to claim 5, wherein after the back-end processing device reads the synthesized netlist generated by the front-end logic synthesis device, the method further comprises:

7. The method for implementing logic optimization in FPGA logic synthesis according to claim 6, further comprising:

8. A front-end logic synthesis apparatus, the front-end logic synthesis apparatus comprising:

the generating module is used for generating a synthesized netlist;

9. A back-end processing apparatus, characterized in that the back-end processing apparatus comprises:

10. A method for implementing logic optimization in FPGA logic synthesis, wherein the system comprises the front-end logic synthesis apparatus according to claim 8 and the back-end processing apparatus according to claim 9.