CN111147060B - Control circuit and semiconductor structure comprising same - Google Patents

Abstract

The invention provides a control circuit and a semiconductor structure comprising the same, wherein the control circuit is used for providing an output voltage to a load and comprises a depletion MOSFET, an enhancement MOSFET and a current-voltage converter. The drain of the depletion MOSFET receives an input voltage, and the gate receives a first control voltage. The drain of the enhancement MOSFET receives an input voltage and its source is coupled to a load. The current-voltage converter generates a second control voltage to the gate of the enhancement MOSFET according to the current flowing through the depletion MOSFET. The enhancement MOSFET generates an output voltage for loading according to the second control voltage, and the enhancement MOSFET and the depletion MOSFET are integrated on the same substrate.

Description

Control circuits and the semiconductor structures they contain

technical field

The present invention relates to a control circuit, in particular to a control circuit for supplying power to a load, wherein the control circuit may include a semiconductor structure of a depletion MOSFET and an enhancement MOSFET.

Background technique

Transistors are mainly classified into bipolar junction transistors (BJT) and field effect transistors (field effect transistors; FET). Field effect transistors are further divided into metal oxide semiconductor field effect transistors (metal oxide semiconductor FETs; MOSFETs) and junction field effect transistors (junctionFETs; JFETs). However, the gate of the junction field effect transistor is prone to leakage current, thereby causing power loss.

Contents of the invention

The invention provides a control circuit for providing an output voltage to a load, and includes a depleted MOSFET, an enhanced MOSFET and a current-to-voltage converter. The drain of the depletion MOSFET receives an input voltage, and the gate receives a first control voltage. The drain of the enhanced MOSFET receives the input voltage, and its source is coupled to the load. The current-to-voltage converter generates a second control voltage to the gate of the enhancement MOSFET according to the current flowing through the depletion MOSFET. The enhanced MOSFET generates an output voltage for the load according to the second control voltage, and the enhanced MOSFET and the depletion MOSFET are integrated on the same substrate.

The present invention provides a semiconductor structure included in a control circuit, comprising: a substrate having a first conductivity type; a first well region having the first conductivity type and formed in the substrate; a first a doped region, having a second conductivity type, and formed in the first well region; a second well region, having the second conductivity type, and formed in the substrate; a second doped region , having the second conductivity type, and formed in the second well region; and a first gate structure, formed on the substrate, and overlapping the first and second well regions; wherein the The first doped region is used as a source of an enhanced MOSFET, the second doped region is used as a drain of the enhanced MOSFET, and the first gate structure is used as a gate of the enhanced MOSFET.

Description of drawings

Fig. 1 is the schematic diagram of operating system of the present invention;

Fig. 2 is a possible embodiment of the control circuit of the present invention;

Fig. 3 is another possible embodiment of the control circuit of the present invention;

Fig. 4 is another possible embodiment of the control circuit of the present invention;

5 is a top view of the semiconductor structure of the depletion MOSFET and the enhancement MOSFET of the present invention;

FIG. 6 is a cross-sectional view of the semiconductor structure in FIG. 5 along the dashed line A-A″.

Explanation of reference signs

100: operating system;

110: control circuit;

120: load;

Vin: input voltage;

Vout: output voltage;

RV: reference voltage;

210, 310, 410: control circuit;

211, 311, 411, DT: Depletion MOSFET;

212, 312, 412, ET: Enhanced MOSFET;

213, 313, 413: current-to-voltage converters;

214: energy storage element;

215: diode;

216, 315, 419: ground terminal;

CV1, CV2: control voltage;

314, 417, 418: resistance;

414: voltage regulator;

415: comparison circuit;

416: resistor string;

DV: divided voltage;

500: base;

511～513, 511A, 511B: well area;

521～525, 521A, 521B, 526A, 526B: doped regions;

531, 532: grid structure;

541～546: isolation structure;

D1: direction.

Detailed ways

In order to make the purpose, features and advantages of the present invention more comprehensible, the following specifically cites the embodiments, together with the accompanying drawings, for a detailed description. The description of the present invention provides different examples to illustrate the technical features of different implementations of the present invention. Wherein, the configuration of each element in the embodiment is for illustration, not for limiting the present invention. In addition, the partial repetition of the symbols in the figures in the embodiments does not imply the relationship between different embodiments in order to simplify the description.

FIG. 1 is a schematic diagram of the operating system of the present invention. As shown in the figure, the operating system 100 includes a control circuit 110 and a load 120 . The control circuit 110 is used to supply power to the load 120 . In this embodiment, the control circuit 110 receives an input voltage Vin and provides an output voltage Vout to the load 120 . In a possible embodiment, the control circuit 110 includes a startup circuit for providing an initial voltage when the power supply is just started.

The load 120 operates according to the output voltage Vout. In a possible embodiment, the output voltage Vout is used as the power supply voltage of the load 120 . The present invention does not limit the circuit structure of the load 120 . In a possible embodiment, the load 120 is a DC-DC converter for converting the level of the output voltage Vout.

In other embodiments, the load 120 generates a reference voltage RV. The control circuit 110 obtains the voltage required by the load 120 according to the reference voltage RV. In a possible embodiment, the control circuit 110 adjusts the output voltage Vout according to the reference voltage RV. For example, when the output voltage Vout is lower than the reference voltage RV, the control circuit 110 increases the output voltage Vout. When the output voltage Vout is greater than the reference voltage RV, the control circuit 110 reduces the output voltage Vout. When the output voltage Vout is equal to the reference voltage RV, the control circuit 110 maintains the output voltage Vout. With the feedback signal provided by the load 120 (ie, the reference voltage RV), the control circuit 110 properly adjusts the output voltage Vout to provide a stable power supply voltage, so that the load 120 works stably.

FIG. 2 is a possible embodiment of the control circuit of the present invention. As shown in the figure, the control circuit 210 includes a depletion-mode MOSFET (hereinafter referred to as depletion-mode MOSFET) 211, an enhancement-mode MOSFET (enhancement-mode MOSFET; hereinafter referred to as enhancement type MOSFET) 212 and a current-to-voltage converter (I-V transformer) 213 .

The drain of the depleted MOSFET 211 receives the input voltage Vin, its gate receives a control voltage CV1 , and its source is coupled to the current-to-voltage converter 213 . In this embodiment, the depletion MOSFET 211 is an always-on transistor. When the voltage difference between the gate and the source of the depletion MOSFET 211 is greater than the threshold voltage of the depletion MOSFET 211 , the depletion MOSFET 211 is turned on. Therefore, the current-to-voltage converter 213 generates a control voltage CV2 according to the current flowing through the depleted MOSFET 211 . However, when the voltage difference between the gate and the source of the depletion MOSFET 211 is smaller than the threshold voltage of the depletion MOSFET 211 , the depletion MOSFET 211 is not turned on. When the depleted MOSFET 211 is not turned on, since no current flows through the depleted MOSFET 211, no power loss will be caused. In a possible embodiment, the control voltage CV1 is provided by an external device (such as the load 120 ). In this example, the external device utilizes the control voltage CV1 to turn on or off the depletion type MOSFET 211 to adjust the output voltage Vout.

The drain of the enhanced MOSFET 212 receives the input voltage Vin, the gate receives the control voltage CV2 , the source provides the output voltage Vout, and the base is coupled to a ground terminal 216 . In this embodiment, the enhancement MOSFET 212 generates the output voltage Vout according to the control voltage CV2. The present invention does not limit the type of enhancement MOSFET 212 . In a possible embodiment, the enhancement MOSFET 212 is an N-type transistor. In this example, when the control voltage CV2 is at a high level, the enhancement mode MOSFET 212 is turned on. At this time, the enhancement MOSFET 212 generates an output voltage Vout according to the input voltage Vin. In a possible embodiment, when the control voltage CV2 is not enough to fully turn on the enhancement MOSFET 212, the output voltage Vout may decrease. When the control voltage CV2 fully turns on the enhancement MOSFET 212, the output voltage Vout increases. Therefore, a stable output voltage Vout can be obtained by controlling the voltage CV2. In this embodiment, the enhancement MOSFET 212 is a high voltage device, and its channel size is larger than that of the depletion MOSFET 211 .

The current-to-voltage converter 213 generates a control voltage CV2 to the gate of the enhancement MOSFET 212 according to the current flowing through the depletion MOSFET 211 . The present invention does not limit the circuit architecture of the current-to-voltage converter 213 . Any circuit structure that can convert current into voltage can be used as the current-to-voltage converter 213 . In this embodiment, the current-to-voltage converter 213 includes an energy storage element 214 and a diode 215 .

One end of the energy storage element 214 is coupled to the source of the depletion MOSFET 211 and the gate of the enhancement MOSFET 212 . The other end of the energy storage element 214 is coupled to the ground 216 . The energy storage element 214 is charged according to the current flowing through the depletion type MOSFET 211 . In this example, the voltage stored in the energy storage element 214 is used as the control voltage CV2. Therefore, even if the depletion MOSFET 211 is not turned on, the enhancement MOSFET 212 can still generate the output voltage Vout according to the control voltage CV2. The invention does not limit the type of the energy storage element 214 . In a possible embodiment, the energy storage element 214 is a capacitor.

The diode 215 is connected in parallel with the energy storage element 214 . In this embodiment, the cathode of the diode 215 is coupled to the source of the depletion MOSFET 211 and the gate of the enhancement MOSFET 212 , and its anode is coupled to the ground terminal 216 . In a possible embodiment, the ground terminal 216 is used to receive a ground voltage (ground). In this embodiment, when the energy storage element 214 stores enough voltage, the enhancement MOSFET 212 is turned on to generate the output voltage Vout.

With the charge stored in the energy storage element 214, the depletion MOSFET 211 does not need to be continuously turned on, thus saving power loss. When the depletion-type MOSFET 211 is not turned on, no current flows through the depletion-type MOSFET 211, so leakage current can be avoided. Furthermore, since the switching speed of the depletion MOSFET 211 is fast, it can ensure that the energy storage element 214 stores enough charge, and can ensure that the enhancement MOSFET 212 can generate the output voltage Vout.

Fig. 3 is another possible embodiment of the control circuit of the present invention. FIG. 3 is similar to FIG. 2 , except that the current-to-voltage converter 313 in FIG. 3 includes a resistor 314 . One end of the resistor 314 is coupled to the source of the depletion MOSFET 311 and the gate of the enhancement MOSFET 312 . The other end of the resistor 314 is coupled to a ground 315 . In this embodiment, the resistor 314 provides a control voltage CV2 according to the current flowing through the depletion MOSFET 311 . In this example, the voltage difference across the resistor 314 is used as the control voltage CV2.

The enhancement MOSFET 312 generates an output voltage Vout according to the control voltage CV2 and the input voltage Vin. Since the operation principle of the enhancement MOSFET 312 is the same as the operation principle of the enhancement MOSFET 212 in FIG. 2 , it will not be repeated here. In addition, the operating principle of the depleted MOSFET 311 in FIG. 3 is similar to the operating principle of the depleted MOSFET 211 in FIG. 2 , so it will not be repeated here.

Fig. 4 is another possible embodiment of the control circuit of the present invention. In this example, the control circuit 410 includes a depletion MOSFET 411 , an enhancement MOSFET 412 , a current-to-voltage converter 413 and a voltage regulator 414 . Since the actions of the depletion MOSFET 411 and the enhancement MOSFET 412 are similar to those of the depletion MOSFET 211 and the enhancement MOSFET 212 in FIG. 2 , they are not repeated here.

The current-to-voltage converter 413 generates a control voltage CV2 according to the current flowing through the depleted MOSFET 411 . The present invention does not limit the circuit architecture of the current-to-voltage converter 413 . In a possible embodiment, the circuit architecture of the current-to-voltage converter 413 is similar to the current-to-voltage converter 213 in FIG. 2 or the current-to-voltage converter 313 in FIG. 3 .

The voltage regulator 415 generates the control voltage CV1 according to the output voltage Vout. In this embodiment, the voltage regulator 415 includes a comparison circuit 415 and a resistor string 416 . The resistor string 416 generates a divided voltage DV according to the output voltage Vout. The resistor string 416 includes resistors 417 and 418 . One end of the resistor 417 is coupled to the source of the enhancement MOSFET 412 . One end of the resistor 417 outputs the divided voltage DV, and is coupled to one end of the resistor 418 . The other end of the resistor 418 is coupled to a ground 419 . The comparison circuit 415 compares the divided voltage DV with the reference voltage RV to determine whether the output voltage Vout reaches a target voltage. The comparison circuit 415 generates the control voltage CV1 according to the comparison result of the divided voltage DV and the reference voltage RV for adjusting the output voltage Vout.

In other embodiments, the comparison circuit 415 directly compares the output voltage Vout with the reference voltage RV. In this example, the resistor string 416 can be omitted, and the comparison circuit 415 is directly coupled to the source of the enhancement MOSFET 412 . When the output voltage Vout is equal to the reference voltage RV, it means that the output voltage Vout has reached the target value. Therefore, the comparison circuit 415 does not turn on the depletion type MOSFET 411 by controlling the voltage CV1. When the output voltage Vout is lower than the reference voltage RV, the comparison circuit 415 controls the depleted MOSFET 411 by controlling the voltage CV1 to increase the current flowing through the depleted MOSFET 411 . In a possible embodiment, the reference voltage RV is provided by an external device (such as the load 120 ). In this example, the reference voltage RV may be stored in an external device in advance.

In a possible embodiment, the depletion MOSFET and the enhancement MOSFET are integrated on the same substrate to reduce the space occupied by the components. 5 is a top view of a possible semiconductor structure of the depletion MOSFET and the enhancement MOSFET of the present invention. In this embodiment, the depletion MOSFET and the enhancement MOSFET are integrated on the same substrate 500 .

As shown, a well region 511 is formed in the substrate 500 . In this embodiment, the well region 511 is a U-shaped structure with an opening facing the direction D1. Doped regions 521 and 522 are formed in the well region 511 . In a possible embodiment, the conductivity type of the doped region 521 is different from that of the doped region 522 . The gate structure 531 is formed on the substrate 500 and overlaps part of the well region 511 . In a possible embodiment, the gate structure 531 serves as a gate of an enhancement MOSFET. A well region 512 is formed in the substrate 500 . The doped region 523 is formed in the well region 512 . In a possible embodiment, the conductivity type of the doped region 523 is the same as that of the doped region 522 . A gate structure 532 is formed on the substrate 500 and overlaps the doped regions 525 and 524 . In a possible embodiment, the gate structure 532 serves as a gate of a depletion MOSFET.

6 is a cross-sectional view of the semiconductor structure of FIG. 5 along the dotted line A-A". The wells 511A and 511B are disposed in the substrate 500. In a possible embodiment, the substrate 500 has a first conductivity type. In this embodiment, Wells 511A and 511B are part of wells 511 of Figure 5. Therefore, wells 511A and 511B are electrically connected to each other. In a possible embodiment, wells 511A and 511B have a first conductivity type. In this example, wells 511A and 511B have a first conductivity type. The doping concentration of the regions 511A and 511B is higher than that of the substrate 500 .

The well region 512 is disposed in the substrate 500 and located between the well regions 511A and 511B. In this embodiment, the well region 512 has the second conductivity type. The second conductivity type is different from the first conductivity type. For example, the first conductivity type is P type, and the second conductivity type is N type. In other embodiments, the first conductivity type is N type, and the second conductivity type is P type.

The doped region 521A is disposed in the well region 511A. In this embodiment, the doped region 521A has the first conductivity type and serves as a bulk of the enhancement MOSFET ET. In a possible embodiment, the doping concentration of the doped region 521A is higher than that of the well region 511A. The doped region 522 has the second conductivity type and is formed in the well region 511A. The doping concentration of the doped region 522 is higher than that of the well region 512 . In this embodiment, the doped region 522 serves as the source of the enhancement MOSFET ET. The gate structure 531 is disposed on the substrate 500 and overlaps part of the well regions 511A and 512 . In this embodiment, the gate structure 531 serves as the gate of the enhancement MOSFET ET. The doped region 523 has the second conductivity type and is formed in the well region 512 . The doping concentration of the doped region 523 is higher than that of the well region 512 . In this embodiment, the doped region 523 serves as the drain of the enhancement MOSFET ET.

In addition, the doped region 523 also serves as the drain of the depletion MOSFET DT. As shown in the figure, the gate structure 532 is disposed on the substrate 500 and overlaps part of the well regions 512 and 511B. In this embodiment, the gate structure 532 serves as the gate of the depletion MOSFET DT. The doped region 525 is formed in the substrate 500 and the well region 511 . As shown, the doped region 525 has a first portion and a second portion, wherein the first portion is located in the substrate 500 and the second portion is located in the well region 511B. In this embodiment, the doped region 525 has the second conductivity type, and serves as a channel of the depletion MOSFET DT. The doped region 524 is disposed in the well region 511B. In this embodiment, the doped region 524 has the second conductivity type and serves as the source of the depletion MOSFET DT. The doped region 521B is disposed in the well region 511B. In this embodiment, the doped region 521B has the first conductivity type and serves as the base of the depletion MOSFET DT. The doped regions 521B and 521A are part of the doped region 521 of FIG. 5 .

Since the depletion MOSFET and the enhancement MOSFET share the same doped region (ie 523 ), the number of wires can be reduced. Furthermore, since the process of the depletion MOSFET is similar to that of the enhancement MOSFET, except that the depletion MOSFET has a doped region (ie 525 ), therefore, the complexity of the process will not be increased.

In other embodiments, the well area 512 further includes a well area 513 . The well region 513 has the second conductivity type. In this example, the well 512 is a deep well. In a possible embodiment, the doping concentration of the doped region 523 is higher than that of the well region 513 . The doping concentration of the well region 513 is higher than that of the well region 512 .

In some embodiments, FIG. 6 further shows isolation structures 541 - 546 . The isolation structures 541 - 546 may be shallow trench isolation (Shallow Trench Isolation; STI) structures or local oxidation (Local Oxidation of Silicon; LOCOS) structures. In other embodiments, the well region 512 further includes doped regions 526A and 526B. The doped region 526A is located under the isolation structure 543 and has the first conductivity type for controlling the breakdown voltage of the enhancement MOSFET ET. The doped region 526B is located under the isolation structure 544 and has the first conductivity type for controlling the breakdown voltage of the depletion MOSFET DT. In one possible embodiment, the doped region 526A is part of a ring structure (not shown), and the doped region 526B is another part of the ring structure. In other words, the doped regions 526A and 526B are electrically connected to each other. In this embodiment, the isolation structure 543 isolates the gate structure 531 from the doped region 523 , and the isolation structure 544 isolates the gate structure 532 from the doped region 523 . In other embodiments, at least one of the doped regions 526A and 526B extends into the well region 513 .

Unless otherwise defined, all terms (including technical and scientific terms) used herein are to be understood by those of ordinary skill in the art to which this invention belongs. In addition, unless expressly stated, the definition of a word in a general dictionary should be interpreted as consistent with the meaning in the article in its related technical field, and should not be interpreted as an ideal state or an overly formal voice.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the art can make some modifications and changes without departing from the spirit and scope of the present invention. retouch. For example, the system, device or method of the embodiments of the present invention can be implemented in physical embodiments of hardware, software, or a combination of hardware and software. Therefore, the protection scope of the present invention shall be determined by the protection scope of the claims.

Claims (10)

1. A control circuit for providing an output voltage to a load, characterized in that the control circuit comprises: A depletion type MOSFET, its drain receives an input voltage, and its gate receives a first control voltage; an enhancement type MOSFET, the drain of which receives the input voltage, and the source of which is coupled to the load; and a current-to-voltage converter for generating a second control voltage to the gate of the enhancement MOSFET according to the current flowing through the depletion MOSFET; wherein the enhanced MOSFET generates the output voltage to the load according to the second control voltage; Wherein the gate of the enhancement MOSFET overlaps with the gate of the depletion MOSFET with a first well region, and the first well region has a first doped region, which serves as the enhancement type MOSFET and the drain of the depletion type MOSFET. 2. The control circuit according to claim 1, wherein the current-to-voltage converter comprises: an energy storage element, coupled to the source of the depletion MOSFET and the gate of the enhancement MOSFET, and charged according to the current flowing through the depletion MOSFET to provide the second control voltage; as well as A diode is connected in parallel with the energy storage element. 3. The control circuit according to claim 1, wherein the current-to-voltage converter is a resistor, and the resistor provides the second control voltage according to the current flowing through the depleted MOSFET. 4. The control circuit according to claim 1, further comprising: A voltage regulator generates the first control voltage according to the output voltage. 5. The control circuit according to claim 4, wherein the voltage regulator comprises: a resistor string processing the output voltage to generate a divided voltage; and A comparator circuit compares the divided voltage with a reference voltage to generate the first control voltage. 6. The control circuit according to claim 5, wherein the reference voltage is provided by the load. 7. A semiconductor structure included in the control circuit of claim 1, comprising: a substrate having a first conductivity type; a second well region, having the first conductivity type, formed in the substrate; a second doped region having a second conductivity type and formed in the second well region; a first gate structure formed on the substrate and overlapping the first well region and the second well region; a third well region, having the first conductivity type, formed in the substrate; a third doped region having the second conductivity type and formed in the third well region; and a second gate structure formed on the substrate and overlapping the second well region and the third well region; Wherein the second doped region serves as the source of an enhancement MOSFET, and the first gate structure serves as the gate of the enhancement MOSFET; Wherein the third doped region serves as the source of the depletion MOSFET, and the second gate structure serves as the gate of the depletion MOSFET; Wherein the first well region has the second conductivity type and is formed in the substrate, and the first doped region has the second conductivity type. 8. The semiconductor structure according to claim 7, further comprising: A fourth doped region having the second conductivity type, the fourth doped region has a first part and a second part, the first part is formed in the substrate, and the second part is formed in In said third well zone; Wherein the fourth doped region serves as the channel of the depletion MOSFET. 9. The semiconductor structure according to claim 8, further comprising: a fourth well region having the second conductivity type and formed in the first well region, wherein the first doped region is located in the fourth well region; a first isolation structure, used to separate the second gate structure from the first doped region; a second isolation structure, used to separate the first gate structure from the first doped region; a fifth doped region having the first conductivity type and formed under the first isolation structure; and A sixth doped region has the first conductivity type and is formed under the second isolation structure. 10. The semiconductor structure according to claim 7, wherein the first conductivity type is P-type, and the second conductivity type is N-type.