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CN111146269A - High electron mobility transistor device and method of manufacturing the same - Google Patents

High electron mobility transistor device and method of manufacturing the same Download PDF

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CN111146269A
CN111146269A CN201811312055.0A CN201811312055A CN111146269A CN 111146269 A CN111146269 A CN 111146269A CN 201811312055 A CN201811312055 A CN 201811312055A CN 111146269 A CN111146269 A CN 111146269A
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layer
layers
substrate
buffer layer
electron mobility
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谢祁峰
王端玮
孙健仁
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Vanguard International Semiconductor Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/472—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having lower bandgap active layer formed on top of wider bandgap layer, e.g. inverted HEMT
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions

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Abstract

一种高电子迁移率晶体管装置及其制造方法，高电子迁移率晶体管装置包含衬底；超晶格缓冲层设置于衬底上方，其中超晶格缓冲层包含多组交替层，每组交替层包含交错排列的至少一AlN层和至少一AlxGa(1‑x)N层，其中0≤x<1；渐变式缓冲层设置于衬底上方，其中渐变式缓冲层包含多个AlyGa(1‑y)N层，其中0≤y<1；以及通道层设置于渐变式缓冲层上方。本发明能够在提高产能的同时，改善高电子迁移率晶体管装置的效能和良率。

Figure 201811312055

A high electron mobility transistor device and a manufacturing method thereof, the high electron mobility transistor device comprising a substrate; a superlattice buffer layer disposed on the substrate, wherein the superlattice buffer layer comprises a plurality of alternating layers, each alternating layer comprising at least one AlN layer and at least one Al x Ga (1-x) N layer arranged in a staggered manner, wherein 0≤x<1; a gradient buffer layer disposed on the substrate, wherein the gradient buffer layer comprises a plurality of Al y Ga (1-y) N layers, wherein 0≤y<1; and a channel layer disposed on the gradient buffer layer. The present invention can improve the performance and yield of the high electron mobility transistor device while increasing the production capacity.

Figure 201811312055

Description

High electron mobility transistor device and method of manufacturing the same
Technical Field
The present invention relates to semiconductor manufacturing technology, and more particularly to a high electron mobility transistor device and a method for manufacturing the same.
Background
A High Electron Mobility Transistor (HEMT), also known as a Heterostructure Field Effect Transistor (HFET) or a modulation-doped field effect transistor (MODFET), is a Field Effect Transistor (FET) composed of semiconductor materials with different energy gaps (energy gaps). A two-dimensional electron gas (2 DEG) layer is created adjacent to the formed interface of the different semiconductor materials. Due to the high electron mobility of the two-dimensional electron gas, the high electron mobility transistor has the advantages of high breakdown voltage, high electron mobility, low on-resistance, low input capacitance and the like, and is suitable for high-power elements.
However, since the substrate material and the semiconductor layer material have different lattice differences, different thermal expansion coefficients, and other problems, which easily cause structural deformation in the hemt, a buffer layer is disposed between the substrate and the semiconductor layer to alleviate the structural deformation and possible defects caused thereby. In order to improve the conventional high electron mobility transistor in various aspects, such as forming a semiconductor layer with better crystal properties and reducing the manufacturing cost, there is still a need to continuously improve the buffer layer.
Disclosure of Invention
According to some embodiments of the present invention, high electron mobility transistor devices are provided. The device includes a substrate; a superlattice buffer layer disposed above the substrate, wherein the superlattice buffer layer comprises multiple sets of alternating layers, each set of alternating layers comprising at least one AlN (aluminum nitride) layer and at least one Al layer arranged in a staggered mannerxGa(1-x)N layers, wherein x is more than or equal to 0<1; a graded buffer layer disposed above the substrate, wherein the graded buffer layer comprises a plurality of AlyGa(1-y)N layers, wherein y is more than or equal to 0<1; and the channel layer is arranged above the gradual change type buffer layer.
In some embodiments, in each set of alternating layers, the Al' sxGa(1-x)The N layers have the same value of x.
In some embodiments, these Al layers are for different sets of alternating layersxGa(1-x)The N layers have different values of x.
In some embodiments, the Al of the set of alternating layers adjacent to the substratexGa(1-x)The value of x of the N layer is greater than the Al of the set of alternating layers remote from the substratexGa(1-x)X value of N layers.
In some embodiments, in each set of alternating layers, the AlN layer has a thickness in the range of 1nm to 20nm, and the AlxGa(1-x)The thickness of the N layer is in the range of 5nm to 100 nm.
In some embodiments, AlxGa(1-x)The ratio of the thickness of the N layer to the thickness of the AlN layer is in the range of 3 to 10.
In some embodiments, these AlyGa(1-y)The thickness of each of the N layers ranges from 50nm to 500 nm.
In some embodiments, Al adjacent to the substrateyGa(1-y)The y value of the N layer is larger than that of Al far away from the substrateyGa(1-y)Y value of N layers.
In some embodiments, a graded buffer layer is disposed over the superlattice buffer layer.
In some embodiments, the hemt device further comprises a nucleation layer disposed between the substrate and the superlattice buffer layer, wherein the nucleation layer comprises aluminum nitride, aluminum gallium nitride, or a combination thereof.
In some embodiments, the hemt device further comprises a barrier layer disposed over the channel layer; and a source, a drain and a gate disposed above the barrier layer.
According to some embodiments of the present invention, methods of fabricating high electron mobility transistor devices are provided. The method comprises the following steps: forming a substrate; forming a superlattice buffer layer above the substrate, wherein the superlattice buffer layer comprises a plurality of groups of alternating layers, each group of alternating layers comprises at least one AlN layer and at least one AlxGa (1-x) N layer which are staggered, and x is more than or equal to 0 and less than 1; forming a graded buffer layer over a substrate, wherein the graded buffer layer comprises a plurality of AlyGa (1-y) N layers, wherein y is greater than or equal to 0 and less than 1; and forming a channel layer above the graded buffer layer.
In some embodiments, in each set of alternating layers, the Al' sxGa(1-x)The N layers have the same value of x.
In some embodiments, these Al layers are for different sets of alternating layersxGa(1-x)The N layers have different values of x.
In some embodiments, the Al of the set of alternating layers adjacent to the substratexGa(1-x)The value of x of the N layer is greater than the Al of the set of alternating layers remote from the substratexGa(1-x)X value of N layers.
In some embodiments, in each set of alternating layers, the AlN layer has a thickness in the range of 1nm to 20nm, and AlxGa(1-x)The thickness of the N layer is in the range of 5nm to 100nm, and AlxGa(1-x)The ratio of the thickness of the N layer to the thickness of the AlN layer is in the range of 3 to 10.
In some embodiments, these AlyGa(1-y)The thickness of each of the N layers ranges from 50nm to 500 nm.
In some embodiments, Al adjacent to the substrateyGa(1-y)The y value of the N layer is larger than that of Al far away from the substrateyGa(1-y)Y value of N layers.
In some embodiments, a graded buffer layer is formed over the superlattice buffer layer.
In some embodiments, the method further comprises forming a nucleation layer between the substrate and the superlattice buffer layer, wherein the nucleation layer comprises aluminum nitride (AIGaN), aluminum gallium nitride (AlGaN), or a combination thereof.
The invention can improve the efficiency and yield of the high electron mobility transistor device while improving the productivity.
Drawings
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale and are merely illustrative. In fact, the dimensions of the elements may be arbitrarily expanded or reduced to clearly illustrate the features of the present invention.
Fig. 1-5 are cross-sectional views depicting various stages in the fabrication of a high electron mobility transistor device, according to some embodiments.
Reference numerals:
100-high electron mobility transistor devices;
110-substrate;
120-nucleating layer;
130 superlattice buffer layer (superlattice buffer layer);
132-a first set of alternating layers;
132a、134a、136a～AlxGa(1-x)n layers;
132b, 134b, 136b to AlN layers;
134 to a second set of alternating layers (alternating layers);
136 to a third set of alternating layers;
140-graded buffer layer (gradient buffer layer);
142 to first AlyGa(1-y)N layers;
144 to second AlyGa(1-y)N layers;
146 to third AlyGa(1-y)N layers;
150-channel layer (channel layer);
152-two-dimensional electron gas;
160 barrier layers;
170-source electrode;
180-grid electrode;
190 to the drain.
Detailed Description
Some examples are summarized below so that those skilled in the art can more easily understand the present invention, but these examples are not intended to limit the present invention. It will be appreciated that those skilled in the art may modify the embodiments described below, for example, by changing the order of manufacture and/or by including more or less steps than those described herein, as desired. In addition, other elements may be added to the embodiments described below, for example, a description of "forming a second element on a first element" may include embodiments in which the first element is in direct contact with the second element, and may also include embodiments in which there are other elements between the first element and the second element such that the first element is not in direct contact with the second element, and the relationship between the first element and the second element may change as the device is operated or used in different orientations.
In accordance with some embodiments of the present invention, the placement of a superlattice buffer layer and a graded buffer layer between a substrate and a channel layer of a hemt device is described to improve the performance and yield of the hemt device while increasing the throughput.
Fig. 1-5 are cross-sectional views depicting various stages in the fabrication of a high electron mobility transistor device 100, according to some embodiments. As shown in fig. 1, the hemt device 100 includes a substrate 110, the substrate 110 may be a bulk semiconductor substrate or include a composite substrate formed of different materials, and any substrate material suitable for semiconductor devices may be used, such as silicon, germanium, silicon carbide, gallium nitride, sapphire.
In some embodiments, a nucleation layer 120 is formed over the substrate 110 to mitigate lattice differences between the substrate 110 and the overlying grown film layers. For example, the material of the nucleation layer 120 may include, for example, aluminum Nitride (AlN), aluminum Gallium Nitride (AlGaN), similar materials, or combinations of the foregoing, and the thickness of the nucleation layer 120 may be in a range of about 100 nanometers (nm) to about 1000nm, such as about 200 nm. The formation of the nucleation layer 120 may include a Deposition process, such as Metal Organic Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy (MBE), Liquid Phase Epitaxy (LPE), or other Deposition techniques.
As shown in fig. 2, in some embodiments, a superlattice buffer layer 130 is formed over the nucleation layer 120. The nucleation layer 120 is selective. In other embodiments, the nucleation layer 120 is not provided and the superlattice buffer layer 130 is formed directly on the substrate. The formation of the superlattice buffer layer 130 may include a deposition process such as, for example, organometallic chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, or other deposition techniques.
The superlattice buffer layer 130 includes a plurality of sets of alternating layers, such as in the embodiment depicted in fig. 2, the superlattice buffer layer 130 includes a first set of alternating layers 132 nearest the substrate, a second set of alternating layers 134, and a third set of alternating layers 136 furthest from the substrate. Each set of alternating layers comprises at least one aluminum Nitride (AlN) layer and at least one aluminum Gallium Nitride (Al) layer arranged alternatelyxGa(1-x)N) layer, wherein the aluminum gallium nitride can be varied according to the aluminum content, with AlxGa(1-x)N is represented by, wherein 0. ltoreq. x<1. As shown in FIG. 2, the first set of alternating layers 132 comprises three staggered layers of AlxGa(1-x)N layers 132a and three AlN layers 132b, and a second set of alternating layers 134 comprising three staggered layers of AlxGa(1-x)N layer 134a and three AlN layers 134b, and a third set of alternating layers 136 comprising three layers of Al staggeredxGa(1-x)N layer 136a and three AlN layers 136 b.
Although in the embodiment of fig. 2, the superlattice buffer layer 130 includes a first set of alternating layers 132, a second set of alternating layers 134, and a third set of alternating layers 136, and each of these alternating layers includes three sets of Al arranged in an alternating mannerxGa(1-x)N layer and AlN layer, but the number of alternate layers and/or Al may be increased or decreased as requiredxGa(1-x)The number of N layers and AlN layers, and for different sets of alternating layers, may each have a different number of staggered Al layersxGa(1-x)An N layer and an AlN layer.
In each set of alternating layers, AlxGa(1-x)The values of x for the N layers are the same, while for different sets of alternating layers, AlxGa(1-x)The x values of the N layers are different. That is, Al having the same aluminum contentxGa(1-x)The N layers are the same set of alternating layers. In addition, a set of alternating layers of Al adjacent the substratexGa(1-x)The N layer has a value of x greater than Al of another set of alternating layers remote from the substratexGa(1-x)X value of N layers. In other words, the set of alternating layers of Al closest to the substratexGa(1-x)The N layer has a maximum aluminum contentAnd the aluminum content generally decreases as the alternating layers move away from the substrate.
In addition, the value of x, i.e., Al, can be adjusted as desiredxGa(1-x)Aluminum content in the N layer. For example, in the embodiment of FIG. 2, the first set of alternating layers 132 of AlxGa(1-x)The value of x for the N layer 132a is about 0.75 and the second set of alternating layers 134 is AlxGa(1-x)The value of x for the N layer 134a is about 0.5 and the third set of alternating layers 136 is AlxGa(1X) the value of x of the N layer 136a is about 0.25, so AlxGa(1-x)The N layers 132a, 134a, and 136a may also be referred to as Al, respectively0.75Ga0.25N layer, Al0.5Ga0.5N layer and Al0.25Ga0.75And N layers.
According to some embodiments, in each set of alternating layers, AlxGa(1-x)The thickness of the N layer is in the range of about 5nm to about 100nm, and the thickness of the AlN layer is in the range of about 1nm to about 20nm, such as AlxGa(1-x)The thickness of the N layer is about 20nm and the thickness of the AlN layer is about 5 nm. In some embodiments, AlxGa(1-x)The ratio of the thickness of the N layer to the thickness of the AlN layer ranges from about 3 to about 10. Although FIG. 2 depicts the first, second, and third sets of alternating layers 132, 134, 136 and the Al in these alternating layersxGa(1-x)The N layers 132a, 134a, 136a and the AlN layers 132b, 134b, 136b have the same thickness, but the present invention is not limited thereto, and each set of alternating layers and/or the staggered arrangement of Al may be adjusted as desiredxGa(1-x)Thicknesses of the N and AlN layers, and may each have a staggered arrangement of Al of different thicknesses for different sets of alternating layersxGa(1-x)An N layer and an AlN layer. In some embodiments, the superlattice buffer layer 130 has a thickness in a range from about 0.05 micrometers (μm) to about 10 μm, such as about 0.2 μm.
As shown in fig. 3, in some embodiments, a graded buffer layer 140 is formed over the superlattice buffer layer 130. The formation of graded buffer layer 140 may include a deposition process such as, for example, metalorganic chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, or other deposition techniques. Gradual bufferLayer 140 comprises a plurality of aluminum gallium nitride (Al) layersyGa(1-y)N) layer, and may be based on different aluminum contents, in terms of AlyGa(1-y)N represents wherein 0. ltoreq. y<1. Al adjacent to the substrateyGa(1-y)The N layer has a y value greater than Al of another set of alternating layers remote from the substrateyGa(1-y)Y value of N layers. In other words, the set of alternating layers of Al closest to the substrateyGa(1-y)The N layers have a maximum aluminum content, and the aluminum content generally decreases as the alternating layers move away from the substrate.
In the embodiment illustrated in fig. 3, the graded buffer layer 140 comprises the first Al closest to the substrateyGa(1-y)N layer 142, second AlyGa(1-y)N layer 144 and third Al furthest from the substrateyGa(1-y)N layers 146. Al can be increased or decreased according to the requirementyGa(1-y)The number of N layers, and the value of y, i.e. Al, can be adjustedyGa(1-y)Aluminum content in the N layer. For example, in the embodiment of FIG. 3, the first AlyGa(1-y)The y value of the N layer 142 is about 0.75, second AlyGa(1-y)The y value of the N layer 144 is about 0.5, third AlyGa(1-y)The y value of N layer 146 is about 0.25, thus first AlyGa(1-y)N layer 142, second AlyGa(1-y)N layer 144 and third AlyGa(1-y)The N layers 146 may also be referred to as Al, respectively0.75Ga0.25N layer, Al0.5Ga0.5N layer and Al0.25Ga0.75And N layers.
According to some embodiments, AlyGa(1-y)The thickness of the N layer is in the range of about 50nm to about 500nm, for example about 100 nm. Although the first Al is illustrated in FIG. 3yGa(1-y)N layer 142, second AlyGa(1-y)N layer 144 and third AlyGa(1-y)The N layers 146 have the same thickness, but the present invention is not limited thereto, and each Al layer can be adjusted as desiredyGa(1-y)The thickness of the N layer. In some embodiments, the thickness of graded buffer layer 140 is in a range from about 0.1 μm to about 10 μm, such as about 0.3 μm.
Although fig. 3 shows that the thickness of the superlattice buffer layer 130 is greater than that of the graded buffer layer 140, the invention is not limited thereto, and the thicknesses of the two layers can be adjusted according to the requirement. In some embodiments, the combined thickness of superlattice buffer layer 130 and graded buffer layer 140 is in a range from about 0.1 μm to about 10 μm, such as about 0.3 μm. In some embodiments, the ratio of the thickness of superlattice buffer layer 130 to the thickness of graded buffer layer 140 is in a range of about 0.2 to about 2, such as about 0.75.
According to some embodiments of the present invention, the superlattice buffer layer 130 and the graded buffer layer 140 are disposed above the substrate 110 of the hemt device 100, so as to alleviate lattice difference between the substrate 110 and other layers formed thereon, and avoid defects such as warpage (bow) or cracks generated by lattice mismatch when the layers are formed, thereby improving yield of the hemt device 100.
In addition, since the manufacturing process time of the graded buffer layer 140 is shorter than that of the superlattice buffer layer 130, for the buffer layer with the same thickness formed on the substrate 110, the buffer layer including the superlattice buffer layer 130 and the graded buffer layer 140 is formed according to some embodiments of the present invention, which can greatly shorten the manufacturing process time and improve the productivity of the hemt device 100 compared to the case of forming only the superlattice buffer layer 130.
On the other hand, the graded buffer layer 140 has a poor effect of mitigating lattice difference compared to the superlattice buffer layer 130. For forming a buffer layer with the same thickness above a substrate, providing a buffer layer including the superlattice buffer layer 130 and the graded buffer layer 140 according to some embodiments of the invention may form a film with better crystalline quality above than forming only the graded buffer layer 140, and thus may increase the thickness of a film such as a channel layer.
In addition, according to some embodiments of the present invention, the superlattice buffer layer 130 is disposed above the substrate 110 of the hemt device 100, and then the graded buffer layer 140 is disposed, and the underlying superlattice buffer layer 130 may block dislocations in the substrate 110 from entering other layers formed above the graded buffer layer 140, so as to further improve the crystallization quality of the other layers above the substrate compared to the superlattice buffer layer 130 disposed after the graded buffer layer 140 is disposed.
Next, as shown in fig. 4, a channel layer 150 is formed on the graded buffer layer 140. In some embodiments, the material of the channel layer 150 may comprise a group III nitride, such as a III-V compound semiconductor material. In some embodiments, the material of the channel layer 150 includes Gallium Nitride (GaN). The channel layer 150 may be doped or undoped as desired. The formation of the channel layer 150 may include a deposition process such as, for example, metalorganic chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, or other deposition techniques. The thickness of the channel layer 150 may be selected as desired. For example, in some embodiments, the thickness of the channel layer 150 is in a range between about 10nm and about 1000nm, such as about 200 nm.
As shown in fig. 5, a barrier layer 160 is formed over the channel layer 150, according to some embodiments. The formation of the barrier layer 160 may include a deposition process such as metalorganic chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, or other deposition techniques. The thickness of the barrier layer 160 can be selected as desired. In some embodiments, the material of the barrier layer 160 may comprise a group III nitride, such as a group III-V compound semiconductor material. The barrier layer 160 may comprise a single layer or a multi-layer structure. For example, the barrier layer 160 includes AlN, AlGaN, AlInN, AlGaInN, similar materials, or combinations thereof. Barrier layer 160 may be doped or undoped as desired. The materials of the channel layer 150 and the barrier layer 160 are selected to produce a two-dimensional electron gas 152 at the interface therebetween.
Then, according to some embodiments, a source 170, a gate 180, and a drain 190 are disposed over the barrier layer 160, forming the hemt device 100. The source 170, gate 180, and drain 190 may be formed using any suitable materials, processes, and sequences, and the pitch and position of the elements may be adjusted as desired. As shown in fig. 5, according to some embodiments, the source electrode 170 and the drain electrode 190 penetrate the barrier layer 160 into the channel layer 150, and the gate electrode 180 is located on the surface of the barrier layer 160, but the present invention is not limited thereto, and may be in other various arrangements or configurations. For example, a p-type doped gallium nitride (p-GaN) layer may be disposed between the gate 180 and the barrier layer 160 such that the gate 180 does not contact the barrier layer 160, and the resulting hemt device 100 is an enhancement mode (E-mode) device; alternatively, no p-type doped gallium nitride (p-GaN) layer is disposed between the gate 180 and the barrier layer 160, and the resulting hemt device 100 is a depletion mode (D-mode) device.
In general, when a channel layer of a high electron mobility transistor device is formed, defects such as cracks or warpage are easily formed in the channel layer due to a lattice difference between the channel layer and a substrate. These defects become severe as the thickness of the channel layer increases, affecting the performance of the hemt device, and thus the thickness of the channel layer is limited. Some embodiments of the present invention provide a superlattice buffer layer and a graded buffer layer between a substrate and a channel layer of a high electron mobility transistor device, and adjust the aluminum content in the superlattice buffer layer and the graded buffer layer, so as to alleviate the lattice difference between the channel layer and the substrate formed above, reduce the defects generated thereby, improve the crystal quality of the channel layer, further increase the thickness of the channel layer, and improve the performance and yield of the high electron mobility transistor device.
In addition, compared with the superlattice buffer layer, the manufacturing process time of the graded buffer layer is shorter, but the effect of avoiding the defects generated by the channel layer is not as good as that of the superlattice buffer layer. Therefore, for forming the buffer layer with the same thickness, the buffer layer including the superlattice buffer layer and the graded buffer layer is arranged above the substrate according to some embodiments of the invention, compared with the situation that only the superlattice buffer layer is arranged, the manufacturing process time can be greatly shortened, and therefore the production performance of the high electron mobility transistor device can be improved; on the other hand, compared with the method of only arranging the gradual change type buffer layers, a channel layer with better crystal quality can be formed above the buffer layers, and the yield of the high electron mobility transistor device is improved.
In addition, according to some embodiments of the present invention, the superlattice buffer layer is disposed above the substrate of the hemt device, and then the graded buffer layer is disposed, so that dislocation in the substrate can be effectively prevented from entering the channel region, and the crystallization quality of the channel layer is further improved. Therefore, some embodiments of the invention can improve the performance and yield of the high electron mobility transistor device while improving the productivity.
While the invention has been described above in terms of several embodiments, these embodiments are not intended to limit the invention. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for modifying or replacing various features and/or advantages of the present disclosure in order to provide those skilled in the art with the desired functionality and/or functionality. It will also be appreciated by those skilled in the art that such modifications or arrangements do not depart from the spirit and scope of the invention. Therefore, the protection scope of the present invention is subject to the claims.

Claims (20)

1.一种高电子迁移率晶体管装置，其特征在于，包括：1. A high electron mobility transistor device, characterized in that, comprising: 一衬底；a substrate; 一超晶格缓冲层，设置于所述衬底上方，其中所述超晶格缓冲层包括多组交替层，每组交替层包括交错排列的至少一AlN层和至少一AlxGa(1-x)N层，其中0≤x<1；A superlattice buffer layer disposed above the substrate, wherein the superlattice buffer layer includes a plurality of groups of alternating layers, each group of alternating layers includes at least one AlN layer and at least one AlxGa (1- x) N layers, where 0≤x<1; 一渐变式缓冲层，设置于所述衬底上方，其中所述渐变式缓冲层包括多个AlyGa(1-y)N层，其中0≤y<1；以及a graded buffer layer disposed above the substrate, wherein the graded buffer layer includes a plurality of AlyGa (1-y) N layers, where 0≤y<1; and 一通道层，设置于所述渐变式缓冲层上方。A channel layer is disposed above the graded buffer layer. 2.根据权利要求1所述的高电子迁移率晶体管装置，其特征在于，在每组交替层中，所述AlxGa(1-x)N层具有相同的x值。2. The high electron mobility transistor device of claim 1, wherein the AlxGa (l-x) N layers have the same value of x in each set of alternating layers. 3.根据权利要求1所述的高电子迁移率晶体管装置，其特征在于，对不同组交替层而言，所述AlxGa(1-x)N层具有不同的x值。3. The high electron mobility transistor device of claim 1, wherein the AlxGa (1-x) N layers have different x values for different sets of alternating layers. 4.根据权利要求3所述的高电子迁移率晶体管装置，其特征在于，邻近所述衬底的所述交替层的所述AlxGa(1-x)N层的x值大于远离所述衬底的所述交替层的所述AlxGa(1-x)N层的x值。4. The high electron mobility transistor device of claim 3, wherein the AlxGa (l-x) N layer adjacent to the alternating layers of the substrate has a value of x greater than a value farther from the substrate The x value of the AlxGa (1-x) N layer of the alternating layers of the substrate. 5.根据权利要求1所述的高电子迁移率晶体管装置，其特征在于，在每组交替层中，所述AlN层的厚度在1nm至20nm的范围，且所述AlxGa(1-x)N层的厚度在5nm至100nm的范围。5. The high electron mobility transistor device of claim 1, wherein in each set of alternating layers, the AlN layer has a thickness in the range of 1 nm to 20 nm, and the AlxGa (1-x ) The thickness of the N layer is in the range of 5 nm to 100 nm. 6.根据权利要求1所述的高电子迁移率晶体管装置，其特征在于，所述AlxGa(1-x)N层的厚度对所述AlN层的厚度的比值在3至10的范围。6 . The high electron mobility transistor device of claim 1 , wherein the ratio of the thickness of the AlxGa (1-x) N layer to the thickness of the AlN layer is in the range of 3 to 10. 7 . 7.根据权利要求1所述的高电子迁移率晶体管装置，其特征在于，所述AlyGa(1-y)N层中的每一个的厚度在50nm至500nm的范围。7 . The high electron mobility transistor device of claim 1 , wherein each of the AlyGa (1-y) N layers has a thickness in the range of 50 nm to 500 nm. 8 . 8.根据权利要求1所述的高电子迁移率晶体管装置，其特征在于，邻近所述衬底的所述AlyGa(1-y)N层的y值大于远离所述衬底的所述AlyGa(1-y)N层的y值。8. The high electron mobility transistor device of claim 1, wherein the y value of the AlyGa (1-y) N layer adjacent to the substrate is greater than the value of y farther from the substrate The y value of the AlyGa (1-y) N layer. 9.根据权利要求1所述的高电子迁移率晶体管装置，其特征在于，所述渐变式缓冲层设置于所述超晶格缓冲层上方。9 . The high electron mobility transistor device of claim 1 , wherein the graded buffer layer is disposed above the superlattice buffer layer. 10 . 10.根据权利要求1所述的高电子迁移率晶体管装置，其特征在于，更包括一成核层，设置于所述衬底和所述超晶格缓冲层之间，其中所述成核层包括氮化铝、氮化铝镓或二者的组合。10. The high electron mobility transistor device of claim 1, further comprising a nucleation layer disposed between the substrate and the superlattice buffer layer, wherein the nucleation layer Includes aluminum nitride, aluminum gallium nitride, or a combination of both. 11.根据权利要求10所述的高电子迁移率晶体管装置，其特征在于，更包括：11. The high electron mobility transistor device of claim 10, further comprising: 一阻障层，设置于所述通道层上方；以及a barrier layer disposed over the channel layer; and 一源极、一漏极、一栅极，设置于所述阻障层上方。A source electrode, a drain electrode, and a gate electrode are disposed above the barrier layer. 12.一种高电子迁移率晶体管装置的制造方法，其特征在于，包括：12. A method for manufacturing a high electron mobility transistor device, comprising: 形成一衬底；forming a substrate; 在所述衬底上方形成一超晶格缓冲层，其中所述超晶格缓冲层包括多组交替层，每组交替层包括交错排列的至少一AlN层和至少一AlxGa(1-x)N层，其中0≤x<1；A superlattice buffer layer is formed over the substrate, wherein the superlattice buffer layer includes a plurality of sets of alternating layers, each set of alternating layers including at least one AlN layer and at least one AlxGa (1-x ) N layers, where 0≤x<1; 在所述衬底上方形成一渐变式缓冲层，其中所述渐变式缓冲层包括多个AlyGa(1-y)N层，其中0≤y<1；以及forming a graded buffer layer over the substrate, wherein the graded buffer layer includes a plurality of layers of AlyGa (1-y) N, where 0≤y<1; and 在所述渐变式缓冲层上方形成一通道层。A channel layer is formed over the graded buffer layer. 13.根据权利要求12所述的高电子迁移率晶体管装置的制造方法，其特征在于，在每组交替层中，所述AlxGa(1-x)N层具有相同的x值。13. The method of manufacturing a high electron mobility transistor device according to claim 12, wherein the AlxGa (1-x) N layers have the same value of x in each set of alternating layers. 14.根据权利要求12所述的高电子迁移率晶体管装置的制造方法，其特征在于，对不同组交替层而言，所述AlxGa(1-x)N层具有不同的x值。14 . The method of claim 12 , wherein the AlxGa (1-x) N layers have different x values for different groups of alternating layers. 15 . 15.根据权利要求14所述的高电子迁移率晶体管装置的制造方法，其特征在于，邻近所述衬底的所述交替层的所述AlxGa(1-x)N层的x值大于远离所述衬底的所述交替层的所述AlxGa(1-x)N层的x值。15. The method of manufacturing a high electron mobility transistor device of claim 14, wherein the AlxGa (1-x) N layers adjacent to the alternating layers of the substrate have an x value greater than Value of x for the AlxGa (1-x) N layer of the alternating layers away from the substrate. 16.根据权利要求12所述的高电子迁移率晶体管装置的制造方法，其特征在于，在每组交替层中，所述AlN层的厚度在1nm至20nm的范围，所述AlxGa(1-x)N层的厚度在5nm至100nm的范围，且所述AlxGa(1-x)N层的厚度对所述AlN层的厚度的比值在3至10的范围。16. The method of manufacturing a high electron mobility transistor device according to claim 12, wherein in each group of alternating layers, the AlN layer has a thickness in the range of 1 nm to 20 nm, and the Al x Ga (1 nm) -x) The thickness of the N layer is in the range of 5 nm to 100 nm, and the ratio of the thickness of the AlxGa (1-x) N layer to the thickness of the AlN layer is in the range of 3 to 10. 17.根据权利要求12所述的高电子迁移率晶体管装置的制造方法，其特征在于，所述AlyGa(1-y)N层中的每一个的厚度在50nm至500nm的范围。17 . The method of manufacturing a high electron mobility transistor device according to claim 12 , wherein the thickness of each of the AlyGa (1-y) N layers is in the range of 50 nm to 500 nm. 18 . 18.根据权利要求12所述的高电子迁移率晶体管装置的制造方法，其特征在于，邻近所述衬底的所述AlyGa(1-y)N层的y值大于远离所述衬底的所述AlyGa(1-y)N层的y值。18. The method for manufacturing a high electron mobility transistor device according to claim 12, wherein the y value of the AlyGa (1-y) N layer adjacent to the substrate is greater than that far from the substrate The y value of the AlyGa (1-y) N layer. 19.根据权利要求12所述的高电子迁移率晶体管装置的制造方法，其特征在于，所述渐变式缓冲层形成于所述超晶格缓冲层上方。19 . The manufacturing method of the high electron mobility transistor device of claim 12 , wherein the graded buffer layer is formed above the superlattice buffer layer. 20 . 20.根据权利要求12所述的高电子迁移率晶体管装置的制造方法，其特征在于，更包括在所述衬底和所述超晶格缓冲层之间形成一成核层，其中所述成核层包括氮化铝、氮化铝镓或二者的组合。20 . The method for manufacturing a high electron mobility transistor device according to claim 12 , further comprising forming a nucleation layer between the substrate and the superlattice buffer layer, wherein the nucleation layer is formed. 21 . The core layer includes aluminum nitride, aluminum gallium nitride, or a combination of both.
CN201811312055.0A 2018-11-06 2018-11-06 High electron mobility transistor device and method of manufacturing the same Pending CN111146269A (en)

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