CN111142808B - Access device and access method - Google Patents

Abstract

The present application discloses an access device and an access method. The local data storage buffer in the access device is used to store data of at least one data type calculated by the target hardware acceleration engine; the write control unit connected to the first number of basic write ports in the local data storage buffer uses for parallel writing data of at least one data type to be written corresponding to the target hardware acceleration engine into the corresponding data storage area of the local data storage buffer; connected to the first number of basic read ports in the local data storage buffer The read control unit is configured to read data of the target data type to be read by the target hardware acceleration engine in parallel from the data storage area of the local data storage buffer. The access device can flexibly configure the local data storage buffer according to the data volume of different data types, and the length of the access data is not limited.

Description

Access device and access method

technical field

The present application relates to the technical field of integrated circuits, and in particular, to an access device and an access method.

Background technique

With the development of the Internet of Things and artificial intelligence, the computing power requirements of hardware are getting higher and higher, and a large amount of data often needs to be processed by hardware acceleration modules. In order to meet the requirements of fast data access and data cache, the hardware acceleration module (or "hardware acceleration engine") usually adds an on-chip data storage buffer locally, that is, the local data storage buffer. The data buffer directly participates in the core operation in the data path, and is accessed by multiple modules in the hardware acceleration engine, so the local data storage buffer is required to provide the operation function of multi-port parallel access.

At present, for processors with low main frequency (or "clock frequency"), the data of different storage units in the multi-port shared memory can be accessed in k times in a relatively short period of time, that is, time-sharing parallel access can be realized to complete different Parallel access to ports. Secondly, the shared memory needs to use a memory chip with a high enough frequency to meet the requirements of time-sharing and parallel access. This kind of multi-port time-sharing and parallel access method is only suitable for data transmission requirements with low throughput, that is, the structure of the shared memory It cannot realize the operation of multi-port parallel access.

When a multi-core processor with a high main frequency accesses a multi-port shared memory, the k-port memory controller uses a k*n crossbar or an on-chip network to connect n different memory units together, and the k ports use a crossbar or an on-chip network to connect n different memory units together. , and simultaneously access n different storage units to realize multi-port parallel access to memory.

However, the crossbar switch in such a multi-port shared memory can complete the crossover operation of multiple ports, but the crossbar switch only supports the read and write of fixed-length data, that is, it can only complete the read and write operations of the fixed-length data buffer, and the fixed-length data buffer can only be read and written. The data type stored in the data buffer is also a fixed type. To store data of other data types in the data buffer, it is necessary to configure the data storage area of the corresponding data type in advance, resulting in low flexibility.

SUMMARY OF THE INVENTION

The embodiments of the present application provide an access device and an access method, which solve the above-mentioned problems in the prior art, improve the flexibility of configuring data types in the local data storage buffer, and solve the problem of local data storage in the prior art The buffer is only limited to support fixed-length data read and write operations.

In a first aspect, an access device is provided, the device may include:

a local data storage buffer, used for storing data of at least one data type corresponding to the target hardware acceleration engine; the local data storage buffer is a different data type composed of a first number of basic storage modules with uniform address codes A data storage area; wherein, the first quantity is determined according to the amount of data required for calculation by the target hardware acceleration engine, and each basic storage module has a basic read port and a basic write port;

a write control unit connected to the first number of basic write ports in the local data storage buffer, for parallel writing data of at least one data type to be written corresponding to the target hardware acceleration engine into the corresponding data storage area of the local data storage buffer;

The read control unit connected to the first number of basic read ports in the local data storage buffer is used to read the target hardware acceleration engine to be read in parallel from the data storage area of the local data storage buffer. The data of the target data type to read.

In an optional implementation, the write control unit is further configured to determine the number of write ports of the write control unit according to the number of types of the at least one data type;

The read control unit is further configured to determine the number of read ports of the read control unit according to the type number of the target data type.

In an optional implementation, if the number of write ports of the write control unit is a second number N, the second number N of write ports of the write control unit are connected to the target hardware acceleration engine , the output ports of the first quantity K of the write control unit are connected in one-to-one correspondence with the basic write ports of the first quantity K;

If the number of read ports of the read control unit is a third number M, the read ports of the third number M of the read control unit are connected to the target hardware acceleration engine, and the read ports of the read control unit are connected to the target hardware acceleration engine. The input ports of the first number K are connected to the basic read ports of the first number K in a one-to-one correspondence.

In an optional implementation, the write control unit includes the second number N of demultiplexers and the first number K of demultiplexers; each demultiplexer includes an input port and the first number K of output ports, each multiplexer including the second number N of input ports and one output port;

The write ports of the second quantity N of the write control unit are connected in one-to-one correspondence with the input ends of the demultiplexers of the second quantity N;

The output terminals of the first quantity K of each demultiplexer are connected in one-to-one correspondence with the input terminals of the first quantity K of the multiplexers;

The output of each multiplexer is connected to the basic write port to be written in the corresponding data storage area.

In an optional implementation, the read control unit includes a third number M of multiplexers and the first number K of demultiplexers; each multiplexer includes a first number K of inputs ports and an output port, each demultiplexer includes an input port and a third number M of output ports;

The read ports of the third quantity M of the read control unit are connected in one-to-one correspondence with the input ends of the multiplexers of the third quantity M;

The input terminals of the first quantity K in each multiplexer are respectively connected with the output terminals of the first quantity K of the demultiplexers in one-to-one correspondence;

The input of each demultiplexer is connected to the base read port to be read in the corresponding data storage area.

In an optional implementation, if the target hardware acceleration engine is a convolutional neural network engine, the at least one data type includes a weight type, an eigenvalue type, a convolution part, and a type.

In a second aspect, an access method is provided, applied in an access device, the method may include:

Write data of at least one data type corresponding to the target hardware acceleration engine into the data storage area of the local data storage buffer in the access device in parallel;

storing data of at least one data type corresponding to the target hardware acceleration engine;

Alternatively, data of the target data type to be read by the target hardware acceleration engine is read in parallel from the data storage area of the local data storage buffer.

In an optional implementation, according to the type number of at least one data type corresponding to the target hardware acceleration engine, determine the number of write ports written to the control unit in the access device;

And, the number of read ports of the read control unit in the access device is determined according to the number of types of target data types to be read by the target hardware acceleration engine.

In a third aspect, an electronic device is provided, the electronic device includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus;

memory for storing computer programs;

The processor is configured to implement the method steps described in any one of the second aspect above when executing the program stored in the memory.

In a fourth aspect, a computer-readable storage medium is provided, and a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, the method steps of any one of the second aspect above are implemented.

An embodiment of the present invention provides an access device, in which a local data storage buffer is used to store data of at least one data type corresponding to a target hardware acceleration engine; the local data storage buffer is encoded by a uniform address Data storage areas of different data types composed of a first number of basic storage modules; wherein, the first number is determined according to the amount of data required for calculation by the target hardware acceleration engine, and each basic storage module has a basic read port and a basic write port. The write control unit connected to the first number of basic write ports in the local data storage buffer is configured to write data of at least one data type to be written corresponding to the target hardware acceleration engine into the local data storage buffer in parallel. Corresponding data storage area; a read control unit connected to the first number of basic read ports in the local data storage buffer, for parallel reading from the data storage area of the local data storage buffer to be read by the target hardware acceleration engine Data of the target data type. The access device can flexibly configure the local data storage buffer according to the amount of data of different data types, and can solve the problem that the local data storage buffer in the prior art only supports read and write operations of fixed-length data.

Description of drawings

FIG. 1 is a schematic structural diagram of an access device according to an embodiment of the present invention;

2 is a schematic structural diagram of a write control unit provided by an embodiment of the present invention;

3 is a schematic structural diagram of a reading control unit according to an embodiment of the present invention;

4 is a schematic flowchart of an access method provided by an embodiment of the present invention;

FIG. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all of the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the protection of the present application.

The access device provided by the embodiment of the present invention may be installed on a server or a terminal. The terminal may be User Equipment (UE) such as a mobile phone, a smart phone, a notebook computer, a digital broadcast receiver, a personal digital assistant (PDA), a tablet computer (PAD), a handheld device, a vehicle-mounted device, and a wearable device. , computing equipment or other processing equipment connected to the wireless modem, mobile station (Mobile station, MS), mobile terminal (Mobile Terminal), etc.

As shown in FIG. 1, the access device may include a local data storage buffer, a write control unit and a read control unit.

The local data storage buffer is a data storage area of different data types composed of a first number K of basic storage modules with uniform address codes. Wherein, each basic storage module has a basic read port and a basic write port; the first quantity K may be determined according to the amount of data required for calculation of the target hardware acceleration engine, or may be preset by a technician, the present invention The embodiment is not limited here.

The local data storage buffer is used to store data of at least one data type corresponding to the target hardware acceleration engine, wherein the data of at least one data type includes the data required for the calculation of the target hardware acceleration engine and the data obtained by the calculation of the target hardware acceleration engine. data;

It can be understood that the above-mentioned target hardware acceleration engine is only a hardware module that needs to access the local data storage buffer to access data, and the local data storage buffer can also store other hardware modules that need to perform data access operations. The embodiments of the invention are not limited herein.

Optionally, if the target hardware acceleration engine is a convolutional neural network engine, at least one data type includes a weight type, an eigenvalue type, a convolution part and a type, that is, the data of at least one data type is a weight type. Value coefficients, image or eigenvalues, convolution part and data. Among them, the weight coefficients and images can be obtained from the memory, the convolution part and data can be calculated by the target hardware acceleration engine each time, and the target hardware acceleration engine accumulates the convolution parts and data obtained by each calculation to obtain the eigenvalues .

In order to improve the flexibility of configuring the local data storage buffer, you can configure the corresponding data storage area according to the data required by the current target hardware acceleration engine calculation and the data type of the calculated data. The number of basic storage modules occupied by data storage areas of different data types may be different or the same.

The write control unit is connected to the first number K of basic write ports in the local data storage buffer, and the read control unit is connected to the first number K of basic read ports in the local data storage buffer.

The writing control unit is configured to write data of at least one data type corresponding to the target hardware acceleration engine into the corresponding data storage area in parallel.

The read control unit is configured to read data of the target data type to be read by the target hardware acceleration engine in parallel from the data storage area of the local data storage buffer.

Optionally, the write control unit is further configured to determine the number of write ports of the write control unit according to the number of types of at least one data type.

The read control unit is further configured to determine the number of read ports of the read control unit according to the number of types of target data types to be read by the target hardware acceleration engine.

If the number of types of at least one data type is the second number N, the number of write ports of the write control unit is the second number N. As shown in FIG. 2 , when the number of write ports of the write control unit is the second number N, the write ports of the second number N of the write control unit are connected to the target hardware acceleration engine, and the write ports of the second number N of the write control unit are connected to the target hardware acceleration engine. The output ports of the number K are connected with the basic write ports of the first number K in a one-to-one correspondence.

Wherein, the writing control unit may include a second number N of multiplexers and a first number K of multiplexers; each multiplexer includes an input port and a first number K of output ports, and each multiplexer includes an input port and a first number K of output ports. The way selector includes a second number N of input ports and one output port.

The write ports of the second quantity N of the write control unit are connected in one-to-one correspondence with the input ends of the second quantity N of demultiplexers; the outputs of the first quantity K of each demultiplexer are connected with the first quantity K The input terminals of the multiplexers are connected in one-to-one correspondence; the output terminals of each multiplexer are connected with the basic write port to be written in the corresponding data storage area.

The multiplexer is used for determining the target basic storage area to be written according to the inter-block address of the basic storage module corresponding to the data type to be written.

The multiplexer is used for determining the basic write port of the basic storage block corresponding to the target basic storage area according to the target basic storage area to be written.

If the number of types of the corresponding data types to be read by the target hardware acceleration engine is the third number M, the number of read ports of the read control unit is the third number M. As shown in FIG. 3 , when the number of read ports of the read control unit is a third number M, the read ports of the third number M of the read control unit are connected to the target hardware acceleration engine, and the first number of read ports of the read control unit M are connected to the target hardware acceleration engine. The input ports of the number K are connected with the basic read ports of the first number K in a one-to-one correspondence.

Wherein, the reading control unit may include a third number M of multiplexers and a first number K of multiplexers; each multiplexer includes a first number K of input ports and one output port, each multiplexer The splitter includes one input port and a third number M of output ports.

The read ports of the third quantity M of the read control unit are connected with the input ends of the multiplexers of the third quantity M in a one-to-one correspondence; the input ends of the first quantity K in each multiplexer are respectively connected with the first quantity The outputs of the demultiplexers of K are connected in one-to-one correspondence; the input end of each demultiplexer is connected with the basic read port to be read in the corresponding data storage area.

The multiplexer is used to determine the target basic storage area to be read according to the basic read port of the basic storage block corresponding to the data type to be read.

The demultiplexer is used to determine the basic read port of the basic storage block corresponding to the target basic storage area according to the target basic storage area to be read.

It should be noted that the specific configuration of each multiplexer and each multiplexer is completed independently.

Further, the convolutional neural network engine generally has multiple network layers that need to implement convolution calculations. Due to the size of the neural network node and the different weight coefficients of each neural network node, each network layer calculates different data types. The size of the storage area required by the data is also different, that is, the number of basic storage modules is different.

It can be seen that the local data storage buffer can dynamically allocate the size of the mechanism, that is, it can dynamically and timely change the size of the functional area of the local data buffer according to the changes in the requirements of different convolutional network layers, so as to meet the needs of different types of data for different storage areas. Size requirements, to achieve the flexibility of the local data storage buffer configuration.

In an example, taking the target hardware acceleration engine as a convolutional neural network engine as an example, for the write port of the write control unit, if the type of data to be written is: weight coefficient, image or feature value, convolution part and data, the write control unit has three write ports, namely N=3, corresponding to three types of data write. For the read control unit read port, if the data type to be read is: weight coefficient, image or feature value, convolution part and data and final volume accumulation and sum, the read control unit has four read ports , that is, M=4, corresponding to four types of data read.

The local data storage buffer requires a total of 108KB, the size of the basic memory module is 4KB (generally, the size of a basic block RAM of an FPGA is 4KB, which is convenient to use the block RAM resources of the FPGA for verification), and the data bit width is 16bit, so that the first The value of the quantity K is 27. The address bit width in the basic storage module is 11 bits, and the address bit width between the basic storage modules is 5 bits (2^5=32>27), that is, the configuration address is from 00000b to 11010b.

The write control unit includes 3 multiplexers and 27 3-to-1 multiplexers, wherein each multiplexer is a multiplexer from 1 to 27 channels, that is, each multiplexer includes 27 multiplexers output port.

The read control unit includes 4 multiplexers and 27 multiplexers of 1 to 4 channels, wherein each multiplexer is a 27-to-1 multiplexer.

Further, taking the data required for the two-layer network convolution calculation as an example, the description is as follows:

For the configuration of the local data storage buffer in the first network layer:

Configuration of data types in the local data store buffer:

The space requirements for each data type entered are as follows:

The input weight coefficients are allocated to the basic storage module space of Block1 (hereinafter referred to as B1) and the basic storage module space of B2;

The input image data is allocated to B3 to B15 basic storage module space;

The input convolution part and data are allocated to B16 to B27 basic memory module space;

The weight coefficient output port can only read the input weight coefficient of the first layer network layer from the B1 and B2 basic storage module spaces;

The image or eigenvalue output port can only read the input image data of the first layer network layer from the B3 to B15 basic storage module space;

The convolution part and data output port can only read the convolution part and data generated during the convolution calculation of the first layer network layer from the basic storage module space of B16 to B27 for the subsequent convolution calculation of the first layer network layer. need;

The final volume accumulation and sum output port can only read the final convolution calculation sum formed after all the convolution calculations of the first layer network layer are completed from the B16 to B27 basic storage module space. This port reads the B16 to B27 basic memory module space in parallel with the convolution part and the data output port in time-sharing.

Configuration of input ports in the local data store buffer:

The corresponding input ports are the weight coefficient input port, the image data input port, and the convolution part and the data input port.

(1) The input range of the inter-block address of the weight coefficient input port is: 00000b to 00001b, and then the 11-bit intra-block address is: 000h-7ffh, that is, the address of the weight coefficient port input to the local data storage buffer is 0000h to 0fffh; among them, the input port of the first 3-to-1 multiplexer and the second 3-to-1 multiplexer should be connected to the output port of the demultiplexer that outputs the weight coefficient, and the configuration parameter is 00b;

(2) The input range of the inter-block address of the image data input port is: 00010b to 01110b, which are combined with the 11-bit intra-block address, that is, the address of the image port input to the local data storage buffer is 1000h to 77ffh; The input ports of the three 3-to-1 multiplexers to the fifteenth 3-to-1 multiplexer should be connected to the output ports of the multiplexer that outputs image data, and the configuration parameter is 01b;

(3) The input range of the inter-block address of the convolution part and the data input port is 01111b to 11010b, which is combined with the 11-bit intra-block address, that is, the address of the convolution part and the port input to the local data storage buffer is 7800h to D7ffh ; Among them, the input port of the 16th 3-to-1 multiplexer to the 27th 3-to-1 multiplexer should be connected to the output port of the output convolution part and the configuration parameter is 10b;

Configuration of output ports in the local data store buffer:

The corresponding output ports are the weight coefficient output port, the image or feature value output port, the convolution part and the data output port, and the final volume accumulation sum output port.

(1) The input range of the inter-block address of the weight coefficient output port is 00000b to 00001b, and then add the 11-bit intra-block address 000h-7ffh, which together means that the weight coefficient output port is from the local data storage buffer address 0000h to The storage space of 0fffh reads the weight coefficient; among them, the output ports of the first 1 to 4-way demultiplexer and the second 1 to 4-way demultiplexer are respectively selected from 27 of the output weight coefficients. The first and second output ports of the channel selector are connected, and the configuration parameter is 00b;

(2) The input range of the inter-block address of the image or eigenvalue output port is 00010b to 01110b, which is combined with the 11-bit intra-block address, that is, the image or eigenvalue output port is stored from the local data storage buffer address from 1000h to 77ffh. Pay space to read image data; among them, the output ports of the third 1 to 4-way demultiplexer to the 15th 1 to 4-way demultiplexer are respectively connected with the output ports of the 27-to-1-way multiplexer for outputting image data. The 3rd to 15th output ports are connected, and the configuration parameter is 01b;

(3) The input range of the inter-block address of the convolution part and the data output port is 01111b to 11010b, which is combined with the 11-bit intra-block address, that is, the address of the convolution part and the data output port from the local data storage buffer is 7800h to The storage space of D7ffh reads the convolution part and data; among them, the output ports of the 16th 1 to 4-way demultiplexer to the 27th 1 to 4-way demultiplexer are respectively selected from the 27 selections of the output convolution part and the sum. The 16th to 27th output ports of the 1-way multiplexer are connected, and the configuration parameter is 10b;

(4) The input range of the inter-block address of the final volume accumulation and output port is 01111b to 11010b, which is combined with the 11-bit intra-block address, that is, the final volume accumulation and output port is from the address of the local data storage buffer from 7800h to 7800h. The storage space of D7ffh reads the final convolution and data; due to time-multiplexing with the convolution part and the data output port, the 16th 1 to 4-way demultiplexer at this time to the 27th 1 to 4-way multiplexer The output ports of the distributor are reconfigured to be connected to the 16th to 27th output ports of the 27-to-1-way multiplexer outputting the accumulated sum of the final volume respectively, and the configuration parameter is 11b.

For the configuration of the local data storage buffers in the Layer 2 network layer:

Configuration of data types in the local data store buffer:

The space requirements for each data type entered are as follows:

The input weight coefficients are allocated to the basic storage module space of B1, B2, B3 and B4;

The input image data is allocated to B5 to B16 basic storage module space;

The input convolution part and data are allocated to B17 to B27 basic memory module space;

The weight coefficient output port can only read the input weight coefficient of the second layer network layer from the basic storage module space of B1, B2, B3 and B4;

The image or feature value output port can only read the input feature data of the second layer network layer from the B3 to B16 basic storage module space;

The convolution part and data output port can only read the convolution part and data generated during the convolution calculation of the second layer network layer from the basic storage module space of B17 to B27 for the subsequent convolution calculation of the second layer network layer. need;

The final volume accumulation sum output port can only read the final convolution calculation sum formed after all the convolution calculations of the second layer network layer are completed from the B17 to B27 basic storage module space. This port reads B17 to B27 basic memory module space in parallel with the convolution part and the data output port in time-sharing.

Configuration of input ports in the local data store buffer:

The corresponding input ports are the weight coefficient input port, the image data input port, the convolution part and the data input port.

(1) The input range of the inter-block address of the weight coefficient input port is 00000b to 00011b, and then add the 11-bit intra-block address 000h-7ffh, which together means that the address of the weight coefficient port input to the local data storage buffer is 0000h to 1fffh; among them, the input ports of the first to fourth 3-to-1 multiplexers are respectively connected with the output ports of the multiplexer that outputs the weight coefficient, and the configuration parameter is 00b;

(2) The input range of the inter-block address of the image data input port is 00100b to 01111b, which is combined with the 11-bit intra-block address, that is, the address of the image port input to the local data storage buffer is 2000h to 7fffh; among them, the fifth The input port to the 16th 3-to-1 multiplexer should be connected to the output port of the multiplexer that outputs image data, and the configuration parameter is 01b;

(3) The input range of the inter-block address of the convolution part and the data input port is 10000b to 11010b, which is combined with the 11-bit intra-block address, that is, the address of the convolution part and the port input to the local data storage buffer is 8000h to D7ffh ; Among them, the input ports of the 17th to 27th 3-to-1 multiplexers should be connected with the output convolution part and the output port of the data, and the configuration parameter is 10b;

Configuration of output ports in the local data store buffer:

The corresponding output ports are the weight coefficient output port, the image or feature value output port, the convolution part and the data output port, and the final volume accumulation sum output port.

(1) The input range of the inter-block address of the weight coefficient output port is 00000b to 00011b, and then add the 11-bit intra-block address 000h-7ffh, which together means that the weight coefficient output port is from the local data storage buffer address 0000h to The storage space of 1fffh reads the weight coefficient; among them, the output ports of the 1st to 4th 1 to 4-way demultiplexers are respectively connected with the 1st output port of the 27-to-1-way multiplexer that outputs the weight coefficient. connected to the fourth output port, the configuration parameter is 00b;

(2) The input range of the inter-block address of the image or eigenvalue output port is 00100b to 01111b, which is combined with the 11-bit intra-block address, that is, the image or eigenvalue output port is stored from the local data storage buffer address 2000h to 7fffh. Pay space to read image data; among them, the output ports of the 5th to 16th 1 to 4-way multiplexers are respectively connected with the 5th to 16th of the 27-to-1-way multiplexers that output image data. The output ports are connected, and the configuration parameter is 01b;

(3) The input range of the inter-block address of the convolution part and the data output port is 10000b to 11010b, which is combined with the 11-bit intra-block address, that is, the address of the convolution part and the data output port from the local data storage buffer is 8000h to The storage space of D7ffh reads the convolution part and data; among them, the output ports of the 17th to 27th 1 to 4-way demultiplexers are respectively connected to the 27-to-1-way multiplexing of the output convolution part and data The 17th to 27th output ports of the device are connected, and the configuration parameter is 10b;

(4) The input range of the inter-block address of the final volume accumulation and output port is 10000b to 11010b, which is combined with the 11-bit intra-block address, that is, the final volume accumulation and output port is from the address of the local data storage buffer from 8000h to 8000h. The storage space of D7ffh reads the final convolution and data; due to time-multiplexing with the convolution part and the data output port, the output ports of the 17th to 27th 1 to 4-way demultiplexers are reconfigured as They are respectively connected with the 17th to 27th output ports of the 27-to-1-way multiplexer that outputs the final volume accumulation and summation, and the configuration parameter is 11b.

It can be seen that the access device provided by the embodiment of the present invention can flexibly configure the local data storage buffer according to the amount of data of different data types, and can solve the problem that the local data storage buffer in the prior art can only perform read and write operations on data that supports a fixed length. limitation issues.

Corresponding to the above access device, an embodiment of the present invention further provides an access method. As shown in FIG. 4 , the execution subject of the method is an access device, and the method includes:

S410. Write data of at least one data type corresponding to the target hardware acceleration engine into the data storage area of the local data storage buffer in parallel.

S420. Store data of at least one data type corresponding to the target hardware acceleration engine.

The local data storage buffer is a data storage area of different data types composed of a first number K of basic storage modules with uniform address codes, and is used to store data of at least one data type calculated by the target hardware acceleration engine.

The first quantity K is determined according to the amount of data required for calculation by the target hardware acceleration engine, and each basic storage module has a basic read port and a basic write port.

S430: Read data of the target data type to be read by the target hardware acceleration engine in parallel from the data storage area of the local data storage buffer.

In an optional implementation, according to the type number of at least one data type corresponding to the target hardware acceleration engine, determine the number of write ports written to the control unit in the access device;

And, the number of read ports of the read control unit in the access device is determined according to the number of types of target data types to be read by the target hardware acceleration engine.

The functions of each functional unit of the access method provided by the above embodiments of the present invention can be implemented by the above units. Therefore, the specific working process and beneficial effects of each method step in the access method provided by the embodiments of the present invention are as follows: This will not be repeated.

An embodiment of the present invention further provides an electronic device, as shown in FIG. 5 , including a processor 510 , a communication interface 520 , a memory 530 and a communication bus 540 , wherein the processor 510 , the communication interface 520 , and the memory 530 pass through the communication bus 540 complete communication with each other.

a memory 530 for storing computer programs;

When the processor 510 is used to execute the program stored in the memory 530, the following steps are implemented:

Write data of at least one data type corresponding to the target hardware acceleration engine into the data storage area of the local data storage buffer in the access device in parallel;

storing data of at least one data type corresponding to the target hardware acceleration engine;

Alternatively, data of the target data type to be read by the target hardware acceleration engine is read in parallel from the data storage area of the local data storage buffer.

In an optional implementation, according to the type number of at least one data type corresponding to the target hardware acceleration engine, determine the number of write ports in the access device to which the control unit is written;

And, the number of read ports of the read control unit in the access device is determined according to the number of types of target data types to be read by the target hardware acceleration engine.

The above-mentioned communication bus may be a peripheral component interconnect standard (Peripheral Component Interconnect, PCI) bus or an Extended Industry Standard Architecture (Extended Industry Standard Architecture, EISA) bus or the like. The communication bus can be divided into an address bus, a data bus, a control bus, and the like. For ease of presentation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

The communication interface is used for communication between the above electronic device and other devices.

The memory may include random access memory (Random Access Memory, RAM), and may also include non-volatile memory (Non-Volatile Memory, NVM), such as at least one disk storage. Optionally, the memory may also be at least one storage device located away from the aforementioned processor.

The above-mentioned processor may be a general-purpose processor, including a central processing unit (Central Processing Unit, CPU), a network processor (Network Processor, NP), etc.; may also be a digital signal processor (Digital Signal Processing, DSP), an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), Field-Programmable Gate Array (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

Since the implementation manners and beneficial effects of each component of the electronic device in the above-mentioned embodiment to solve the problem can be achieved by referring to the steps in the embodiment shown in FIG. 4 , the specific working process and beneficial effects of the electronic device provided by the embodiment of the present invention The effect will not be repeated here.

In yet another embodiment provided by the present invention, a computer-readable storage medium is also provided, where instructions are stored in the computer-readable storage medium, when the computer-readable storage medium is run on a computer, the computer is made to execute any one of the above-mentioned embodiments. the described access method.

In yet another embodiment provided by the present invention, there is also provided a computer program product containing instructions, which, when run on a computer, cause the computer to execute the access method described in any one of the foregoing embodiments.

Those skilled in the art should understand that the embodiments in the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the embodiments of the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein .

The embodiments of the present application are described with reference to the flowcharts and/or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It will be understood that each flow and/or block in the flowcharts and/or block diagrams, and combinations of flows and/or blocks in the flowcharts and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to the processor of a general purpose computer, special purpose computer, embedded processor or other programmable data processing device to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing device produce Means for implementing the functions specified in one or more of the flowcharts and/or one or more blocks of the block diagrams.

These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory result in an article of manufacture comprising instruction means, the instructions An apparatus implements the functions specified in a flow or flows of the flowcharts and/or a block or blocks of the block diagrams.

These computer program instructions can also be loaded on a computer or other programmable data processing device to cause a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process such that The instructions provide steps for implementing the functions specified in one or more of the flowcharts and/or one or more blocks of the block diagrams.

Although the preferred embodiments of the embodiments of the present application have been described, additional changes and modifications to these embodiments may be made by those skilled in the art once the basic inventive concepts are known. Therefore, the appended claims are intended to be construed to include the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present application.

Obviously, those skilled in the art can make various changes and modifications to the embodiments in the embodiments of the present application without departing from the spirit and scope of the embodiments in the embodiments of the present application. In this way, if these modifications and variations of the embodiments in the embodiments of the present application fall within the scope of the claims in the embodiments of the present application and their equivalents, the embodiments of the present application are also intended to include these modifications and variations.

Claims (7)

1. An access device, characterized in that the device comprises:

the local data storage buffer area is used for storing data of at least one data type corresponding to the target hardware acceleration engine; the local data storage buffer area is a data storage area with different data types and composed of a first number of basic storage modules with uniform address coding; wherein the first number is determined according to the amount of data required for the target hardware acceleration engine calculation, each basic storage module having a basic read port and a basic write port; if the target hardware acceleration engine is a convolutional neural network engine, the at least one data type comprises at least one of a weight type, a characteristic value type and a convolutional part and type;

the write-in control unit is connected with the first number of basic write-in ports in the local data storage buffer area and is used for writing data of at least one data type to be written, which corresponds to the target hardware acceleration engine, into a corresponding data storage area of the local data storage buffer area in parallel;

the reading control unit is connected with the first number of basic reading ports in the local data storage buffer area and is used for reading the data of the target data type to be read by the target hardware acceleration engine from the data storage area of the local data storage buffer area in parallel;

the write control unit is further configured to determine the number of write ports of the write control unit according to the type number of the at least one data type;

the reading control unit is further configured to determine the number of reading ports of the reading control unit according to the number of types of target data to be read by the target hardware acceleration engine.

2. The apparatus of claim 1,

if the number of the write-in ports of the write-in control unit is a second number, the second number of the write-in ports of the write-in control unit are connected with the target hardware acceleration engine, and the first number of the output ports of the write-in control unit are connected with the first number of the basic write-in ports in a one-to-one correspondence manner;

if the number of the read ports of the read control unit is a third number, the third number of the read ports of the read control unit are connected with the target hardware acceleration engine, and the first number of the input ports of the read control unit are connected with the first number of the basic read ports in a one-to-one correspondence manner.

3. The apparatus of claim 2,

the write control unit includes the second number of demultiplexers and the first number of multiplexers; each demultiplexer comprises an input port and said first number of output ports, and each multiplexer comprises said second number of input ports and an output port;

the second number of write-in ports of the write-in control unit are connected with the input ends of the second number of multi-way distributors in a one-to-one correspondence manner;

the first number of output ends of each demultiplexer are correspondingly connected with the input ends of the first number of multiplexers one by one;

and the output end of each multiplexer is connected with a basic writing port to be written in the corresponding data storage area.

4. The apparatus of claim 1 or 2,

the read control unit includes a third number of multiplexers and the first number of demultiplexers; each multiplexer including a first number of input ports and an output port, each demultiplexer including an input port and a third number of output ports;

the reading ports of the third number of the reading control units are correspondingly connected with the input ends of the multiplexers of the third number one by one;

the input ends of the first number in each multiplexer are respectively connected with the output ends of the first number of the multi-way distributors in a one-to-one correspondence manner;

the input end of each demultiplexer is connected with a basic reading port to be read in the corresponding data storage area.

5. An accessing method applied to the accessing apparatus of claim 1, the method comprising:

writing data of at least one data type corresponding to a target hardware acceleration engine into a data storage area of a local data storage buffer area in the access equipment in parallel;

storing data of at least one data type corresponding to the target hardware acceleration engine;

or, reading the data of the target data type to be read by the target hardware acceleration engine in parallel from the data storage area of the local data storage buffer;

determining the number of write-in ports of a write-in control unit in the access equipment according to the type number of at least one data type corresponding to the target hardware acceleration engine;

determining the number of reading ports of a reading control unit in the access device according to the type number of the target data types to be read by the target hardware acceleration engine;

wherein, if the target hardware acceleration engine is a convolutional neural network engine, the at least one data type includes at least one of a weight type, a feature value type, and a convolutional part sum type.

6. An electronic device, characterized in that the electronic device comprises a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory are communicated with each other through the communication bus;

a memory for storing a computer program;

a processor for implementing the method steps of claim 5 when executing a program stored in the memory.

7. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the method steps of claim 5.

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