CN111142653B

CN111142653B - PCIe device low-power-consumption control method and device and electronic device

Info

Publication number: CN111142653B
Application number: CN201911367152.4A
Authority: CN
Inventors: 刘海亮
Original assignee: Jiangsu Xinsheng Intelligent Technology Co ltd
Current assignee: Jiangsu Xinsheng Intelligent Technology Co ltd
Priority date: 2019-12-26
Filing date: 2019-12-26
Publication date: 2022-03-22
Anticipated expiration: 2039-12-26
Also published as: CN111142653A

Abstract

The invention provides a low-power-consumption control method and device for PCIe (peripheral component interface express) equipment and electronic equipment, wherein the PCIe equipment is controlled to enter an L1 sub-state through two interrupt signals, low-power-consumption setting of a power domain except for CPU/PCIe (central processing unit/peripheral component interface express) is mainly processed when a first interrupt is received, PCIe low-power-consumption setting and a handshake mechanism are mainly processed when a second interrupt is received, and two interrupt operations respectively play their roles and jointly form a complete L1 sub-state to enter a low-power-consumption flow; and simultaneously setting two interrupt signals to control PCIe to exit from an L1 sub-state, and mainly finishing software recovery operation, an SoC power-on process and a reset process when the first interrupt is carried out. The setting of the PCIe UPF related registers and the PCIe pmu state machine handshake are mainly completed in the second interrupt. The two L1 sub-state exit interrupt signals are used, so that the CPU exception caused by the fact that the PCIe LTSSM state machine returns to the L0 state to receive an operation command from the host side after software is not recovered or the SoC is not performed to the end of executing the power-on process is avoided.

Description

PCIe device low-power-consumption control method and device and electronic device

Technical Field

The application relates to the technical field of PCIe (peripheral component interface express), in particular to a low-power-consumption control method and device for PCIe (peripheral component interface express) equipment and electronic equipment.

Background

The existing high-speed serial computer expansion bus standard (PCIe) energy saving technology includes two energy saving modes, power management and link active state power management, a PCIe link power management state L is defined, and according to a PCIe3.1a protocol, the L1 state includes L1.0, L1.1, and L1.2 sub-states, where the L1.0 sub-state is a conventional L1 state, and L1.1 or L1.2 enters after the L1.0 state meets conditions, how the L1 sub-state is linked with SoC low power consumption in engineering practice of the SoC chip low power consumption L1 sub-state integrated with PCIe, and a problem of short operation time faced by software to backup and restore when entering and exiting the L1 sub-state is encountered.

Disclosure of Invention

In view of the above, the present invention provides a method and an apparatus for controlling low power consumption of a PCIe device, and an electronic device, so as to solve the above problems.

When a PCIe hardware circuit sends a first interrupt signal entering an L1 sub-state, performing backup operation of software, powering off a power domain where a non-CPU and PCIe are located, and closing a corresponding gated clock; when the PCIe hardware circuit sends a second entering interrupt signal of the L1 sub-state, the setting before the PCIe power-off is completed, the power supply of the power domain where the CPU is located and the corresponding gated clock are turned off, and finally the save _ state _ ack signal is set to 1, so that the PCIe equipment terminal enters the L1 sub-state.

When the PCIe hardware circuit sends a first quit interrupt signal, performing software recovery operation, a SoC power-on process and a reset process, and controlling the PCIe hardware circuit to set the ack _ en _ vmain signal to be 0 so that the PCIe LTSSM state machine stays in an L1 state; and when the PCIe hardware circuit sends a second exit interrupt signal, performing PCIe UPF register configuration, and performing PCIe pmu state machine handshake to exit the L1 substate.

Further, the PCIe device low power consumption control method further includes: when a PCIe hardware circuit sends out a first entering interrupt signal of an L1 sub-state, triggering a low-power-consumption entering event corresponding to the SoC, so that the SoC enters a low-power-consumption state.

Further, the method further comprises: when a PCIe hardware circuit sends out a first exit interrupt signal of an L1 sub-state, triggering a low-power-consumption exit event corresponding to the SoC, so that the SoC exits from the low-power-consumption state.

Further, the L1 substate first enter interrupt signal is the rising edge of the clk _ req _ in _ n signal; the L1 substate second entry interrupt signal is the rising edge of the pm _ save _ state _ req signal.

Further, the L1 sub-state first exit interrupt signal is the falling edge of the clk _ req _ in _ n signal; the L1 substate second exit interrupt signal is the rising edge of the pm _ restore _ state _ req signal.

In a second aspect, the present invention further provides a PCIe device low-power-consumption control apparatus, where the apparatus includes a processing module, where the processing module is configured to perform a software backup operation when a PCIe hardware circuit sends an L1 sub-state first entry interrupt signal, power off a power domain where a non-CPU and PCIe are located, and close a corresponding gated clock;

the processing module is further configured to complete setting of the PCIe before power off when the PCIe hardware circuit sends the second entry interrupt signal in the L1 sub-state, turn off a power domain power source where the CPU is located and a corresponding gated clock, and finally set the save _ state _ ack signal to 1, so that the PCIe device terminal enters the L1 sub-state.

Further, the processing module is further configured to perform a software recovery operation, a SoC power-on process and a reset process when the PCIe hardware circuit issues the first exit interrupt signal, and control the PCIe hardware circuit to set the ack _ en _ vmain signal to 0 so that the PCIe LTSSM state machine stays in the L1 state;

and when the PCIe hardware circuit sends a second exit interrupt signal, performing PCIe UPF register configuration, and performing PCIe pmu state machine handshake to exit the L1 substate.

Further, the processing module is further configured to trigger a low power consumption entry event corresponding to the SoC when a PCIe hardware circuit sends a first entry interrupt signal in the L1 sub-state, so that the SoC enters the low power consumption state;

the processing module is further configured to trigger a low power consumption exit event corresponding to the SoC when a PCIe hardware circuit sends a first exit interrupt signal of the L1 sub-state, so that the SoC exits the low power consumption state.

In a third aspect, the present invention also provides an electronic device comprising a processor for executing computer-readable program instructions to implement the steps of the PCIe device low power consumption control method as described above.

Compared with the prior art, the technical scheme provided by the application has the following beneficial effects:

according to the low-power-consumption control method and device for the PCIe equipment and the electronic equipment, the PCIe equipment is controlled to enter the L1 sub-state after two interrupt signals are respectively passed, and after the CPU receives the first interrupt signal, the CPU mainly processes the low-power-consumption setting, the power failure process and the software backup operation of other power domains except the CPU/PCIe, so that the operation consumes long time; after receiving the second interrupt signal, the CPU mainly processes PCIe low power consumption setting and handshake mechanism, and the operation consumes very short time due to the low power consumption setting of the CPU power domain. The two interrupt CPUs operate respectively and form a complete L1 sub-state together to enter a low-power-consumption flow of PCIe, SoC and software.

In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.

Fig. 1 shows a schematic diagram of an electronic device provided by the present invention.

Fig. 2 is a flowchart illustrating a PCIe device low power consumption control method provided in the present invention.

Fig. 3 shows the L1 substate entry timing diagram provided by the present invention.

FIG. 4 is a flow chart illustrating another method for controlling low power consumption of a PCIe device according to the present invention.

FIG. 5 illustrates the L1 substate exit timing diagram provided by the present invention.

FIG. 6 is a flow chart illustrating another method for controlling low power consumption of a PCIe device according to the present invention.

Fig. 7 is a schematic diagram illustrating functional modules of a low power consumption control apparatus for PCIe devices provided in the present invention.

Icon: 200-PCIe device low power consumption control means; 210-processing module.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

In the description of the present invention, it should also be noted that relational terms such as first and second, and the like, may be used solely herein to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

Some embodiments of the invention are described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.

Fig. 1 is a block diagram of an electronic Device according to a preferred embodiment of the present invention, which may be a System on chip (SoC) based on a PCIe bus, and the electronic Device includes a processor and a PCIe Device, where the processor is connected to the PCIe Device to complete reading, writing, and controlling registers of the PCIe Device. The processor may be a general-purpose processor including a Central Processing Unit (CPU), a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components. The various methods, steps and logic blocks disclosed in the embodiments of the present invention may be implemented or performed. In the following description, a processor is exemplified as a CPU unless otherwise noted.

Further, the PCIe Device includes PCIe control registers (PCIe controller) and PCIe physical layer registers (PCIe PHY), such as reset registers, accelerated emulation registers, and the like. Power management and Link active State Power management defines the PCIe power management state L, as shown in Table 1.

TABLE 1

According to the pci 3.1a protocol, the L1 state includes L1.0, L1.1, and L1.2 sub-states, where the L1.0 sub-state is the conventional L1 state, and L1.1 or L1.2 enters the L1.0 state after the conditions are satisfied, and in the engineering practice of the SoC chip low power consumption L1 sub-state integrated with PCIe, the problem of how the L1 sub-state is linked with SoC low power consumption is encountered, and the problem of short operation time faced when software backups and restores after entering and exiting the L1 sub-state is encountered.

In order to improve the above problem, based on the electronic device provided in fig. 1, the present embodiment provides a method for controlling PCIe device with low power consumption. Referring to fig. 2, fig. 2 shows a schematic flow chart of a PCIe device low power consumption control method provided in this embodiment, where the PCIe device low power consumption control method provided in this embodiment includes:

step 110: when the PCIe hardware circuit sends out a first entering interrupt signal of an L1 sub-state, the backup operation of software is carried out, the power domain where the non-CPU and the PCIe are located is powered off, and the corresponding gated clock is closed.

The PCIe hardware circuit provides two L1 sub-state entering interrupt signals to the CPU, and the CPU controls the PCIe device to enter the L1 sub-state according to the two L1 sub-state entering interrupt signals.

When the PCIe hardware circuit sends out a first entering interrupt signal of an L1 sub-state, the backup operation of software is carried out, the power domain where the non-CPU and the PCIe are located is powered off, and the corresponding gated clock is closed. A power domain may be understood as a range of power supply voltages and turning off a power domain may be understood as stopping power.

Step 120: when the PCIe hardware circuit sends out the second entering interrupt signal of the L1 sub-state, the setting before the PCIe power-off is completed, the power supply of the power domain where the CPU is located and the corresponding gated clock are closed, and finally the save _ state _ ack signal is set to 1, so that the PCIe equipment terminal enters the L1 sub-state.

When the PCIe hardware circuit sends out the second entering interrupt signal of the L1 sub-state, the setting before the PCIe power-off is completed, the power supply of the power domain where the CPU is located and the corresponding gated clock are closed, and finally the save _ state _ ack signal is set to 1, so that the PCIe equipment terminal enters the L1 sub-state.

The save _ state _ ack signal is set to 1, completing the handshake of the PCIe pmu state machine with the CPU. When Save _ state _ ack is high, the pmu state machine jumps to ISO _ L1 state, initiates isolation, and after completion of the isolation start, the state machine jumps to a reset state, placing the PCIe core in a reset state to enable the circuit to remain in the reset state after power up. After the reset state is completed, the PCIe pmu state machine jumps to a PD _ L1 state, a pm _ en _ vmain signal is set to be at a high level to request completion of power down of low power consumption, an ack _ en _ vmain signal is a power control signal of a PCIe core, the signal is at a high level and indicates that the power supply is in an on-position state at present, and the signal is at a low level and indicates that the power supply is turned off. In this state, the ack _ en _ vmain signal is from the output of the power switch, whose input is pm _ en _ vmain.

According to the low-power-consumption control method for the PCIe device, the CPU controls the PCIe device to enter the low-power-consumption L1 sub-state according to the two interrupt signals by setting the two interrupt signals, and after receiving the first interrupt signal entering the L1 sub-state, the CPU mainly processes the low-power-consumption setting, the power-down flow and the software backup operation of other power domains except the CPU/PCIe, wherein the operation consumes longer time; and after receiving the second interrupt, the CPU mainly processes PCIe low-power-consumption setting and handshaking mechanism and the low-power-consumption setting of the CPU power domain, and the operation consumes very short time. The two interrupt CPUs operate respectively to form a complete L1 sub-state entry and PCIe, SoC and software low-power consumption flow.

In one possible implementation, referring to fig. 3, the L1 sub-state first entry interrupt signal is the rising edge of the clk _ req _ in _ n signal, which is the CLKREQ # input to the PCIe module, and the L1 sub-state second entry interrupt signal is the rising edge of the pm _ save _ state _ req.

It should be noted that, after the PCIe hardware circuit issues the L1 sub-state second entry interrupt signal, the CPU configures the selection control signal ack _ en _ vmain _ sel of ack _ en _ vmain high level to switch the source of ack _ en _ vmain to the CPU configured register signal ack _ en _ vmain _ sys, but when pmu jumps to the PD _ L1 state, the hardware circuit switches the source of ack _ en _ vmain to the output signal ack _ en _ vmain _ psw of the power switch, so that ack _ en _ vmain is derived from the ack _ en _ vmain _ psw signal when the L1 sub-state enters, and the ack _ en _ vmain is derived from the CPU configured register signal ack _ en _ vmain _ sys when the L1 sub-state exits.

The circuit logic configured is as follows:

ack_en_vmain＝((pmu_state＝＝Save_State)||(pmu_state＝＝ISO_L1)||(pmu_stat e＝＝Reset_L1)||(pmu_state＝＝PD_L1))？ack_en_vmain_psw:(ack_en_vmain_selack_en_vmain_sys:ack_en_vmain_psw)。

after entering the L1 substate, the PCIe device resumes operation and exits the L1 substate, similarly to entering the L1 substate, the control is also performed by two interrupt signals. Referring to fig. 4, on the basis of fig. 2, the PCIe device low power consumption control method further includes:

step 130: when the PCIe hardware circuit sends out a first exit interrupt signal of an L1 sub-state, a software recovery operation, a SoC power-on process and a reset process are carried out, and the PCIe hardware circuit is controlled to set the ack _ en _ vmain signal to be 0 so that the PCIe LTSSM state machine stays in an L1 state.

Referring to fig. 5, fig. 5 shows a schematic diagram of the interrupt signal when the L1 substate exits. In one possible implementation, the L1 substate first exit interrupt signal is: clk _ req _ in _ n _ neg _ intr. After the CPU receives a first exit interrupt clk _ req _ in _ n _ neg _ intr sent by a PCIe hardware circuit, the CPU completes the recovery operation of software, the power-on process of the SoC and the reset release process, after the operations are completed, the CPU reads a pm _ en _ vmain register, if the value of the register is 1, the CPU sets an ack _ en _ vmain _ sel register to be 0, so that an ack _ en _ vmain signal comes from an output ack _ en _ vmain _ psw signal of a power switch, and the power-on of a PCIe core is completed. After the PCIe core is electrified, the PCIe pmu state machine finishes the jump of the internal state, and the internal state is sequentially in a PU _ L1- > Release _ Reset- > Active- > Restore state.

Step 140: when the PCIe hardware circuit sends out a second exit interrupt signal of the L1 sub-state, PCIe UPF register configuration is carried out, and PCIe pmu state machine handshake is carried out to exit the L1 sub-state.

In the Restore state, the PCIe hardware circuit issues a second exit interrupt signal in the L1 sub-state, and in a possible implementation, the second exit interrupt signal in the L1 sub-state is: pm _ restore _ state _ req _ intr, and after receiving the state, the CPU completes the configuration of the PCIe UPF register, sets the handshake signal restore _ state _ ack of the pmu state machine to 1, and completes the handshake with the pmu state machine. PCIe pmu completes the restore state after receiving the handshake signal, and switches the state to the Active state. The LTSSM continues to exit the L1 substate until it returns to the L0 state.

The two interrupt signals in the PCIe L1 sub-state exit flow are responsible for their respective functions, and the CPU mainly completes the software recovery operation, SoC power-on flow and reset flow in the first interrupt clk _ req _ n _ neg _ intr. During this interrupt, the PCIe hardware circuitry causes the PCIe LTSSM state machine to stay in the L1 state by setting the ack _ en _ vmain signal to 0 to give the CPU sufficient time to interrupt processing. And after receiving the second interrupt, the CPU mainly completes the setting of the PCIe UPF related register and the handshaking with the PCIe pmu state machine. The two L1 sub-states are used for exiting the interrupt, so that the condition that the PCIe LTSSM state machine returns to the L0 state to receive an operation command from the host side to cause a CPU exception if the software is not recovered or the SoC is not performed to finish the power-on process is avoided.

In one possible implementation, in order to combine the low power control of the PCIe device with the low power control of the SoC, referring to fig. 6 on the basis of fig. 4, after step 110, the PCIe device low power control method further includes:

step 111: when the PCIe hardware circuit sends out a first entering interrupt signal of the L1 sub-state, a low-power-consumption entering event corresponding to the SoC is triggered, so that the SoC enters the low-power-consumption state.

Similarly, when the PCIe device exits the L1 substate, the SoC also synchronously exits the low power consumption state. After step 130, the PCIe device low power consumption control method further includes:

step 131: when the PCIe hardware circuit sends out a first exit interrupt signal of the L1 sub-state, a low-power-consumption exit event corresponding to the SoC is triggered, so that the SoC exits from the low-power-consumption state.

The scheme provided by the embodiment selects the clk _ req _ in _ n signal as a low-power consumption linkage trigger signal of the SoC and the PCIe L1 substates, according to the PCIe protocol, when the signal is switched from a low level to a high level, PCIe is triggered to enter the L1 substate, the SoC triggers a low-power consumption entry event corresponding to the SoC by using a rising edge of the signal, and the low-power consumption entry event and the PCIe L1 substate are executed in parallel to enter the low-power consumption state corresponding to the SoC. When the clk _ req _ in _ n signal is switched from low level to high level, the PCIe is triggered to exit the L1 sub-state, the SoC triggers a low-power-consumption exit event corresponding to the SoC by using the falling edge of the signal, and the low-power-consumption state corresponding to the SoC is exited by the SoC in parallel with the PCIe L1 sub-state.

In order to execute the corresponding steps in the above embodiments and various possible implementations, an implementation manner of the low power consumption control apparatus for PCIe devices is given below. Referring to fig. 7, fig. 7 is a functional block diagram of a PCIe device low power consumption control apparatus 200 according to an embodiment of the present application, it should be noted that the basic principle and the generated technical effect of the PCIe device low power consumption control apparatus 200 provided in the present embodiment are the same as those of the foregoing embodiment, and for brief description, no mention is made in this embodiment, and reference may be made to corresponding contents in the foregoing embodiment.

The PCIe device low power consumption control apparatus 200 apparatus includes a processing module 210.

The processing module 210 is configured to perform a backup operation of software when the PCIe hardware circuit sends the first entry interrupt signal in the L1 sub-state, power off the power domain where the non-CPU and the PCIe are located, and close the corresponding gated clock.

Optionally, in a possible implementation manner, the processing module 210 may be configured to execute step 110 in each of the above-mentioned figures to achieve a corresponding technical effect.

The processing module 210 is further configured to trigger a low power consumption entry event corresponding to the SoC when the PCIe hardware circuit issues the L1 sub-state first entry interrupt signal, so that the SoC enters the low power consumption state.

Optionally, in a possible implementation manner, the processing module 210 may be configured to execute step 111 in each of the above-mentioned figures to achieve a corresponding technical effect.

The processing module 210 is further configured to complete setting of PCIe before power off when the PCIe hardware circuit sends the second entry interrupt signal in the L1 sub-state, turn off the power domain power source where the CPU is located and the corresponding gated clock, and finally set the save _ state _ ack signal to 1, so that the PCIe device terminal enters the L1 sub-state.

Optionally, in a possible implementation manner, the processing module 210 may be configured to execute step 120 in each of the above-mentioned figures to achieve a corresponding technical effect.

The processing module is further configured to perform a software recovery operation, a SoC power-on process and a reset process when the PCIe hardware circuit issues the first exit interrupt signal, and control the PCIe hardware circuit to set the ack _ en _ vmain signal to 0 so that the PCIe LTSSM state machine stays in the L1 state.

Optionally, in a possible implementation manner, the processing module 210 may be configured to execute the step 130 in each of the above-mentioned figures to achieve a corresponding technical effect.

The processing module 210 is further configured to trigger a low power consumption exit event corresponding to the SoC when the PCIe hardware circuit issues the L1 sub-state first exit interrupt signal, so that the SoC exits the low power consumption state.

Optionally, in a possible implementation manner, the processing module 210 may be configured to execute step 131 in each of the above-mentioned figures to achieve a corresponding technical effect.

The processing module 210 is further configured to perform PCIe UPF phase registration configuration and PCIe pmu state machine handshake to exit the L1 substate when the PCIe hardware circuit issues the second exit interrupt signal.

Optionally, in a possible implementation manner, the processing module 210 may be configured to execute step 140 in each of the above-mentioned figures to achieve a corresponding technical effect.

In summary, the present invention provides a method, an apparatus, and an electronic device for controlling low power consumption of PCIe devices, where the PCIe devices are controlled to enter an L1 sub-state after two interrupt signals are respectively passed, and a CPU mainly processes low power consumption settings, power failure procedures, and software backup operations of power domains other than CPU/PCIe after receiving a first interrupt signal, and this operation consumes a long time; after receiving the second interrupt signal, the CPU mainly processes PCIe low power consumption setting and handshake mechanism, and the operation consumes very short time due to the low power consumption setting of the CPU power domain. The two interrupt CPUs respectively perform their own functions and jointly form a complete L1 sub-state to enter a low-power-consumption flow of PCIe, SoC and software; and simultaneously setting two interrupt signals to control PCIe to exit from an L1 sub-state, and mainly finishing software recovery operation, an SoC power-on process and a reset process in the first interrupt clk _ req _ n _ neg _ intr. During this interrupt, the PCIe hardware circuitry causes the PCIe LTSSM state machine to stay in the L1 state by setting the ack _ en _ vmain signal to 0 to give the CPU sufficient time to interrupt processing. And after receiving the second interrupt, the CPU mainly completes the setting of the PCIe UPF related register and the handshaking with the PCIe pmu state machine. The two L1 sub-state exit interrupt signals are used, so that the condition that the software is not recovered or the SoC is not recovered to finish executing the power-on process, namely the PCIe LTSSM state machine returns to the L0 state to receive the operation command from the host side to cause the exception of the CPU is avoided.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In addition, the functional modules in the embodiments of the present invention may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A low-power-consumption control method for PCIe equipment is characterized in that the low-power-consumption control method for the PCIe equipment is applied to a PCIe equipment terminal, and comprises the following steps:

when the PCIe hardware circuit sends out a first entering interrupt signal of an L1 sub-state, the backup operation of software is carried out, the power domain where the non-CPU and the PCIe are located is powered off, and the corresponding gated clock is closed;

when the PCIe hardware circuit sends a second entering interrupt signal of the L1 sub-state, setting the PCIe before powering off is completed, a power supply domain power supply where the CPU is located and a corresponding gated clock are turned off, and finally setting a save _ state _ ack signal to be 1 so that the PCIe equipment terminal enters the L1 sub-state;

the PCIe device low power consumption control method further comprises the following steps:

when the PCIe hardware circuit sends out a first exit interrupt signal of an L1 sub-state, performing software recovery operation, a SoC power-on process and a reset process, and controlling the PCIe hardware circuit to set the ack _ en _ vmain signal to be 0 so that the PCIe LTSSM state machine stays in an L1 state;

and when the PCIe hardware circuit sends a second exit interrupt signal of the L1 sub-state, PCIe UPF register configuration is carried out, and PCIe pmu state machine handshake is carried out to exit the L1 sub-state.

2. The PCIe device low power control method of claim 1, further comprising:

when a PCIe hardware circuit sends out a first entering interrupt signal of an L1 sub-state, a low-power-consumption entering event corresponding to the SoC is triggered, so that the SoC enters a low-power-consumption state.

3. The PCIe device low power consumption control method of claim 1, the method further comprising:

when a PCIe hardware circuit sends out a first exit interrupt signal of an L1 sub-state, triggering a low-power-consumption exit event corresponding to the SoC, so that the SoC exits from the low-power-consumption state.

4. The PCIe device low power consumption control method of claim 1,

the L1 substate first enter interrupt signal is the rising edge of the clk _ req _ in _ n signal;

the L1 substate second entry interrupt signal is the rising edge of the pm _ save _ state _ req signal.

5. The PCIe device low power consumption control method of claim 1,

the L1 substate first exit interrupt signal is the falling edge of the clk _ req _ in _ n signal;

the L1 substate second exit interrupt signal is the rising edge of the pm _ restore _ state _ req signal.

6. The PCIe equipment low-power consumption control device is characterized by being applied to a PCIe equipment terminal and comprising a processing module, wherein the processing module is used for carrying out software backup operation when a PCIe hardware circuit sends a first interrupt signal entering an L1 sub-state, powering off a power domain where a non-CPU and PCIe are located and closing a corresponding gated clock;

the processing module is further configured to:

when the PCIe hardware circuit sends out a first quit interrupt signal, performing software recovery operation, an SoC power-on process and a reset process, and controlling the PCIe hardware circuit to set the ack _ en _ vmain signal to be 0 so that the PCIe LTSSM state machine stays in an L1 state;

7. The PCIe device low power consumption control apparatus of claim 6, wherein the processing module is further configured to:

when a PCIe hardware circuit sends a first entering interrupt signal of an L1 sub-state, triggering a low-power-consumption entering event corresponding to the SoC so as to enable the SoC to enter a low-power-consumption state;

8. An electronic device, comprising a processor configured to execute computer-readable program instructions to implement the steps of the method according to any one of claims 1 to 6.