CN1111375A - information processing system - Google Patents

Abstract

A system designed to wake up from a removable external storage device information necessary to resume and resume a task, regardless of whether the system has been hibernated or not. The history information indicates that the system performs the hibernation operation as long as the external storage device has been installed in one of its predetermined areas before. The wake-up system checks history information for wake-up operations performed. The external storage device stores system configuration information including when the task is suspended. Wake up the system and compare the stored system configuration information with the configuration information of the system itself. Refuse to restore information from the external storage device to main memory when the two are inconsistent.

Description

The present invention relates to information processing systems operating with low power consumption, and more particularly to portable information processing systems such as notebook computers.

As a result of the latest technology, small and lightweight portable computers have become commonplace. When such portable computers are used outdoors, they are powered by batteries. However, batteries mounted on portable computers are limited to small batteries. Thus, each time the battery is charged, the personal computer can only be operated for a short period of time. Therefore, in many portable computers, various devices are provided to reduce power consumption.

Suspend/resume is one of these device functions. When the suspend/resume function is activated, if no I/O device activity is detected for a period of time, in response to this, the computer enters suspend mode. In suspend mode, all tasks are suspended and main memory stores the data needed to resume tasks later. In suspend mode, the main memory and video memory (VRAM) are powered on, while the CPU, etc. is powered off. However, a portable computer has a disadvantage that the suspend mode lasts for a long period of time, only suspend/resume function is supported, and the power of the battery is also consumed, which will cause the contents of the memory and VRAM to be lost.

Therefore, portable computers such as the LTE Lite/25 manufactured by Compaq Corporation supported by hibernation mode have been put on the market (Compaq and LTE are both registered trademarks of Compaq Computer Corporation). When hibernation is initiated, the computer enters a low-battery state. In addition, when the suspend mode lasts for a period of time, after all the data required for future recovery tasks are stored on the hard disk, the computer enters the hibernation state. In hibernation mode, the entire system, including memory and VRAM, is powered down. When the user powers up the system later, the data stored in the hard disk is restored in the memory and VRAM, and the suspended tasks are automatically resumed. A series of operations starting with power-on is also called wake-up.

In recent years, removable hard disk devices have begun to be installed on computers. However, there has not been seen such a technology that enables carrying a task-freeze removable hard disk device and enabling such a device to be installed in a different system where the task is unfreezed (recovered).

Therefore, the present invention aims at recovering information necessary to restart a task from a removable external storage device, regardless of whether the system to be awakened is a hibernated system or not.

Furthermore, the present invention aims to provide an information processing system having a detachable external storage device capable of determining whether the system performs an operation from hibernation to wakeup or an operation from hibernation to normal boot when the system is powered on.

Furthermore, the present invention aims to provide an information processing system having a detachable external storage device capable of determining whether the system configuration is appropriate and whether the environment can wake up.

PUPA 5-6233 discloses a technique in which the part holding information necessary for restoration constitutes a detachable cartridge structure holding the content as it is from the main body of the computer. In this technique, however, the main memory itself is set to be nonvolatile and detachable from the main body of the personal computer. The present invention is intended to store information in an external storage device that can be detached from a volatile main memory, and to restore such information. The conventional techniques described above therefore cannot provide a means for solving the problems that the present invention intends to solve.

In order to achieve the above object, the first aspect of the present invention provides an information processing system, the system includes a CPU, a volatile main memory and a detachable non-volatile external storage device, and the system supports a wake-up function, using the A task whose function has been suspended in the system is resumed, the external storage device has been installed in the system in response to powering on the system, the task stores necessary information in the external storage device, characterized in that :

storing history information indicating that a hibernation operation has been performed in the system in a predetermined area of the external storage device, the external storage device having previously been installed in the system; and

The system includes means for checking the historical information and performing a wake-up operation.

Furthermore, a second aspect of the present invention includes an information processing system including a CPU, a volatile main memory, and a detachable nonvolatile external storage device, and the system supports a wake-up function by which the The task suspended in the system is resumed, and the system power is turned on in response, the external storage device has been installed in the system, and the task stores necessary information in the external storage device, which is characterized in that:

The external storage device stores control information including system configuration information when the task is suspended,

The system includes:

(a) means for comparing system configuration information stored in said external storage device with system configuration information of the system itself,

(b) means for restoring information necessary for restoring the task from the external storage device into the main memory according to the consistency of the configuration information, and

(c) means for refusing to restore information from the external storage device to the main memory based on the inconsistency of the configuration information.

Fig. 1 represents and adopts the hardware structure in an embodiment of the information system of the present invention;

Fig. 2 shows hardware structure;

Figure 3 shows the structure of the hibernation file;

Fig. 4 represents the drive that can be accessed by OS file system or PM code;

Figure 5 represents a flow chart for performing the POST steps;

Figure 6 shows a flowchart of the operation of the file preparation utility;

Figure 7 shows a flow chart of a general hibernation/wake sequence;

Fig. 8 represents the flowchart of the operation process of storing hibernation file;

Fig. 9 represents the file allocation table on the hard disk;

Figure 10 represents the transformed file allocation information;

Fig. 11 represents the flowchart of the recovery operation process from the hibernation file;

Fig. 12 represents the flow chart of the operation process related to the hibernation icon display;

Figure 13 shows a screen including hibernation icons;

Figure 14 shows a screen including hibernation icons;

Fig. 15 is a flow chart showing the detailed procedure of the hibernation icon display operation;

Figure 16 shows the hardware associated with FDD change line emulation;

Figure 17 shows a flowchart of the steps involved in the first method of FDD change line simulation;

Fig. 18 shows the trap of I/O access in the first method;

Figure 19 represents the relationship between codes and traps in the BIOS/driver;

Fig. 20 represents the hardware realizing the second method of FDD change line emulation;

Fig. 21 represents the flow diagram that is included in the second method; And

Fig. 22 shows waveform diagrams related to the second method.

[Example]

A. The configuration of the whole system

FIG. 1 schematically shows the main hardware components of a notebook computer (hereinafter simply referred to as a system) to which the present invention is applied. Reference numeral 10 denotes a main CPU. In this embodiment, it is an Intel 80486SL including a memory controller. The CPU 10 communicates with the main memory 12 and the PM memory 13 through the memory path 11 . The main memory 12 is loaded with BIOS, drivers, OS and application programs. On the other hand, the PM memory 13 stores a PM code (PMC) for performing power management including the hibernation mode and its operation data. The PM memory is further divided into an area for storing PMC and an area for storing work data. At POR (power on/reset), the PMC is loaded from ROM.

Different chips can be allocated for PM memory and main memory, for example, SRAM is used as PM memory and DRAM is used as main memory. In this embodiment, the architecture of 80486SL is used to allocate a specific area of each DRAM chip to the main memory 12 and the PM memory 13 .

The PMC can access the main memory 12 and the PM memory 13 . On the other hand, the OS and drivers cannot access the PM memory 13 . The memory controller can switch the communication of the CPU 10 so that the CPU 10 communicates with either the main memory 12 or the PM memory 13 .

CPU10 communicates with trap logic circuit 16, DMAC (direct memory access controller) 18, PIC (programmable interrupt controller) 20, PIT (programmable interval timer) 22, serial port 24, parallel through address/data bus 14 and trap logic circuit 16, Port 26, RTC (real time clock) 28, CMOS30 and ROM32 are connected.

The output of trap logic circuit 16 is connected to a specific terminal of CPU 10 via system interrupt line 52 . Trap logic circuit 16 continuously monitors bus 14 . The system interrupt line 52 becomes asserted when the trap logic circuit 16 detects a signal that an access is made to the address set in the stored register. Trap logic circuit 16 also activates system interrupt line 52 when signal 50 input to the external input becomes active.

Present embodiment adopts Intel I/O chipset 82360SL, and it comprises trap logic circuit 16, DMAC18, PIC20, PIT22, serial port 24, RTC28 and CMOS30. In 82360SL, the system interrupt is called SMI (System Management Interrupt). When an SMI occurs, the memory controller causes communication between the CPU 10 and the PM memory 13 to start execution of the PMC as an SMI processing program. The SMI handler (PMC) detects the cause of the SMI and, depending on the cause, branches to a handling routine.

Serial port 24 is connected to one or more I/O drivers through serial port buffer 34 . These I/O drivers can automatically set either of two numbers (eg, 3F8(H) or 2F8(H)) for the base address of the I/O space assigned to port 24.

RTC28 and CMOS30 are installed on one chip. A backup battery 36 can power the chip even if the system is powered off. Backup battery 36 may be a coin battery.

In addition to storing the BIOS code, the ROM 32 also stores the PMC. POST (Power On Self Test), which runs at the system's POR, loads the PMC from ROM 32 into PM memory 13 .

CPU 10 receives signals from mouse 42 and keyboard 44 via KMC (keyboard/mouse controller) 38 . In this embodiment, a matrix of processors (sub-CPUs 40) monitoring keyboard 44 is also included as part of the power management function. Sub CPU 40 monitors a matrix of keyboard 44 , LED 46 and main battery 48 . Signal line 50 becomes active when sub-CPU 40 detects that a predetermined condition has occurred, such as pressing an active key, LED turning off, or main battery 48 being in a low voltage state. The sub CPU 40 is connected to the bus 14 via the bus 41 . Then the sub-CPUs exchange instructions and data (including hibernation) related to power management with the CPU 10 via the bus 41 .

The sub-CPU 40 outputs a signal to the power control register 54 instructing each component to be powered off, or the entire system to be powered off. Details will be given below in conjunction with FIG. 2 .

The CPU 10 is connected to the VGA chip 56 through the bus 14 . The VGA chip is a display controller which controls the LCD panel 62 through the LCDC (LCD Controller) 60 and thus displays information according to the contents of the VRAM 58 . Otherwise a display unit including a CRT 66 and a DAC (Digital to Analog Converter) 64 can be installed as an option for the system. In this case, the VGA chip 56 controls the display of information on the CRT 66 .

The system installs a hard disk device 68 and FDC (floppy disk controller) 70/FDD (floppy disk drive) 72 as external storage devices. The hard disk device 68 includes a hard disk drive and a hard disk installed in the hard disk drive in concept itself. The hard disk device 68 will hereinafter be referred to as a hard file. When the system enters hibernation mode, a file (hibernation file) for storing data is prepared on the hard file. According to the present invention, hibernation/wakeup can be supported even when the hard file is detachable.

In addition to the above-mentioned hardware components, there are actually many I/Fs (interfaces) in the system (for example, a bus transceiver is set between the hard file 68 and the bus 14). These components are already known to those of ordinary skill in the art. For simplicity, they are not drawn in the drawings.

The power on/off mechanism will be described below with reference to FIG. 2 . The output of the main battery is input to a FET switch 76 which enables the entire system to be powered down at once. The output of FET switch 76 goes directly to main memory and VRAM. On the other hand, the output of the FET switch 76 is sent to the input terminal of the LCD backlight power supply through the FET switch 80, to the integrated modem directly connected to the serial port 24 through the FET switch 81, and to the main CPU 10 through the switch 78. and other peripherals.

Each FET switch is electrically connected to a bit cell corresponding to the power control register 54 . Thus, the value set by the sub-CPU 40 to the register 54 controls the energization/de-energization of the FET switches 76 , 78 , 80 and 81 . When the system enters the hibernation mode, when receiving a PMC command, the sub-CPU 40 sets a corresponding bit to a value that powers off the FET switch 76, thereby powering off the entire system including the main memory and VRAM. When the system enters the suspend mode, when receiving the PMC command, the sub-CPU 40 enables the FET switch 76 to be energized, and sets a value that causes the FET switches 78, 80, 81 in the register 54 to be de-energized, thereby making all but the main memory and the VRAM Other systems are powered off.

The reset terminal of the power control register 54 is electrically connected to the power switch 82 of the system. A signal generated when the user applies power to the system then resets a value in register 54, thereby turning on all of the FET switches and energizing the entire system.

B. Structure of the hibernate file

As shown in Figure 3, this embodiment ensures that on the hard disk there is a storage unit for block A for control information, a storage unit for block B for file allocation information, and a storage unit for block C for working data in the PM memory The memory cells for block D are provided for the contents of the VRAM, and the memory cells for block E are provided for the contents of the main memory. As will be explained in more detail below, control information is required as soon as the system is powered on. Such information includes system configuration information and the respective start addresses of blocks B to D. Working data is additional data required for hibernation. Job data includes hardware content information (described later) and various control flags. An example of a control flag is a flag whose value can be changed by the user to select whether the system beeps when the system enters or exists in hibernation mode.

Blocks A through E may be a series of regions physically connected into an integrated circuit. However, block A needs to reside in at least one fixed location on the disk. Thus in this embodiment, only block A is arranged at the beginning of the CE parity track (it is reserved, but cannot be accessed by the user), which is defined in the innermost part of the hard disk. The gist of it is that the above locations are fixed and control information can be stored from a sector in the middle of the CE parity track.

As will be seen in detail in Section C, blocks B to E are locations used by the OS file system to secure a location for a file in the user partition of the hard disk at the same size as the user file. The file name is reserved, PM-HIBER.BIN in this embodiment. Blocks B to E may extend in the length direction. When the hibernation file actually stores data, the start addresses of blocks C to E can be determined. The sectors that make up blocks B to E typically reside physically on the hard disk in a distributed fashion. Sector connection information is recorded in the file allocation information area (FAT when DOS is used as OS) on the hard disk in the form of a table. As will be seen in detail in Section D, the PMC swaps the sector connection information making up the PM-HIBER.BIN into unique allocation information and stores the transformed information in block B.

C. Hibernation file generation

The process of generating the hibernation file according to the present invention will be described in detail below with reference to FIGS. 4 to 6 .

According to the present invention, an OS file system is used to provide a hibernation file in a user partition of a block device such as a hard file or the like. For this, prepare a file preparation utility such as an executable program (.EXE file) that will generate the hibernation file. However, multiple block devices are available and the PMC does not need to access all of them directly (not through drivers/BIOS managed by OS system files). This is because the PMC cannot directly access certain devices, and the reason is that the I/F (hardware) that drives the PMC, which looks logically the same from the utility, is not suitable.

In the embodiment shown in Figure 4, the OS file system can access removable disks (CD-ROM, SSF (Solid State File), SRAM card, etc.), network drives (remote files), RAM disks, compressed partitions, Hard File 1, Partitions 1, 2 and 3 of Hard File 2 as IDE drives. To the utility, these are the same logical drive.

These drivers are described below. Originally, network drives were drives for different systems connected by a network. PMC cannot access network drivers to send hibernation/wake data. The RAM disk is an imaginary drive, and has no I/F that the PMC can access (since the RAM disk is volatile in nature, the disk cannot hold data during hibernation mode).

A compressed partition is a drive used to store compressed data. In a compressed partition, a corresponding drive with a specific algorithm compresses data to be written into the drive, or expands data to be read. The PMC cannot employ compression/expansion algorithms because drives corresponding to compressed partitions can operate under the management of the OS file system. Therefore, compressed partitions are not suitable for preparing hibernation files. In addition, when only the IDE drive is prepared as the I/F of the hard file, the PMC can directly access it, and the PMC cannot access the hard file1.

Partition 4 prepared on hard file 2 is a hidden partition. Also, partition 5 is a drive whose format is not supported on the OS file system. When DOS is used in the OS file system, HPFS of OS/2 does not support (OS/2 is a registered trademark of IBM Corporation). Even when the PMC can access these partitions 4 and 5, the OS file system cannot access these partitions 4 and 5.

Some of these drives become unsuitable for preparing hibernation files when the utility refers to the OS file system. In the embodiment shown in FIG. 4, a network driver is such a driver. However, it is unclear whether the PMC can access other drives for utilities.

Conceivably, the drive letter assigned to the drive could make the utility specify a hibernation file to prepare the file for. However, the drive letter is different depending on the level of the installed driver that supports the drive. Also, when multiple bootable drives reside, the utility cannot specify the drive in a fixed manner by utilizing a drive letter. PMC, on the other hand, does not know the interrelationship between drives and drive letters.

The present invention determines a drive, which can be accessed by the PMC, and which is suitable for the utility to prepare the hibernation file in the following manner.

Firstly, the system operation at the time of POR will be described in detail with reference to FIG. 5 . When the power switch is turned on or when the system is reset, the POST program is executed (step 502). When the process of POST loading the PMC into the PM memory is completed, the PMC is temporarily executed. Each drive that the PMC can access looks for a hibernation file (PM-HIBER.BIN) (step 503). After the search is completed, POST is executed again, so as to enter the normal boot process or wake up the boot process (steps 504, 505).

The steps performed by the hibernation file preparation utility are described below with reference to FIG. 6 . When the user inputs a command or gives an instruction to start the hibernation file through the graphical user interface, the file preparation utility starts to be executed (step 601 ). In step 602, the utility calls the BIOS to know the required size of the hibernation file (the overall size of the main memory, the PM memory and the working data area of the VRAM).

In step 603 , it is inquired whether there is a hibernation file (PM-HIBER.BIN) whose size is larger than the required PMC searched in step 503 . If such a file exists, the file can be used to store data. So the process after this ends.

When the PMC answers in the negative, the following steps are performed for each drive, the utility can access drives other than those described below which are not suitable as network drives according to the OS file system.

It is first determined whether the size of the selected drive is larger than the above-mentioned required size (step 606). If the result of the judgment is answered in the affirmative, a small file is temporarily prepared with the OS file system, and its file name is stored in the drive, thereby notifying the PMC of such a fact that the file is temporarily ready (step 607). The name of the temporary file can be PM-HIBER.BIN or other names. The size of the file to prepare it can be 0.

The PMC that has been notified of the above fact immediately intends to read the temporary file. When the PMC task is complete, it sends an affirmative reply to the utility. When the drive receives an affirmative reply from the PMC, the PMC can access the drive. The scale of PMC is also large enough. Therefore, the utility erases the initial temporary files. After that, by using the OS file system, a hibernation file having the same size as the above-mentioned necessary file and having a file name of PM-HIBER.BIN is prepared on the drive (step 609 ).

When the PMC does not issue an acknowledgment, the temporary file is erased (step 611). Steps 606, 607 and 608 are then repeated for the selected files. When the size of the driver is not enough, steps 607, 608 and 611 are skipped. When the PMC does not give an affirmative reply to any drive, the system notifies the user by beeping or displaying a message that the hibernation file cannot be executed with this device. After this, the sequence of operations is complete (step 614).

In the above-described embodiment, a drive suitable for preparing a file is detected, and a hibernation file is immediately prepared. As a modification to this embodiment, after checking whether the preparation of the hibernation file is suitable for all logical drives, a drive suitable for the user may be proposed. In this case, the drive suitable for the user is prompted, so that a hibernation file is proposed to be prepared on the drive selected by the user.

D. Overview of the save/restore sequence

Referring to Figure 7, an overview of the store/restore sequence for entering or remaining in hibernation mode is illustrated. When the main CPU executes the PMC of the PM memory, steps 701 to 708 shown in the figure, and steps 713 to 719 are performed.

First, the store/restore sequence is explained. As shown in FIG. 1, trap logic circuit 16 transmits a system interrupt signal to main CPU 10 when sub-CPU 40 detects a predetermined condition (such as pressing a working key or the system is in a low voltage state). This causes the executing task to be suspended and the control of the system operation is transferred from the OS file system or an application to the PMC (trap handler).

When the PMC analyzes the cause of the system interruption and determines that an external phenomenon added through the signal line 50 is responsible for the system interruption, the PMC transfers to the storage operation execution routine to enter the hibernation mode.

The PMC is started to detect the activity existing in the I/O device (step 701). When there is activity (for example, performing DMA), after a predetermined period of time (for example, 10 seconds), the detection activity is repeated again until the I/O activity is detected.

When no I/O activity is detected, the PMC saves hardware context information in PM memory. Next, the system saves the entire working data including hardware context information from the PMC memory to the hard disk device (step 702 ). Typical examples of hardware context information include register values of each chip such as CPU, register values of interrupt controller, DMA controller, and video controller, and counting values of timers.

In step 703, the PMC transmits the original data of the VRAM to the hard disk device. At this time, in order to store on the hard disk, the data of VRAM can be compressed. In step 704, an icon image indicating that the hibernated store operation is active is written into the VRAM for display on the display device.

While displaying an icon, the PMC transfers the raw data of the main memory to the hard disk device (step 705). At this time, the data in the main memory may be compressed for storage on the hard disk. In step 706, the system configuration information from CMOS is stored in the hard disk device. Typical examples of system configuration information include the type and number of optional devices connected to the system main body (portable computer), and the size of the main memory.

In step 707, the PMC sets a hibernation flag indicating that the above sequence has passed. The hibernation flag is 2-byte information which is a piece of control information stored in area A shown in the figure.

Finally, the PMC sends a command to the sub-CPU to power off the system (step 708).

Next, the recovery sequence will be described. When the system is powered on, the main CPU executes a POST (Power On Self Test) program stored in ROM (step 712). POST performs the following operations.

(i) When the system configuration is modified, such as increasing the memory during power-off, or changing the number of FDDs, POST detects this modification, and rewrites the system configuration information of CMOS directly or indirectly by using the establishment program.

(ii) As an operation related to FDD, the system detects whether the FDD/FDC is operating normally, and the system needs to import from FDD before waking up from hibernation, remove FDD, and install another unit or device.

(iii) PMC is transferred from ROM to PM memory.

(iv) Detection of hibernation markers.

When the system needs to be imported from the FDD, or when the system is not powered off through steps 701 to 708, the system enters a normal boot process, and the control right of the entire system operation does not need to be transferred to the PMC. When a hardware failure is detected, such as FDD/FDC not operating normally, the system stops.

In this way, according to the present invention, the personal history information of whether the system has gone through the hibernation sequence is stored in the hard disk device, rather than stored in other components of the system. At POR, POST uses personal history information in the hard disk device to determine whether hibernation wakeup or normal boot is valid. Therefore, the detachable hard disk device starts tasks with other devices whose function is the same as that of the device performing the storage operation to be restored. In other words, the frozen system environment can be moved freely.

When it is confirmed that there is a hibernation flag, that is, a hibernation context, the control right of the entire system is transferred from POST to PMC. The PMC starts to compare the hard disk with the system configuration information of the CMOS (step 713 ). When it is detected that the configuration information of the hard disk is inconsistent with that of the system, the fault information will be displayed with icons, etc., prompting the system to allow the user to choose any of the following operations: invalidate the current hibernation flag, or restore the system settings by powering off the system before modification (step 714). In addition, when prompted to restore the system configuration, the system configuration before modification is proposed so as to guide the user.

When the hard disk device is detachable, there is a great possibility that the environment (first environment) when data is stored on the hard disk is different from the environment (second environment) when the system is in a wake-up state. For example, in some cases, the size of the main memory in the second environment may be smaller. Furthermore, although the running application requires a specific value for the base address of the I/O device, the specific value is not available in the second environment. Additional executing applications access the floppy disk in the first environment. There are no floppy disks in the second environment. In this case, various disadvantages arise: wakeup itself becomes impossible, resumed tasks destroy data, etc. Therefore, it is very important to detect the function of the system configuration.

When it is confirmed that the wake-up function is allowed by the environment, the PMC writes the icon image representing that the PMC is recovering (waking up) into the VRAM, so that it is displayed on the display device (step 715). While displaying the hibernation icon, the PMC restores the original data of the main memory from the hard disk (step 716 ). Then erase the icon and recover the original data of VRAM from the hard disk (step 717). At step 718, working data including hardware context information is restored in PM memory. The hardware is then restored to addresses such as I/O devices and CPU registers. In the last step, the PMC is set up for FDD change line emulation (step 719). After the above sequence is completed, control of the system is transferred to the OS file system and applications. Resume execution of tasks after the breakpoint.

E. Details of save/restore operations for hibernation files

The operation of saving data in the hibernation file (PM-HIBER.BIN) (steps 702 , 703 , 704 , 705 , 706 and 707 ) will be described in more detail below in conjunction with FIG. 8 .

Initially, the PMC stores hardware context information in the PMC area of the memory (step 801 ). Therefore, if the hardware context information is stored at the beginning, the hardware context information can be modified to facilitate subsequent storage operations.

In step 802, the basic boot record (MBR) of the hard disk is accessed to obtain partition information (start address and size of each partition) of the hard disk device. MBR is a parity track, which is located in the outermost area of the hard disk. Pared tracks are reserved but cannot be accessed by users.

In step 803, the PMC obtains an address of the route directory of each partition except the partition smaller than the predetermined value. Since the address calculation method is known, it will not be repeated here. For example, when a DOS is used as the OS file system, the BIOS parameter block (BPB) located in front of the partition is used to calculate an address of the route directory of the partition.

In step 804, sequentially access the directory of the calculated address, and search for the file name (PM-HIBER.BIN). If no PM-HIBER.BIN is detected in any directory, the hibernation file is not executed and the user is notified of this by beeping or displaying a message that does not execute.

When PM-HIBER.BIN is detected, the file allocation table is tracked (step 805). Figure 9 shows an example in which given DOS as the OS file system, the file allocation given when four sectors are defined as a cluster is divided into one sector block starting from cluster 100 until the end of cluster 149, starting from cluster 500 One sector block until the end of cluster 549, and one sector block from the beginning of cluster 300 until the end of cluster 349. The entry of PM-HIBER.BIN in the route directory indicates the number 100 of the first cluster. As already known, a FAT (File Allocation Table) is formed in each cluster according to a ratio of 1:1. FAT describes a continuous cluster number (ie FAT number) or a specific number representing the end of the file. At step 805, the PMC accesses the hard disk one or more times to track the list of 200FAT.

The file allocation information thus obtained is transformed in step 806 into unique allocation information suitable for storage/retrieval. Fig. 10 shows the information formed after the above transformation. The example shown corresponds to FIG. 9 . The PMC produces 8-byte long data in which the previous sector address (relative address from the sector address actually preceding the address) and length (sector number) are recorded. The allocation information after conversion is temporarily buffered in the working data area of the PMC memory.

Referring to Fig. 8 again, in step 807, the PMC detects whether the file size of PM-HIBER.BIN can support the overall size of the working data of the currently installed VRAM, main memory and PM memory. For example, when the main memory increases after the hibernation file is generated, not all data can be saved. However, when the file size is not enough, the system refuses to perform the hibernation operation. This fact is notified by beeping, etc.

When the file is large enough, the allocation information from the PMC is stored in the hibernation file using the allocation information generated in step 806 itself (step 808). Then the working data, the content of the VRAM and the content of the main memory are respectively stored in the hibernation file (steps 809 to 811). When transferring data to the hard disk, it refers to the file allocation information in the PMC memory.

Finally, control information is prepared so that it is stored in the control information area (area A in FIG. 3) (steps 812 and 813). The control information items respectively include the start addresses of blocks B, C and D shown in FIG. 3 , the current system configuration information in CMOS and the hibernation flag. The system configuration information includes the basic I/O address of the device, the size of the main memory, and the device configuration (type and quantity of the device). The base I/O address indicates which of the two base addresses is, for example, 3F8(H) or 2F8(H) according to each device connected to the serial port.

Referring next to FIG. 11 , the data recovery operation (steps 713 , 716 and 717 ) will be described in more detail below from the hibernation file (PM-HIBER.BIN).

At first, the PMC accesses the control information area of the CE parity track, and reads the control information there, so as to know the position of the hibernation file on the hard disk (step 1101). Since the addresses in the control information area are fixed, the addresses can be accessed immediately. In step 1102, the system configuration information included in the control information is compared with the system configuration information in the CMOS of the wakeup mechanism.

In step 1103, the PMC uses the start address included in the control information to access the file allocation information block on the hard disk, so as to restore the file allocation information in the PMC. The PMC initially restores the contents of main memory with the file allocation information, and then restores the contents of VRAM (steps 1104 and 1105). In these steps, the start addresses of the main memory block and the VRAM block included in the control information area are used. Finally, the control information on the hard disk is invalidated, thereby completing the recovery operation (step 1106). Since the hibernation flag is also inactive, the system can be booted with power-on operation through the normal process as long as the system does not enter hibernation mode.

In addition, although the description is omitted, there is actually a step of displaying a hibernation icon between steps 810 and 811 in FIG. 8 and between steps 1103 and 1104 in FIG. 11 . Attention should be paid to the fact that between steps 1105 and 1106 in FIG. 11 there is also a step of restoring the H/W context information.

The sector position information constituting the hibernation file on the hard disk is managed by the OS file system in the form of a complex table. Therefore according to the present invention, before starting to transfer data to the hibernation file, a complex table or driver managed by the OS file system is accessed to obtain the location information of these sectors, thereby converting the location information into independent allocation information, and using the Information is input to the buffer (PM memory). Then when the data is transferred from VRAM and memory to the hard disk device, its separate information is dedicated to know the sector position of the file. Therefore, when data is transferred to the hard disk, the file location information area such as the FAT area on the hard disk may not be accessed, so that the storage operation can be accelerated.

Also according to the present invention, allocation information on an independent hibernation file prepared in performing a store operation is written into a portion of the hibernation file. At the same time, its start address is written in a block located at a fixed address on the hard disk. When data is transferred from the hard disk device to VRAM and memory, the allocation information stored in the file is used to know the location of the sectors that make up the file. Therefore, when data is transferred from the hard disk device, there is no need to access the file space allocation information area such as the FAT area on the hard disk. Therefore, when the wake-up operation is performed, the frequency of accessing the hard disk to obtain the allocation information of the hibernation file can be minimized, so that the recovery operation can be accelerated.

F. Icon display operation

Referring to FIG. 12 , operations related to icon display (steps 703 to 705 and steps 715 to 717 ) will be described more specifically below.

According to the present invention, the contents of the main memory and the contents of the VRAM are separated for management purposes. When the system enters the hibernation mode, the PMC stores the contents of the VRAM on the hibernation file (step 1201). After storing the original data, set the VGA chip (video controller) to the graphics mode, and write the icon image on the VRAM, so as to display the image on the display device connected to the system main body (steps 1203 and 1204). The icon remains displayed while data is being transferred from main memory to hard disk.

When waking up the operation, set the VGA chip to the graphics mode, and write the icon image on the VRAM, so as to display the image on the display device (steps 1205 and 1206). While the data is being transferred from the hard disk to the main memory, the icon is displayed (step 1207). Then restore the original data of the VRAM (step 1208).

While accessing the VRAM (steps 1203 to 1208), icons are not displayed. However, the time to access VRAM is much shorter than the time to access main memory (steps 1204 and 1208). In steps 1203 and 1208, only the icon is not displayed at this moment, which does not have any disadvantages in practice.

FIG. 13 shows an example of the screen shown in step 1203. The icon 101 represents the system, 102 represents the hard disk device, and 103 represents the direction of data transfer. These icons are surrounded by icon frames 104 and 105 . The color of the area 106 and the color of the area 107 within the icon frame 104 is different from the color of the background 108 .

FIG. 14 shows an example of the screen shown in step 1208 of FIG. 12 . This example is the same as the corresponding part of FIG. 13 except that the positions of the icons 101 and 102 are changed.

Referring to FIG. 15 , the common icon drawing steps in steps 1203 and 1206 in FIG. 12 will be described in detail. Initially, the PMC sets the background color data on the entire VRAM so as to cover the screen with the background color (step 1501). The PMC then paints the areas 106 and 107 within the icon box with a different color than the background (step 1502). As shown in Figures 13 and 14, the areas 106 and 107 are rectangles, so the program (PMC) can very conveniently specify their positions on the screen and color their interiors. In steps 1503 and 1504, the image data of icons 101, 102 and 103 are read from the PM memory to set them on the VRAM. Since the amount of data of icon images is small, the images are pre-stored in ROM so that they are written on PM memory at POR.

The hibernation icon may be a still image. However, as data is transferred between the hard disk and main memory, VRAM is accessed regularly, rewriting the contents, thus changing the hibernation icon over time. For example, flashing the arrow icon 103 or adding an image representing the amount of saved/restored data in the system icon 101 .

In this way the main memory blocks and the VRAM data blocks are separated for management according to the present invention. When the system enters hibernation mode, the original data of VRAM is stored first. The raw data of the main memory is then stored. In addition, when the system is in the wake-up state, the original data of the main memory is restored before the original data of the VRAM is restored. That is, no matter whether it is a save operation or a restore operation, the access process to the VRAM is different from the access process to the main memory.

It is assumed that main memory blocks and VRAM data blocks are not separated for management. When the contents of VRAM are saved before the contents of main memory are saved, the contents of VRAM must be restored before the contents of main memory. Therefore, when the system enters hibernation mode, even if the icon is displayed when the system wakes up, the icon cannot be displayed at this time. Conversely, if the contents of main memory are saved first, and then the contents of VRAM are saved, icons cannot be displayed when entering hibernation mode.

Therefore, in order to display icons without damaging the original data in VRAM when entering hibernation mode and waking up, as proposed in the specification of the present invention, it is necessary to separate the main memory data block from the block of VRAM, from The order of access to VRAM and main memory is changed from the time of the save operation to the time of the restore operation.

G. FDD change line simulation

The FDD change line emulation supported by the PMC will be described below with reference to FIGS. 16 and 22 .

FIG. 16 shows the hardware components related to FFD change line simulation separated from FIG. 1 . The parts shown in Fig. 1 include FD (floppy disk) 94 installed in FDD, change line 92 between FDD and FDC, change line status register 90 in FDC, and trap logic storing addresses to be monitored in trap logic circuit Circuit 96.

The method of accessing the FD generally differs depending on whether the FD has been accessed before. When the FD has been accessed (read/written) before, the file allocation information read at that time (when DOS serves as the OS file system) is stored in a predetermined memory address managed by the OS file system. Therefore, it is no longer necessary to read allocation information from FD. This speeds up the second visit to the FD.

The following mechanism is generally used to determine whether the allocation information on the FD in the main memory is valid. The change line connecting FDD and FDC is a signal line specially used to monitor the connection and removal of FD on FDD. The change line is automatically activated when the system is powered on. Then POST accesses FDD through FDC, detects the presence of FD, and the change line automatically becomes inactive. When no FD is detected, the change line remains active. Also, when inserting FD, the change line becomes active. When actually accessing the inserted FD, the change line automatically becomes inactive. When the FD is removed, the change line becomes active again. In this embodiment, the high state corresponds to the active state and the low state corresponds to the inactive state.

The flag reflects the state of the change line. Bit 7 of the change line status register (register 90 in Fig. 16) assigned to I/O address 3F7(H) is a flag (change line flag) at that time. Bit 7 indicates that the change line is active when the assumed value is 1, and that the change line is not active when the assumed value is 0.

The BIOS or drivers access the FDC directly (e.g. BIOS when DOS is used as the OS file system, and drivers when OS/2 is used as the OS file system). The BIOS/driver reads the content of the change line status register, when bit line 7 is assumed to be 1, invalidates the allocation information on the FD in the main register, and reads the new file allocation information on the FD.

So when the system enters hibernation mode, FD is inserted into FDD. In addition, when the FD has been accessed, the file allocation information of the FD is saved on the hard disk, and restored in the memory when the system wakes up.

Then in hibernate mode FD swap, POST detects FD resides in FDD. When the wakeup sequence is complete, the change line signal becomes inactive. Therefore, the BIOS/driver has its disadvantage that it determines the file allocation information stored on the old FD that will become valid, and uses this information to access the FD currently inserted in the FDD, and reads out wrong data, thereby destroying the Data on the FD. There is also the possibility of causing similar problems in the case of resuming after a pause.

Issues related to suspending or hibernating media transitions also exist for stick memory media (such as SSF). In the case of this medium, however, well-established software has been prepared. In other words, when the card is installed on the system, the system goes into low power mode. When the system leaves this mode, software tricks the system into thinking the card appears to have been removed when entering low power mode. On the other hand, when the software resumes or wakes up, it tricks the system into thinking that the card appears to be installed. When receiving such falsified information, the system invalidates the file allocation information on the card in the main memory and obtains new allocation information. Thus, when entering and remaining in low power mode, the software does a fake operation of the system with the software in order to stop power to the card.

However, in the case of FD, a method is used in which the state of the state change line signal changes with a predetermined time according to hardware, and the state is read out by the CPU. When adapting the method formed so as to solve the above-mentioned problems caused by exchanging FDs, all this is done in a low power consumption mode, a device other than a card-type memory medium must be used.

Therefore, the present invention fakes its state in such a way that the BIOS/driver detects the change line state plug for the first time after a wake-up operation or after completing its sequence. Then even if the FD is inserted into the FDD, the software makes the system think that it seems that the FD has been removed from the FDD, thereby flashing the file allocation information on the FD. Specifically, two methods can be used.

(1) Set a trap for accessing the changeline state in order to temporarily falsify the value of a changeline state flag.

(2) Prepare a board that allows change line signal operation by hardware.

Each of the above methods will be described in terms of wake-up patterns from hibernate mode. Note, however, that the present invention can be used for resume operations from suspend mode.

(1) The latest laptops provide mechanisms for trapping I/O accesses. This mechanism can be realized by combining Intel 80486SL (CPU) and 82360SL (trap logic circuit). When the I/O address is set in the 82360SL register (register 96 in Figure 16), the 80486SL issues an instruction to access the I/O address, and at this time the 82360SL issues a system interrupt instruction to the system. In response to a system interrupt, start the handler (PMC). After analyzing the cause of the interruption, it has been determined that the system interruption is caused by accessing a predetermined I/O address, and the system transfers to the trap routine.

Typically the trap mechanism has been used to power up a powered off device when a command to access the device was issued prior to accessing the device. The first method of fictitiously changing the state of the line employs a trap mechanism.

Referring to Fig. 17, the steps related to the imaginary operation will be described in detail below. As described above, once the hibernation flag is asserted by the POST running after power up, the system enters a wakeup sequence (steps 171, 172). The change line becomes active when the power is turned on. However, when POST detects that the FD is still inserted in the FDD, the system becomes inoperative.

At step 173, the PMC sets the system in a state ready to change line emulation. Specifically, the value of the register 96 of the trap logic circuit 16 (see FIG. 16 ) is set to 3F7 (H). After this, control of the system returns to the OS/application.

When the FD is accessed for the first time after resuming execution of the OS/application, the fabrication of the state of the change line is done (step 174). Step 174 will be further described below in conjunction with FIGS. 18 and 19 .

Figure 19 shows the code portion of the BIOS/driver. When the instruction MOV DX, 3F7(H) is executed, the DX register of the CPU is loaded into 3F7(H). Then when the instruction IN AL, DX is executed, the I/O address 3F7 (H) is accessed so that the AL register in the CPU can store the content of the change line status register. At this time, a system interrupt is executed, thereby executing the trap handler (PMC). The handler analyzes the cause of the system interrupt and thus transfers to the routine that executes the trap that accesses I/O address 3F7(H). The routine sets the value of bit 7 in the AL register to 1 and returns it to the BIOS/driver. Therefore, the following command TEST AL, 80H sends the information that the value of bit 7 is set to 1 to the BIOS/driver. According to this, the OS/driver flashes the file allocation information in the FD in the memory. Then in order to access the desired file on the FD, the system reads the allocation information in the FD.

Incidentally, before returning to the BIOS/driver, the PMC clears the value set in the trap register (step 175 of FIG. 17). Therefore, the state of the line is not faked during access to the FD after the first time.

(2) The second method is realized by adding hardware components to the board, as shown in Figure 20. The added components are I/O port 110 including register 112 , I/O address decoder 114 , OR gate 116 and signal lines 118 and 120 . A specific I/O address (1500(H)) is assigned to the register 112 . A specific bit value (bit 0) representing register 112 is input to an input of OR gate 116 via signal line 118 . The change line signal is input from FDD92 to the other input terminal of OR gate 116 . The output of OR gate 116 is connected to bit 7 of change line status register 90 . The output of OR gate 116 becomes the value of bit 7 of register 90 . The I/O address decoder 114 monitors the address bus 14 and decodes the address signal 3F7 (H), thereby outputting a pulse signal to the I/O port 110 . The output terminal of the decoder 110 is connected with the clearing terminal of the register 112 .

Referring to FIG. 21, the flow of steps of the second method will be described. Steps 211 and 212 are the same as steps 171 and 172 in FIG. 17, so their descriptions are omitted. In step 213, to set the FDD change line emulation, the PMC command I/O address 1500 (H) is specified, thereby setting the value of bit 0 to 1. As a result, as shown in Figure 22, changing the line state remains inactive for accessing the FDC with POST. However, since signal line 118 becomes active, the state of signal line 120 becomes active. Bit 7 of the change line status register 90 is therefore set to one.

After step 213, control of the system returns to the OS/application. While the OS/application program is executing, the value of bit 7 in register 90 remains at 1, and the virtual change line state continues.

The value of bit 7 becomes 1 when the BIOS/driver starts to read address 3F (H) in order to access the FD after restoring the OS/application. The OS/driver then flashes the file allocation information of the FD.

During an access to address 3F7(H), slave decoder 114 generates a pulse which clears register 112. Thus, none of the inputs to OR gate 116 becomes active. The state of bit 7 of the change line register 90 is unchanged. FDD change line emulation reset (step 214) is accomplished in this way which is different from the first method.

Some systems do not have a trap mechanism. In some cases, even if some systems have a trap mechanism, the operation of the trap mechanism is limited. In this case, the second method works.

According to the present invention, it is possible to restore and wake up information necessary for resuming a task from a removable external storage device, regardless of whether a system to be woken up has performed a hibernation operation.

Claims (18)

1, a kind of information handling system, this system comprises CPU, volatile main memory and non-volatile External memory equipment, and support hibernation function, utilize this function when predetermined condition occurring, task suspension, and the content of described primary memory is stored in the described External memory equipment before described storer outage, it is characterized in that described External memory equipment is dismountable, and the historical information of expression outage only exists in the described External memory equipment by a series of storage operations that enter hibernate mode.

2,, it is characterized in that described historical information is stored in the presumptive area of described External memory equipment according to the information handling system of claim 1.

3, a kind of information handling system, this system comprises CPU, volatile main memory and non-volatile External memory equipment, and support hibernation function, utilize this function when predetermined condition occurring, task suspension, and the content of described primary memory is stored in the described External memory equipment before described storer outage, it is characterized in that described External memory equipment is dismountable, and described system comprises the device of the configuration information that is used for storing the described system that has described External memory equipment.

4,, it is characterized in that described historical information is stored in the presumptive area of described External memory equipment according to the information handling system of claim 3.

5, according to the information handling system of claim 3, the configuration information that it is characterized in that described system is the size of primary memory.

6, according to the information handling system of claim 3, the configuration information that it is characterized in that described system is the kind and the quantity thereof of I/O equipment.

7, according to the information handling system of claim 3, the configuration information that it is characterized in that described system is the I/O base address of I/O equipment.

8, a kind of information handling system, this system comprises CPU, volatile main memory and dismountable non-volatile External memory equipment, and this system supports arousal function, utilize the task that this function has been interrupted in described system to obtain recovery, connection responds to system power supply, described External memory equipment has been installed in this system, and described task in described External memory equipment, is characterized in that the information stores of necessity:

Storage representation has been carried out the historical information of hibernation operation in described system in the presumptive area of described External memory equipment, and described External memory equipment is former to be installed in the described system; And

Described system comprises the described historical information of check and carries out the device of wake operation.

9, information handling system according to Claim 8 is characterized in that described system comprises that the final step that is used in a series of wake up process makes the invalid device of described historical information.

10, a kind of information handling system, this system comprises CPU, volatile main memory and dismountable non-volatile External memory equipment of independently supporting arousal function, according to progress, the task that arousal function restarts to be placed in the system and inquired in system, described External memory equipment is former to be installed in this system, data necessary has existed in the described External memory equipment, the control information that comprises system's preparation of described tasks interrupt time is included in the described External memory equipment

Described system is characterised in that and comprises:

(a) device that compares of the system configuration information that is used for being stored in the system configuration information of described External memory equipment and system itself,

(b) according to the consistance of described configuration information, will be used for recovering described task information necessary and return to the device of described primary memory from described External memory equipment, and

(c) according to the nonuniformity of described configuration information, refusal returns to device the described primary memory with information from described External memory equipment.

11,, it is characterized in that by system cut-off prompting user being changed the configuration of system itself according to the information handling system of claim 10.

12,, it is characterized in that described suggestion device shows the system configuration information that is stored in the described External memory equipment to the user according to the information handling system of claim 10.

13, according to the information handling system of claim 10, the configuration information that it is characterized in that described system is the size of primary memory.

14, according to the information handling system of claim 10, the configuration information that it is characterized in that described system is the kind or the quantity of I/O equipment.

15, according to the information handling system of claim 10, the configuration information that it is characterized in that described system is the I/O base address of I/O equipment.

16, according to the information handling system of claim 10, it is characterized in that described control information comprises the historical information that hibernation is worked in the system of being illustrated in, described external memory is former to be installed in this system.

17,, it is characterized in that described device (c) comprises the suggestion device that makes described historical information invalid according to the information handling system of claim 16.

18,, it is characterized in that described system comprises that the final step that is used in a series of wake up process makes the invalid device of described control information according to the information handling system of claim 10.

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