CN111129002A - Electrostatic protection circuit - Google Patents
Electrostatic protection circuit Download PDFInfo
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- CN111129002A CN111129002A CN201911256096.7A CN201911256096A CN111129002A CN 111129002 A CN111129002 A CN 111129002A CN 201911256096 A CN201911256096 A CN 201911256096A CN 111129002 A CN111129002 A CN 111129002A
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- 238000009792 diffusion process Methods 0.000 claims abstract description 80
- 230000003071 parasitic effect Effects 0.000 claims abstract description 35
- 210000000746 body region Anatomy 0.000 claims abstract description 31
- 239000003990 capacitor Substances 0.000 claims description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 229920005591 polysilicon Polymers 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 6
- 229910052760 oxygen Inorganic materials 0.000 claims 6
- 239000001301 oxygen Substances 0.000 claims 6
- 230000003068 static effect Effects 0.000 abstract description 15
- 230000005611 electricity Effects 0.000 abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
- H10D89/921—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs characterised by the configuration of the interconnections connecting the protective arrangements, e.g. ESD buses
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- Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
本发明公开了一种静电保护电路，包括：寄生可控硅和触发电路；第一PLDMOS包括体区，漂移区，栅极结构、第一源端P+扩散区、第一源端N+扩散区、第一漏端P+扩散区。第一PLDMOS中通过插入第一漏端N+扩散区形成寄生可控硅；栅极结构、第一源端N+扩散区和第一源端P+扩散区连接在一起形成阳极，阳极连接静电端；第一漏端N+扩散区接地形成阴极；第一漏端P+扩散区作为触发电极，第一漏端P+扩散区和第一漏端N+扩散区之间连接有第一电阻；触发电路连接在阳极和触发电极之间；当无静电时，触发电路关闭；当有静电时，触发电路导通并触发寄生可控硅导通。本发明能调节电路的可控硅的触发电压，从而能有效保护住被保护的内部高压器件。
The invention discloses an electrostatic protection circuit, comprising: a parasitic thyristor and a trigger circuit; a first PLDMOS includes a body region, a drift region, a gate structure, a first source end P+ diffusion region, a first source end N+ diffusion region, The first drain terminal P+ diffusion region. In the first PLDMOS, a parasitic thyristor is formed by inserting the first drain end N+ diffusion region; the gate structure, the first source end N+ diffusion region and the first source end P+ diffusion region are connected together to form an anode, and the anode is connected to the electrostatic end; A drain end N+ diffusion region is grounded to form a cathode; the first drain end P+ diffusion region is used as a trigger electrode, and a first resistor is connected between the first drain end P+ diffusion region and the first drain end N+ diffusion region; the trigger circuit is connected between the anode and the Between the trigger electrodes; when there is no static electricity, the trigger circuit is turned off; when there is static electricity, the trigger circuit is turned on and the parasitic thyristor is turned on. The invention can adjust the trigger voltage of the thyristor of the circuit, thereby effectively protecting the protected internal high-voltage device.
Description
Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to an electrostatic protection circuit.
Background
As shown in fig. 1, it is an applied circuit diagram of the electrostatic protection circuit; the electrostatic protection circuit 102 is disposed between the input/output pad 101 and the ground, and when static electricity occurs in the input/output pad 101, the electrostatic protection circuit 102 is triggered and discharges the static electricity, thereby protecting the internal circuit 103.
FIG. 2 is a schematic cross-sectional view of a conventional ESD protection circuit; the circuit shown in fig. 2 adopts a high-voltage PLDMOS structure, a body region 202 composed of a high-voltage N well and a drift region 203 composed of a high-voltage P well are formed on a P-type semiconductor substrate such as a silicon substrate 201, and a gate dielectric layer such as a gate oxide layer 204 and a polysilicon gate 205 covers the surface of the body region 202 and extends to the surface of the drift region 203. A source region 206 composed of a P + region formed in the body region 202 and a first side of the polysilicon gate 205 are self-aligned, a P + region formed in the body region 202 is composed of a body region lead-out region 209, and a field oxide layer 210b is isolated between the source region 206 and the body region lead-out region 209. A drain P + diffusion region 207 composed of a P + region and a drain N + diffusion region 208 composed of an N + region are formed in the drift region 203, and the drain P + diffusion region 207 and the polysilicon gate 205 are spaced apart by a certain distance and are isolated by a field oxide layer 210 a. The source region 206, the body lead-out region 209 and the polysilicon gate 205 are all connected to a static terminal, the resistor R101 is connected between the polysilicon gate 205 and the static terminal, and the drain terminal N + diffusion region 208 is connected to the ground GND.
In the existing method, a high-voltage Silicon Controlled Rectifier (SCR) structure composed of a high-voltage PLDMOS shown in fig. 2 is usually an external structure, but the general SCR structure itself does not have the capability of adjusting trigger voltage, and sometimes it is impossible to effectively protect an internal high-voltage device to be protected.
Disclosure of Invention
The technical problem to be solved by the invention is to provide an electrostatic protection circuit, which can adjust the trigger voltage of the controllable silicon of the circuit, thereby effectively protecting the protected internal high-voltage device.
In order to solve the above technical problem, the present invention provides an electrostatic protection circuit, including: parasitic thyristors and trigger circuits.
The parasitic silicon controlled rectifier is a parasitic structure of the first PLDMOS.
The first PLDMOS comprises an N-type lightly doped body region, a P-type lightly doped drift region and a grid structure.
And a first source end P + diffusion region consisting of a P + region and a first source end N + diffusion region consisting of an N + region are formed in the body region.
A first drain-end P + diffusion region composed of a P + region is formed in the drift region.
And a first drain end N + diffusion region consisting of an N + region is also formed in the drift region, and the parasitic controlled silicon is formed by inserting the first drain end N + diffusion region.
The grid structure, the first source end N + diffusion region and the first source end P + diffusion region are connected together to form an anode, and the anode is connected with an electrostatic end.
And the first drain terminal N + diffusion region is grounded to form a cathode.
The first drain terminal P + diffusion region is used as a trigger electrode, and a first resistor is connected between the first drain terminal P + diffusion region and the first drain terminal N + diffusion region.
The trigger circuit is connected between the anode of the parasitic thyristor and the trigger electrode.
When the static end is free of static electricity, the trigger circuit is closed; when the static end has static electricity, the trigger circuit is conducted and forms trigger current from the static end to the trigger electrode, so that the parasitic silicon controlled rectifier is conducted.
In a further improvement, the trigger circuit comprises a second PLDMOS, a second resistor and a first capacitor.
And the source electrode of the second PLDMOS is connected with the electrostatic end, and the drain electrode of the second PLDMOS is connected with the trigger electrode.
The first end of the second resistor is connected with the electrostatic end, the second end of the second resistor is connected with the grid electrode of the second PLDMOS and the first end of the first capacitor, and the second end of the first capacitor is connected with the trigger electrode.
In a further improvement, the second PLDMOS is a high voltage device capable of withstanding electrostatic voltages.
In a further improvement, the first capacitor is a high voltage device capable of withstanding an electrostatic voltage.
In a further improvement, the second resistor is a polysilicon resistor or a doped diffused resistor.
In a further improvement, the trigger circuit forms an adjustable structure of trigger voltage for enabling the parasitic thyristor to be conducted.
In a further improvement, the adjustable structure of the trigger voltage for the conduction of the parasitic thyristor comprises the first capacitor, and the larger the first capacitor is, the smaller the trigger voltage is.
In a further improvement, the adjustable structure of the trigger voltage for the conduction of the parasitic thyristor comprises the second resistor, and the larger the second resistor is, the smaller the trigger voltage is.
In a further improvement, the adjustable structure of the trigger voltage for the conduction of the parasitic thyristor comprises an effective channel width of the second PLDMOS, and the smaller the effective channel width of the second PLDMOS, the smaller the trigger voltage.
In a further improvement, the first PLDMOS is a high voltage device capable of withstanding electrostatic voltages.
In a further improvement, the body region is composed of a high-voltage N well, the drift region is composed of a high-voltage P well, the high-voltage N well and the high-voltage P well are both formed in a P-type semiconductor substrate, and the body region is laterally contacted with the drift region.
In a further improvement, a first field oxide is formed on the surface of the drift region between the first drain P + diffusion region and the body region, a distance is provided between a first side surface of the first field oxide and the body region, and a second side surface of the first field oxide is in contact with the first drain P + diffusion region.
And a second field oxide is formed between the first drain terminal P + diffusion region and the first drain terminal N + diffusion region.
In a further improvement, the gate structure overlies the body surface and extends laterally to the surface of the first field oxide.
In a further improvement, the first source P + diffusion region is self-aligned to the first side of the gate structure, and a third field oxide is isolated between the first source P + diffusion region and the first source N + diffusion region.
The gate structure is further improved by superposing a gate dielectric layer and a polysilicon gate.
The first resistor is a polysilicon resistor or a doped diffusion resistor.
The SCR of the electrostatic protection circuit is directly formed by inserting the high-voltage P-type LDMOS, namely the first PLDMOS into the first drain terminal N + diffusion region and then parasitizing the high-voltage P-type LDMOS, the SCR does not need to be externally connected, the SCR is connected with the trigger circuit, the trigger circuit can adjust the trigger voltage of the SCR, and finally the trigger voltage of the controllable silicon of the circuit can be adjusted, so that the protected internal high-voltage device can be effectively protected.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a circuit diagram of an application of an electrostatic protection circuit;
FIG. 2 is a schematic cross-sectional view of a conventional ESD protection circuit;
FIG. 3 is a schematic cross-sectional view of an ESD protection circuit according to an embodiment of the present invention;
fig. 4 is an equivalent circuit of the electrostatic protection circuit according to the embodiment of the present invention.
Detailed Description
Fig. 3 is a schematic cross-sectional view of an electrostatic protection circuit according to an embodiment of the invention; the electrostatic protection circuit of the embodiment of the invention comprises: parasitic thyristors 302 and a trigger circuit 304.
The parasitic thyristor 302 is a parasitic structure of the first PLDMOS 301.
The first PLDMOS301 includes an N-type lightly doped body region 2, a P-type lightly doped drift region 3, and a gate structure.
A first source P + diffusion region 6 composed of a P + region and a first source N + diffusion region 9 composed of an N + region are formed in the body region 2.
A first drain-side P + diffusion region 7 composed of a P + region is formed in the drift region 3.
A first drain terminal N + diffusion region 8 composed of an N + region is also formed in the drift region 3, and the parasitic thyristor 302 is formed by inserting the first drain terminal N + diffusion region 8.
The gate structure, the first source end N + diffusion region 9 and the first source end P + diffusion region 6 are connected together to form an anode, and the anode is connected to an electrostatic end.
The first drain terminal N + diffusion region 8 is grounded to form a cathode.
The first drain P + diffusion region 7 serves as a trigger electrode, and a first resistor R1 is connected between the first drain P + diffusion region 7 and the first drain N + diffusion region 8.
The trigger circuit 304 is connected between the anode of the parasitic thyristor 302 and the trigger electrode.
When the static end is free of static electricity, the trigger circuit 304 is turned off; when the electrostatic end has static electricity, the trigger circuit 304 is turned on and forms a trigger current from the electrostatic end to the trigger electrode, so that the parasitic thyristor 302 is turned on.
The trigger circuit 304 includes a second PLDMOS303, a second resistor R2 and a first capacitor C1.
The source electrode of the second PLDMOS303 is connected with the electrostatic terminal, and the drain electrode is connected with the trigger electrode.
A first terminal of the second resistor R2 is connected to the electrostatic terminal, a second terminal of the second resistor R2 is connected to the gate of the second PLDMOS303 and a first terminal of the first capacitor C1, and a second terminal of the first capacitor C1 is connected to the trigger electrode.
The second PLDMOS303 is a high voltage device capable of withstanding electrostatic voltages.
The first capacitor C1 is a high voltage device capable of withstanding electrostatic voltages.
The second resistor R2 is a polysilicon resistor or a doped diffused resistor.
The trigger circuit 304 forms an adjustable structure for the trigger voltage that turns on the parasitic thyristor 302.
The adjustable structure of the trigger voltage of the parasitic thyristor 302 comprises the first capacitor C1, and the larger the first capacitor C1 is, the smaller the trigger voltage is.
The adjustable structure of the trigger voltage of the parasitic thyristor 302 comprises the second resistor R2, and the larger the second resistor R2 is, the smaller the trigger voltage is.
The adjustable structure of the trigger voltage for the conduction of the parasitic silicon controlled rectifier 302 comprises the effective channel width of the second PLDMOS303, and the smaller the effective channel width of the second PLDMOS303 is, the smaller the trigger voltage is.
The first PLDMOS301 is a high voltage device capable of withstanding electrostatic voltages.
The body region 2 is composed of a high-voltage N well, the drift region 3 is composed of a high-voltage P well, the high-voltage N well and the high-voltage P well are both formed in a P-type semiconductor substrate, and the body region 2 is in lateral contact with the drift region 3.
The first field oxide 10a is formed on the surface of the drift region 3 between the first drain P + diffusion region 7 and the body region 2, a first side surface of the first field oxide 10a is spaced apart from the body region 2, and a second side surface of the first field oxide 10a is in contact with the first drain P + diffusion region 7.
A second field oxide 10b is formed between the first drain P + diffusion region 7 and the first drain N + diffusion region 8. A field oxide 10d is further formed outside the first drain-side N + diffusion region 8.
The gate structure covers the surface of the body region 2 and extends laterally to the surface of the first field oxide 10 a.
The first source end P + diffusion region 6 and the first side surface of the gate structure are self-aligned, and a third field oxide 10c is isolated between the first source end P + diffusion region 6 and the first source end N + diffusion region 9.
The grid structure is formed by superposing a grid dielectric layer 4 and a polysilicon grid 5.
The first resistor R1 is a polysilicon resistor or a doped diffused resistor.
As shown in fig. 4, it is an equivalent circuit of the electrostatic protection circuit according to the embodiment of the present invention; the PNP device 305 is composed of the first source terminal P + diffusion region 6, the body region 2, the drift region 3, and the first drain terminal P + diffusion region 7. The NPN device 304 is composed of the first source-side N + diffusion region 9, the body region 2, the drift region 3, and the first drain-side N + diffusion region 8.
The resistance Rnw is a parasitic resistance of the body region 2 between the first source terminal P + diffusion region 6 and the drift region 3.
The resistor R1a is a parallel resistance formed by the parasitic resistance of the drift region 3 between the body region 2 and the first drain-side N + diffusion region 8 and the resistor R1.
When static electricity occurs, the base voltage Vbn of the NPN device 304 rises to turn on the NPN device 304, and after the NPN device 304 is turned on, the base voltage Vbp of the PNP device 305 falls to turn on the PNP device 305, and finally, the conduction of the parasitic thyristor 302 is realized.
The SCR of the electrostatic protection circuit in the embodiment of the invention is formed by inserting a high-voltage P-type LDMOS (i.e. a first PLDMOS 301) into a first drain terminal N + diffusion region 8 and then parasitizing the high-voltage P-type LDMOS without external connection, and the SCR is connected with a trigger circuit 304, the trigger circuit 304 can realize the regulation of the trigger voltage of the SCR, and finally the trigger voltage of the controllable silicon of the circuit can be regulated, so that an internal high-voltage device to be protected can be effectively protected.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (15)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911256096.7A CN111129002B (en) | 2019-12-10 | 2019-12-10 | Electrostatic protection circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911256096.7A CN111129002B (en) | 2019-12-10 | 2019-12-10 | Electrostatic protection circuit |
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| Publication Number | Publication Date |
|---|---|
| CN111129002A true CN111129002A (en) | 2020-05-08 |
| CN111129002B CN111129002B (en) | 2022-08-16 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911256096.7A Active CN111129002B (en) | 2019-12-10 | 2019-12-10 | Electrostatic protection circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112736124A (en) * | 2020-12-28 | 2021-04-30 | 矽力杰半导体技术(杭州)有限公司 | ESD protection device |
| WO2024179208A1 (en) * | 2023-02-28 | 2024-09-06 | 杰华特微电子股份有限公司 | Electrostatic discharge semiconductor device and manufacturing method therefor, and integrated circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109148438A (en) * | 2018-07-26 | 2019-01-04 | 上海华虹宏力半导体制造有限公司 | High-voltage electrostatic protection device and equivalent circuit |
| CN110190052A (en) * | 2019-06-04 | 2019-08-30 | 电子科技大学 | A three-terminal compact composite SCR device for full-chip ESD protection |
-
2019
- 2019-12-10 CN CN201911256096.7A patent/CN111129002B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109148438A (en) * | 2018-07-26 | 2019-01-04 | 上海华虹宏力半导体制造有限公司 | High-voltage electrostatic protection device and equivalent circuit |
| CN110190052A (en) * | 2019-06-04 | 2019-08-30 | 电子科技大学 | A three-terminal compact composite SCR device for full-chip ESD protection |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112736124A (en) * | 2020-12-28 | 2021-04-30 | 矽力杰半导体技术(杭州)有限公司 | ESD protection device |
| CN112736124B (en) * | 2020-12-28 | 2023-10-27 | 矽力杰半导体技术(杭州)有限公司 | ESD protection device |
| WO2024179208A1 (en) * | 2023-02-28 | 2024-09-06 | 杰华特微电子股份有限公司 | Electrostatic discharge semiconductor device and manufacturing method therefor, and integrated circuit |
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| Publication number | Publication date |
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| CN111129002B (en) | 2022-08-16 |
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