CN111128966A - Alignment structure and package cutting method - Google Patents
Alignment structure and package cutting method Download PDFInfo
- Publication number
- CN111128966A CN111128966A CN201911358850.8A CN201911358850A CN111128966A CN 111128966 A CN111128966 A CN 111128966A CN 201911358850 A CN201911358850 A CN 201911358850A CN 111128966 A CN111128966 A CN 111128966A
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- cutting
- alignment structure
- alignment
- cutting channel
- channel
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- 238000005520 cutting process Methods 0.000 title claims abstract description 67
- 238000000034 method Methods 0.000 title claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 24
- 229910003460 diamond Inorganic materials 0.000 claims description 5
- 239000010432 diamond Substances 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 238000004806 packaging method and process Methods 0.000 abstract description 10
- 238000010586 diagram Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides an alignment structure and a packaging and cutting method, wherein a cutting channel is formed between two adjacent single chips to be separated, the alignment structure is distributed at two ends of any cutting channel and is communicated with the cutting channel, the alignment structure at any end is surrounded by edges of metal circuit layers of the multiple single chips to be separated, the size of the alignment structure is larger than that of the cutting channel, and the alignment structure is one or more of a circle, an ellipse, a polygon and an abnormity, wherein the shape of the alignment structure is different from that of the cutting channel. When the invention is used for rewiring, a special pattern is made at the center of each cutting channel under the condition of not influencing the performance of a chip and is used as a special mark for cutting alignment, and the special mark can effectively improve the problem of cutting alignment deviation, reduce the abnormity caused by cutting and improve the yield of products.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an alignment structure and a packaging and cutting method.
Background
As shown in fig. 1, the CIS chip package structure is provided. And bonding the wafer 90 and the glass substrate 100, rewiring 70 on the back of the wafer by using a through silicon via technology to complete signal output, and finally cutting into single chips. The current cutting method adopts two steps of cutting, pre-cutting and final cutting, wherein the pre-cutting is to perform primary cutting on the wafer along the cutting channel to the cofferdam 50, perform final cutting after the whole packaging is completed, and cut and separate the residual cofferdam and the glass substrate 100 into single chips.
As shown in fig. 2, which is a conventional rewiring plan view of the metal wiring layer 70, the design uses the rewiring method to lead out the Pad 30 signal on the chip to the ball, so as to realize the function. In order to make the design beautiful and meet the process requirements, the tail ends of the metal circuit layer 70 covering the Pad 30 are all parallel and level, and the rewiring at the four corners of the chip is in a right-angle shape. If the metal circuit layer covers the groove structure below, the tail end metal circuit layer is distributed in the groove structure of the cutting channel, so that the alignment mark of the chip is fuzzy in the cutting process, even the alignment mark is not arranged, alignment deviation is caused, the effective area of the chip is cut, and the function failure is caused.
Therefore, it is necessary to provide a further solution to the above problems.
Disclosure of Invention
The invention aims to provide a contraposition structure and a packaging and cutting method, so as to overcome the defects in the prior art.
In order to solve the technical problems, the technical scheme of the invention is as follows:
a cutting channel is formed between two adjacent single chips to be separated, the alignment structures are distributed at two ends of any cutting channel and are communicated with the cutting channel, the alignment structure at any end is surrounded by edges of metal circuit layers of the multiple single chips to be separated, the size of the alignment structure is larger than that of the cutting channel, and the alignment structure is one or more of a circle, an ellipse, a polygon and an abnormity, wherein the shape of the circle, the ellipse, the polygon and the abnormity is different from that of the cutting channel.
As an improvement of the alignment structure, the alignment structure is a diamond structure or a square surrounded by the edge outlines of the metal circuit layers of four adjacent single chips.
In order to solve the technical problems, the technical scheme of the invention is as follows:
a package cutting method comprises the following steps:
designing a hollow area of the mask plate according to the wiring shape of the metal circuit layer and the alignment structure;
rewiring design is carried out on each single chip on the wafer through a designed mask plate, and alignment structures suitable for identification are formed at two ends of the cutting channel;
and cutting and separating each single chip along the cutting path through the indication of the alignment structure.
As an improvement of the packaging and cutting method, four corners of an area corresponding to the single chip metal circuit layer on the mask plate are cut off by a right angle to form a chamfer shape suitable for manufacturing an alignment structure.
As an improvement of the packaging and cutting method, the single chip on the wafer is subjected to rewiring design in the modes of coating, exposure, development and metal etching by means of a designed mask plate.
As an improvement of the package cutting method of the present invention, the single chip is a CIS chip.
Compared with the prior art, the invention has the beneficial effects that: when the invention is used for rewiring, a special pattern is made at the center of each cutting channel under the condition of not influencing the performance of a chip and is used as a special mark for cutting alignment, and the special mark can effectively improve the problem of cutting alignment deviation, reduce the abnormity caused by cutting and improve the yield of products.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a CIS chip package structure in the prior art;
FIG. 2 is a plan view of a conventional metal wiring layer rewiring in the prior art;
FIG. 3 is a plan view of a star fixing alignment structure of a single chip according to an embodiment of the present invention;
fig. 4 and 5 are schematic diagrams illustrating a package dicing method according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides a method for improving cutting alignment from wiring design. When rewiring is carried out, under the condition that the performance of a chip is not influenced, a special graph is made at the center of each cutting channel and used as a special mark for cutting alignment, the special mark can effectively improve the problem of cutting alignment deviation, the abnormity caused by cutting is reduced, and the product yield is improved.
As shown in fig. 3, in an embodiment of the present invention, a scribe line is formed between two adjacent single chips 300 to be separated, the alignment structure 100 is distributed at two ends of any scribe line and is communicated with the scribe line, and the position of the scribe line can be indicated by the alignment structure 100, so as to be used as a positioning mark during dicing.
In order to form the alignment structure 100, the metal circuit layers 200 of the single chips 300 need to be designed such that the alignment structure 100 at either end is surrounded by the edges of the metal circuit layers 200 of the multiple single chips 300 to be separated. Meanwhile, in order to make the alignment structure 100 easily recognizable, the size of the alignment structure 100 is larger than the size of the scribe line, and is one or more of a circle, an ellipse, a polygon and an irregular shape different from the shape of the scribe line. For example, the alignment structure 100 is a diamond structure or a square surrounded by the edge outlines of the metal circuit layers 200 of four adjacent single chips 300. At this time, the diamond structure or the square is formed by the right angle at the corner of the cut metal line layer 200.
The invention also provides a packaging and cutting method. The packaging and cutting method comprises the following steps:
designing a hollow area of the mask plate according to the wiring shape of the metal circuit layer and the alignment structure; rewiring design is carried out on each single chip on the wafer through a designed mask plate, and alignment structures suitable for recognition are formed at two ends of the cutting channel; and cutting and separating each single chip along the cutting path through the indication of the alignment structure.
The packaging and cutting method of one embodiment of the invention comprises the following steps:
as shown in fig. 4, the hollow area of the mask is designed according to the wiring shape of the metal circuit layer and the diamond alignment structure. At the moment, the four corners of the area corresponding to the single chip metal circuit layer on the mask plate are cut off to form a chamfer shape suitable for manufacturing the alignment structure.
As shown in fig. 5, the individual chips 300 on the wafer 500 are re-wired by the designed mask plate, and the alignment structures 100 having the above shapes suitable for recognition are formed at both ends of the scribe line. Wherein the individual chips 300 are arranged in an array on the wafer 500. In one embodiment, the single chip 300 on the wafer 500 is re-wired by means of a designed mask plate through coating, exposure, development and metal etching. In this embodiment, the single chip 300 is a CIS chip.
Through the indication of the alignment structure 100, the individual chips 300 are cut and separated along the dicing streets, and the subsequent packaging steps are performed.
In summary, when the rewiring is performed, a special pattern is formed at the center of each cutting track without affecting the performance of the chip, and the special pattern is used as a special mark for cutting alignment, so that the problem of cutting alignment deviation can be effectively solved, the abnormity caused by cutting is reduced, and the product yield is improved.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (6)
1. The alignment structure is characterized in that a cutting channel is formed between two adjacent single chips to be separated, the alignment structure is distributed at two ends of any cutting channel and is communicated with the cutting channel, the alignment structure at any end is surrounded by edges of metal circuit layers of the multiple single chips to be separated, the size of the alignment structure is larger than that of the cutting channel, and the alignment structure is one or more of a circle, an ellipse, a polygon and an abnormity, wherein the shape of the circle, the ellipse, the polygon and the abnormity is different from that of the cutting channel.
2. The alignment structure of claim 1, wherein the alignment structure is a diamond structure or a square surrounded by the edge outlines of the metal circuit layers of four adjacent single chips.
3. A package cutting method is characterized by comprising the following steps:
designing a hollow area of the mask plate according to the wiring shape of the metal circuit layer and the alignment structure of claim 1 or 2;
rewiring design is carried out on each single chip on the wafer through a designed mask plate, and alignment structures suitable for identification are formed at two ends of the cutting channel;
and cutting and separating each single chip along the cutting path through the indication of the alignment structure.
4. The package cutting method according to claim 3, wherein four corners of the area of the mask corresponding to the metal wiring layer of the single chip are cut off by a right angle to form a chamfered shape suitable for manufacturing the alignment structure.
5. The package cutting method according to claim 3, wherein the rewiring design of the single chip on the wafer is performed by means of a designed mask plate through coating, exposure, development and metal etching.
6. The package dicing method according to claim 3, wherein the single chip is a CIS chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911358850.8A CN111128966A (en) | 2019-12-25 | 2019-12-25 | Alignment structure and package cutting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911358850.8A CN111128966A (en) | 2019-12-25 | 2019-12-25 | Alignment structure and package cutting method |
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| Publication Number | Publication Date |
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| CN111128966A true CN111128966A (en) | 2020-05-08 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201911358850.8A Pending CN111128966A (en) | 2019-12-25 | 2019-12-25 | Alignment structure and package cutting method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118657112A (en) * | 2024-08-16 | 2024-09-17 | 苏州亿麦矽半导体技术有限公司 | A wiring adjustment method and device |
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| CN1664991A (en) * | 2004-03-05 | 2005-09-07 | 三洋电机株式会社 | Semiconductor device and manufacturing method of the same |
| CN101521493A (en) * | 2008-02-26 | 2009-09-02 | 富士通媒体部品株式会社 | Electronic component and method of manufacturing the same |
| CN102184903A (en) * | 2011-03-09 | 2011-09-14 | 格科微电子（上海）有限公司 | Encapsulated semiconductor chip and manufacturing method of through holes thereof |
| CN102683311A (en) * | 2011-03-10 | 2012-09-19 | 精材科技股份有限公司 | Chip package and method for forming the same |
| CN102881678A (en) * | 2011-07-11 | 2013-01-16 | 台湾积体电路制造股份有限公司 | Mechanisms for marking the orientation of a sawed die |
| CN103887238A (en) * | 2014-04-01 | 2014-06-25 | 惠州硕贝德无线科技股份有限公司 | Cutting and classifying method for wafer after BGA package is completed |
| CN106531689A (en) * | 2015-09-15 | 2017-03-22 | 上海微世半导体有限公司 | Production method and equipment for back-surface cutting counterpoint line of glass passivation silicon wafer |
-
2019
- 2019-12-25 CN CN201911358850.8A patent/CN111128966A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1664991A (en) * | 2004-03-05 | 2005-09-07 | 三洋电机株式会社 | Semiconductor device and manufacturing method of the same |
| CN101521493A (en) * | 2008-02-26 | 2009-09-02 | 富士通媒体部品株式会社 | Electronic component and method of manufacturing the same |
| CN102184903A (en) * | 2011-03-09 | 2011-09-14 | 格科微电子（上海）有限公司 | Encapsulated semiconductor chip and manufacturing method of through holes thereof |
| CN102683311A (en) * | 2011-03-10 | 2012-09-19 | 精材科技股份有限公司 | Chip package and method for forming the same |
| CN102881678A (en) * | 2011-07-11 | 2013-01-16 | 台湾积体电路制造股份有限公司 | Mechanisms for marking the orientation of a sawed die |
| CN103887238A (en) * | 2014-04-01 | 2014-06-25 | 惠州硕贝德无线科技股份有限公司 | Cutting and classifying method for wafer after BGA package is completed |
| CN106531689A (en) * | 2015-09-15 | 2017-03-22 | 上海微世半导体有限公司 | Production method and equipment for back-surface cutting counterpoint line of glass passivation silicon wafer |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118657112A (en) * | 2024-08-16 | 2024-09-17 | 苏州亿麦矽半导体技术有限公司 | A wiring adjustment method and device |
| CN118657112B (en) * | 2024-08-16 | 2024-11-08 | 苏州亿麦矽半导体技术有限公司 | A wiring adjustment method and device |
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Application publication date: 20200508 |