CN111105761A - Display panel, control method thereof and display device - Google Patents
Display panel, control method thereof and display device Download PDFInfo
- Publication number
- CN111105761A CN111105761A CN201811265810.4A CN201811265810A CN111105761A CN 111105761 A CN111105761 A CN 111105761A CN 201811265810 A CN201811265810 A CN 201811265810A CN 111105761 A CN111105761 A CN 111105761A
- Authority
- CN
- China
- Prior art keywords
- sub
- pixel units
- pixel
- data signals
- row
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The disclosure relates to a display panel, a control method thereof and a display device, and belongs to the technical field of displays. The display panel includes: a plurality of pixel units arranged in an array, each pixel unit including a plurality of sub-pixel units; a plurality of gate lines and a plurality of data lines; the driving circuit is used for loading data signals to all pixel units in the Nth row at the same time when the Nth grid line loads the grid conduction state, loading the data signals to all pixel units in the (N + 1) th row at the same time when the (N + 1) th grid line loads the grid conduction state, and sequentially loading the data signals to a plurality of sub-pixel units in each pixel unit; in any column of pixel units, the sub-pixel unit which loads the data signal last in the pixel units in the Nth row and the sub-pixel unit which loads the data signal first in the pixel units in the (N + 1) th row are connected with the same data line and load the data signals continuously, N and K are integers, K is more than N and more than 0, and K is the row number of the pixel units.
Description
Technical Field
The disclosure relates to the technical field of displays, and in particular to a display panel, a control method thereof and a display device.
Background
The display panel is an important component of the display. The display panel generally includes a plurality of pixel units arranged in an array, each pixel unit including a plurality of sub-pixel units, for example, three sub-pixel units of Red (R), Green (G), and Blue (B). Each row of sub-pixel units is controlled to be turned on or turned off through one grid line, and each column of sub-pixel units are written with data signals through one data line when being turned on.
The data signal written through the data line is provided by a source driver Integrated Circuit (IC) of the liquid crystal display. In order to simplify the transmission channel between the data line and the source drive IC, the source drive IC multiplexes the data signals of three data lines corresponding to one column of pixels into one path of drive signal for transmission. And the driving circuit is arranged between the source driving IC and the data lines, receives the driving signals output by the source driving IC, converts the driving signals into data signals of the three data lines, and then sequentially outputs the data signals to the three data lines in a time-sharing manner.
The drive circuit outputs data signals of three data lines, and a gap time is reserved between the high level and the grid conducting level of the data signals to ensure that the data signals are loaded to the data lines after the level of the grid lines reaches the grid conducting level. Meanwhile, interval time is reserved between high levels of data signals output to the three data lines by the driving circuit. These intervals result in a long scanning time for one frame of picture, which is not favorable for the application of the technology to a large-sized high-refresh-rate display screen or touch screen.
Disclosure of Invention
The present disclosure provides a display panel, a control method thereof, and a display device, which save signal loading time, so that the technology can be applied to a large-sized high refresh rate display screen or a touch screen.
According to a first aspect of embodiments of the present disclosure, there is provided a display panel including: a plurality of pixel units arranged in an array, each of the pixel units including a plurality of sub-pixel units; each grid line in the grid lines is respectively connected with all the sub-pixel units in a unique row of the pixel units, each data line in the data lines is respectively connected with a unique column of the pixel units, and each data line is connected with one sub-pixel unit in each row of the pixel units; the driving circuit is used for loading data signals to all the pixel units in the Nth row at the same time when the loading grid of the Nth grid line is on, and loading the data signals to a plurality of sub-pixel units in each pixel unit in sequence; when the (N + 1) th grid line loads a grid electrode conduction level, loading data signals to all the pixel units in the (N + 1) th row at the same time, and sequentially loading the data signals to a plurality of sub-pixel units in each pixel unit; in any column of the pixel units, a first sub-pixel unit which is located in the nth row and loads a data signal last in the pixel units and a second sub-pixel unit which is located in the N +1 th row and loads a data signal first in the pixel units are connected with the same data line, the first sub-pixel unit and the second sub-pixel unit load data signals continuously, N and K are integers, K is greater than N and greater than 0, and K is the row number of the pixel units.
In the disclosure, the signal loading of the sub-pixel units of the display panel is controlled by the driving circuit, when the N-th grid line loads the grid on state, the data signals are simultaneously loaded to all the pixel units in the N-th row, and the data signals are sequentially loaded to the plurality of sub-pixel units in each pixel unit; when the (N + 1) th grid line loads a grid electrode conduction level, simultaneously loading data signals to all pixel units in the (N + 1) th row, and sequentially loading the data signals to a plurality of sub-pixel units in each pixel unit; in addition, in a row of pixel units, the sub-pixel unit which loads the data signal last in the Nth row and the sub-pixel unit which loads the data signal first in the (N + 1) th row are connected with the same data line, and the two sub-pixel units continuously load the data signal, so that the interval time is not required to be reserved between the two sub-pixel units, so that the signal loading time is saved by the mode, the scanning time of a frame of picture is further shortened, and the technology can be applied to a large-size high-refresh-rate display screen; and, since the scanning time becomes short, the time that can be allocated to the touch is greatly increased, which is advantageous for the application of the technology to the touch screen.
In one implementation manner of the present disclosure, in any column of the pixel units, the sub-pixel unit located in the nth row and the (N + 2) th row, where the data signal is loaded first, is connected to the same data line, and the sub-pixel unit where the data signal is loaded last is connected to the same data line.
In this implementation, in a column of pixel units, the sub-pixel unit which loads the data signal first and the sub-pixel unit which loads the data signal last in each row are connected to two data lines, which facilitates control of the data signal loading timing.
In one implementation manner of the present disclosure, in any column of the pixel units, the driving circuit is configured to control an order of loading data signals to the plurality of sub-pixel units located in the nth row when the nth gate line is loaded with the gate-on state to be opposite to an order of loading data signals to the plurality of sub-pixel units located in the N +1 th row when the N +1 th gate line is loaded with the gate-on state.
In this implementation, the order of sequentially loading the data signals to the plurality of sub-pixel units in the nth row and the (N + 1) th row is reversed, which facilitates control of the data signal loading timing.
In one implementation manner of the present disclosure, each of the pixel units includes a red sub-pixel unit, a green sub-pixel unit, and a blue sub-pixel unit, and the sub-pixel units connected to the same data line are sub-pixel units of the same color;
the driving circuit is used for loading data signals to the plurality of sub-pixel units positioned on the Nth row in the following sequence: the pixel structure comprises a red sub-pixel unit, a green sub-pixel unit and a blue sub-pixel unit;
the driving circuit is used for loading data signals to the plurality of sub-pixel units positioned on the (N + 1) th row in the following sequence: the pixel structure comprises a blue sub-pixel unit, a green sub-pixel unit and a red sub-pixel unit.
In this implementation, the pixel units are designed as the most common RGB sub-pixel units, and two rows of pixel units are loaded in the order of RGB and BGR, respectively, which facilitates control of the data signal loading timing sequence.
In one implementation manner of the present disclosure, the driving circuit sequentially loads the data signals to the plurality of sub-pixel units in the pixel units located in the odd-numbered columns in the same order as the arrangement order of the plurality of sub-pixel units in the pixel units located in the odd-numbered columns; the driving circuit loads data signals to a plurality of sub-pixel units in the pixel units in even columns in sequence, and the sequence of the data signals is opposite to the arrangement sequence of the sub-pixel units in the pixel units in even columns;
or the driving circuit loads data signals to the plurality of sub-pixel units in the odd columns in sequence, wherein the sequence of the data signals is opposite to the arrangement sequence of the plurality of sub-pixel units in the odd columns; the driving circuit loads the data signals to the plurality of sub-pixel units in the even columns in sequence, and the sequence of the data signals is the same as the arrangement sequence of the plurality of sub-pixel units in the even columns.
In this implementation manner, the arrangement order of the sub-pixel units is the same as or opposite to the order in which the sub-pixel units load the data signals, so that the working order of the sub-pixel units is the same as or opposite to the arrangement order, on one hand, the time sequence is convenient to design, and on the other hand, the display effect is better.
In one implementation manner of the present disclosure, the driving circuit includes a control sub-circuit and a plurality of switches, one of the switches is disposed at an input end of each of the data lines; the switches are divided into a plurality of groups, and a data line corresponding to each group of switches is connected with one output channel of the driving integrated circuit; the control sub-circuit is used for controlling each switch in a group of switches to be sequentially opened and closed, and loading a data signal output by one output channel of the driving integrated circuit to a group of data lines corresponding to the switches in a time-sharing manner.
In the implementation mode, the connection and disconnection between the output channel of the driving integrated circuit and the data line are controlled through the switch to control the loading of the data signal, the driving circuit is convenient in structure, and the control method is simple.
According to a second aspect of the embodiments of the present disclosure, there is provided a display panel control method adapted to control the display panel according to the first aspect, the method including: loading a grid conducting level to each grid line in sequence according to the arrangement sequence of the grid lines; when the loading grid of the Nth grid line is electrified, loading data signals to all the pixel units on the Nth row at the same time, and sequentially loading the data signals to a plurality of sub-pixel units in each pixel unit; when the (N + 1) th grid line loads a grid electrode conduction level, loading data signals to all the pixel units in the (N + 1) th row at the same time, and sequentially loading the data signals to a plurality of sub-pixel units in each pixel unit; in any column of the pixel units, a first sub-pixel unit which is located in the pixel unit of the Nth row and is loaded with a data signal last and a second sub-pixel unit which is located in the pixel unit of the (N + 1) th row and is loaded with a data signal first are connected with the same data line, the first sub-pixel unit and the second sub-pixel unit are loaded with data signals continuously, N and K are integers, K is more than N and more than 0, and K is the row number of the pixel units.
In one implementation manner of the present disclosure, in any column of the pixel units, the sub-pixel unit located in the nth row and the (N + 2) th row, where the data signal is loaded first, is connected to the same data line, and the sub-pixel unit where the data signal is loaded last is connected to the same data line.
In one implementation manner of the present disclosure, when the nth gate line loads a gate on state, data signals are simultaneously loaded to all the pixel units in the nth row, and a plurality of sub-pixel units in each pixel unit load data signals in sequence; when the (N + 1) th grid line loads the grid on-state, load the data signal to all the pixel units in the (N + 1) th row at the same time, and a plurality of sub-pixel units in each pixel unit load the data signal in proper order, including: in any column of the pixel units, the order of loading the data signals to the plurality of sub-pixel units in the nth row when the nth gate line is loaded with the gate-on state is controlled to be opposite to the order of loading the data signals to the plurality of sub-pixel units in the (N + 1) th row when the (N + 1) th gate line is loaded with the gate-on state.
In one implementation of the present disclosure, each of the pixel units includes a red sub-pixel unit, a green sub-pixel unit, and a blue sub-pixel unit, and the sub-pixel units connected to the same data line are sub-pixel units of the same color, and the controlling loads data signals to the plurality of sub-pixel units in the nth row in a sequence opposite to a sequence of loading data signals to the plurality of sub-pixel units in the N +1 th row in a sequence when the nth gate line loads a gate on state includes: the sequence of loading the data signals to the plurality of sub-pixel units positioned on the Nth row is as follows: the pixel structure comprises a red sub-pixel unit, a green sub-pixel unit and a blue sub-pixel unit; the sequence of loading the data signals to the plurality of sub-pixel units positioned on the N +1 th row is as follows: the pixel structure comprises a blue sub-pixel unit, a green sub-pixel unit and a red sub-pixel unit.
In one implementation manner of the present disclosure, an order in which the plurality of sub-pixel units in the pixel units located in the odd-numbered columns sequentially load the data signals is the same as an arrangement order of the plurality of sub-pixel units in the pixel units located in the odd-numbered columns; the sequence of loading the data signals in sequence by the plurality of sub-pixel units in the pixel units positioned in the even columns is opposite to the arrangement sequence of the plurality of sub-pixel units in the pixel units positioned in the even columns; or the sequence of loading the data signals in sequence by the plurality of sub-pixel units in the odd columns is opposite to the arrangement sequence of the plurality of sub-pixel units in the odd columns; the driving circuit loads the data signals to the plurality of sub-pixel units in the even columns in sequence, and the sequence of the data signals is the same as the arrangement sequence of the plurality of sub-pixel units in the even columns.
According to a third aspect of embodiments of the present disclosure, there is provided a display device including the display panel according to any one of the first aspect.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.
Fig. 1 is a schematic structural view of a display panel in the related art;
FIG. 2 is a control timing diagram of a display panel according to the related art;
FIG. 3 is a schematic diagram illustrating a structure of a display panel according to an exemplary embodiment;
FIG. 4 is a control timing diagram shown in accordance with an exemplary embodiment;
fig. 5 is a flowchart illustrating a display panel control method according to an exemplary embodiment.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the exemplary embodiments below are not intended to represent all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.
For ease of understanding, the control of the display panel in the related art will be briefly described below.
Fig. 1 is a schematic structural diagram of a display panel in the related art. As shown in fig. 1, the display panel includes a plurality of pixel units arranged in an array, and one dotted line frame in fig. 1 indicates one pixel unit. Each pixel cell typically includes three or four sub-pixel cells, and the distribution of sub-pixel cells shown in fig. 1 is merely an example. Referring to fig. 1, each pixel unit includes R, G, B three sub-pixel units, and R, G, B sub-pixel units are arranged in sequence in each row. Each row of sub-pixel units controls the switch through one gate line (G1, G2 in the figure), for example, in fig. 1, the sub-pixel unit in the first row controls the switch of each sub-pixel unit through the gate line G1, and the sub-pixel unit in the second row controls the switch of each sub-pixel unit through the gate line G2. Specifically, the gate driving IC applies a gate-on level to the gates of the thin film transistors of a row of sub-pixel units through the gate lines, so that the thin film transistors of a row of sub-pixel units are turned on, that is, the sub-pixel units are turned on. The gate-on level is a level signal for controlling the thin film transistor to be turned on, and the level signal may be a high level signal or a low level signal according to the type of the thin film transistor. Each column of sub-pixel units is loaded with data signals through one data line (L1-L6 in the figure), for example, in fig. 1, the sub-pixel unit in the first column is loaded with data signals to each sub-pixel unit through the data line L1, the sub-pixel unit in the second column is loaded with data signals to each sub-pixel unit through the data line L2, and so on. The data signal refers to a signal for controlling the luminance of the sub-pixel unit.
The data signals of the sub-pixel units are provided by the source drive ICs. As shown in fig. 1, one source line S1 of the source drive IC connects three data lines L1, L3, and L5, and the other source line S2 of the source drive IC connects three data lines L2, L4, and L6. Switches are arranged at the connection of the data lines and the source lines, for example, in fig. 1, switches SW1, SW3 and SW5 are respectively arranged at the connection of the data lines L1, L3 and L5 and the source line S1, switches SW2, SW4 and SW6 are respectively arranged at the connection of the data lines L2, L4 and L6 and the source line S2, and the source lines are controlled to sequentially output data signals to the corresponding three data lines by controlling the turn-on sequence of the switches.
In order to avoid the solidification of the liquid crystal characteristics, the liquid crystal driving needs to use an ac voltage, so the display panel usually adopts a polarity inversion design. Taking column inversion (the polarities of the data signals in adjacent columns are opposite) as an example, in the display panel shown in fig. 1, one data line connected to another source line is arranged between two adjacent data lines among three data lines connected to each source line at an interval, so that the polarities of the data signals in the three data lines connected to each source line are the same, and the column inversion design of the display panel is realized.
Fig. 2 is a control timing diagram of the display panel shown in fig. 1, wherein G1 and G2 are signals loaded on gate lines G1 and G2, respectively, in fig. 1, and R, G and B are data signals loaded on L1, L2 and L3, respectively, in fig. 1. In the initial state, SW 1-SW 6 are all turned off. With reference to fig. 1 and 2, when G1 loads a gate-on level (e.g., a high level in fig. 2), SW1 and SW4 are first controlled to be turned on, and data signals on S1 and S2 are output to R sub-pixel cells in the first row of sub-pixel cells through L1 and L4, respectively; then controlling the SW1 and the SW4 to be switched off, the SW2 and the SW5 to be switched on, and the data signals on the S1 and the S2 to be output to the G sub-pixel units in the first row of sub-pixel units through the L2 and the L5 respectively; and then controlling the SW2 and the SW5 to be switched off, the SW3 and the SW6 to be switched on, and the data signals on the S1 and the S2 to be output to the B sub-pixel units in the first row of sub-pixel units through the L3 and the L6 respectively. When the gate-on level is loaded by G2, data signals are sequentially output to R, G, B sub-pixel units in the second row in the same manner as in the first row, so that the R sub-pixel units, the G sub-pixel units and the B sub-pixel units in the second row are controlled to sequentially operate.
Since a change process is required when the level rises and falls without an instantaneous change, that is, without an abrupt change at a certain time as in fig. 2, an interval time is reserved between the high level of the data signal and the gate-on level in order to avoid loading the data line with the data signal before the level of the gate line reaches the gate-on level. Meanwhile, since there is a delay in switching the data lines to which the data signals are applied by the switches (SW1 to SW6), an interval time is also reserved between high levels of the data signals applied to the R, G, and B sub-pixel cells by the source drive IC. As shown in fig. 2, the reserved interval times t1, t7 and t8 between the high level of the data signal and the gate-on level, and the reserved interval times t3 and t5 between the high level of the data signal, which results in a longer scanning time of one frame of picture, are not favorable for the application of the technology to a large-size high-refresh-rate display screen; and because the scanning time is long, the time that can be allocated to touching is greatly reduced, which is not beneficial to applying the technology to the touch screen.
The present disclosure provides a display panel, a control method thereof, and a display device, which save signal loading time, so that the technology can be applied to a large-sized high refresh rate display screen or touch screen.
Fig. 3 is a schematic structural diagram illustrating a display panel according to an exemplary embodiment, and as shown in fig. 3, the display panel includes a plurality of pixel units 101 arranged in an array, and each pixel unit 101 includes a plurality of sub-pixel units 102. The number of pixel cells 101 and the number of sub-pixel cells 102 in each pixel cell 101 in fig. 3 are examples and are not intended to be a limitation of the present disclosure.
The display panel further comprises a plurality of gate lines 103 and a plurality of data lines 104, wherein each gate line 103 of the plurality of gate lines 103 is respectively connected with all the sub-pixel units 102 of a unique row of pixel units, each data line 104 of the plurality of data lines 104 is respectively connected with a unique column of pixel units 101, and each data line 104 is connected with one sub-pixel unit 102 of each row of pixel units 101. As shown in fig. 3, a row of pixel units 101 includes only one row of sub-pixel units 102, and each row of pixel units 101 controls on or off of all sub-pixel units 102 in the row through one gate line 103. Each column of pixel units 101 includes three columns of sub-pixel units 102, and each column of pixel units 101 writes data signals through three data lines 104 when the sub-pixel units 102 are turned on. As shown in fig. 3, a plurality of gate lines 103 are disposed in parallel at intervals, and the length direction of the gate lines 103 is arranged in the row direction. The plurality of data lines 104 are disposed in parallel at intervals, and the length direction of the data lines 104 is arranged in the column direction.
The display panel further includes a driving circuit 105, wherein the driving circuit 105 is configured to load data signals to all pixel units 101 in the nth row at the same time when the nth gate line 103 is loaded with the gate-on level, and the plurality of sub-pixel units 102 in each pixel unit 101 are sequentially loaded with the data signals. When the (N + 1) th gate line 103 is loaded with the gate-on level, all the pixel units 101 in the (N + 1) th row are simultaneously loaded with the data signals, and the plurality of sub-pixel units 102 in each pixel unit 101 are sequentially loaded with the data signals. Wherein the data signal may be provided by the source drive IC.
In any column of pixel units 101, a first sub-pixel unit which loads a data signal last in the pixel units 101 in the nth row and a second sub-pixel unit which loads a data signal first in the pixel units 101 in the (N + 1) th row are connected to the same data line 104, the first sub-pixel unit and the second sub-pixel unit load data signals continuously, N and K are integers, K > N > 0, and K is the row number of the pixel units.
The voltages of the data signal loaded by the first sub-pixel unit in the nth row of pixel units 101 and the data signal loaded by the second sub-pixel unit in the (N + 1) th row of pixel units 101 may be the same or different.
In the disclosure, the signal loading of the sub-pixel units of the display panel is controlled by the driving circuit, when the N-th grid line loads the grid on state, the data signals are simultaneously loaded to all the pixel units in the N-th row, and the data signals are sequentially loaded to the plurality of sub-pixel units in each pixel unit; when the (N + 1) th grid line loads a grid electrode conduction level, simultaneously loading data signals to all pixel units in the (N + 1) th row, and sequentially loading the data signals to a plurality of sub-pixel units in each pixel unit; in addition, in a row of pixel units, the sub-pixel unit which loads the data signal last in the Nth row and the sub-pixel unit which loads the data signal first in the (N + 1) th row are connected with the same data line, and the two sub-pixel units continuously load the data signal, so that the interval time is not required to be reserved between the two sub-pixel units, so that the signal loading time is saved by the mode, the scanning time of a frame of picture is further shortened, and the technology can be applied to a large-size high-refresh-rate display screen; and, since the scanning time becomes short, the time that can be allocated to the touch is greatly increased, which is advantageous for the application of the technology to the touch screen.
Each sub-pixel unit 102 includes a thin film transistor, the gate line 103 is connected to a gate of the thin film transistor, and controls the sub-pixel unit 102 to be turned on or off by controlling on or off of the thin film transistor, and the data line 104 is connected to a source of the thin film transistor, and a data signal is written through the source of the thin film transistor.
In the embodiment of the present disclosure, each pixel unit 101 includes the same number and color of the sub-pixel units 102 (sub-pixel unit emitting color), and the sub-pixel units 102 of the same kind in different pixel units 101 emit light at the same time.
Since the circuit of a Liquid Crystal Display (LCD) may adopt the structure shown in fig. 3, the scheme of the Display panel provided by the embodiment of the present disclosure may be applied to an LCD. Of course, the embodiments of the present disclosure also do not limit the scheme of using the display panel provided by the embodiments of the present disclosure for other types of displays, such as Organic Light Emitting Diode (OLED) displays.
In the embodiment of the present disclosure, in any column of pixel units 101, the sub-pixel unit 102 which is located in the nth row and the (N + 2) th row and is loaded with the data signal first is connected to the same data line 104, and the sub-pixel unit 102 which is loaded with the data signal last is connected to the same data line 104.
In this implementation, for any column of pixel units 101, it is defined that not only the sub-pixel unit 102 which loads the data signal last in the nth row and the sub-pixel unit 102 which loads the data signal first in the N +1 th row in the two adjacent rows are connected to the same data line 104, but also the sub-pixel unit 102 which loads the data signal first in the nth row and the N +2 th row is connected to the same data line 104, and the sub-pixel unit 102 which loads the data signal last is connected to the same data line 104. This allows the sub-pixel unit 102 to which the data signal is first loaded and the sub-pixel unit 104 to which the data signal is last loaded in each row to be connected to two data lines 104, which is designed to facilitate the control of the data signal loading timing.
According to the above implementation manner, for any column of pixel units 101, the sub-pixel unit 102 which loads the data signal first in the odd-numbered row is connected to the same data line 104, and the sub-pixel unit 102 which loads the data signal last in the odd-numbered row is connected to the same data line 104; the sub-pixel unit 102 which loads the data signal first in the even-numbered row is connected to the same data line 104, and the sub-pixel unit 102 which loads the data signal last in the even-numbered row is connected to the same data line 104. In other implementation manners, only the sub-pixel unit 102 that is loaded with the data signal last in the nth row and the sub-pixel unit 102 that is loaded with the data signal first in the (N + 1) th row may be limited to be connected to the same data line 104, without limiting the positional relationship between the nth row and the (N + 2) th row.
In any column of pixel units 101 in the disclosed embodiment, the driving circuit 105 is used to control the order of loading data signals to the plurality of sub-pixel units 102 in the nth row when the nth gate line 103 is loaded with the gate-on state, and the order of loading data signals to the plurality of sub-pixel units 102 in the (N + 1) th row when the (N + 1) th gate line 103 is loaded with the gate-on state. For example, referring to fig. 3, the data signals are sequentially loaded to the plurality of sub-pixel units 102 in the pixel unit 101 in the first row by RBG, that is, the data signals are loaded to all R sub-pixel units first, then the data signals are loaded to all B sub-pixel units, and finally the data signals are loaded to all G sub-pixel units; the order of loading the data signals to the plurality of sub-pixel units 102 in the pixel unit 101 in the second row is GBR.
In this implementation manner, the sequence of sequentially loading the data signals to the plurality of sub-pixel units in the nth row and the (N + 1) th row is opposite, so that the on and off sequence of each switch is conveniently controlled, and the control of the data signal loading timing sequence is convenient.
In other embodiments, the order in which the driving circuit 105 controls the N-th row and the N + 1-th row to sequentially load the data signals to the plurality of sub-pixel units 102 may not be the same. For example, referring to fig. 3, the order in which the plurality of sub-pixel units 102 in the pixel unit 101 located in the first row are loaded with the data signals is RBG in sequence, and the order in which the plurality of sub-pixel units 102 in the pixel unit 101 located in the second row are loaded with the data signals is GRB in sequence.
As shown in fig. 3, each pixel unit 102 includes an R sub-pixel unit, a G sub-pixel unit, and a B sub-pixel unit, and the sub-pixel units 102 connected to the same data line 104 are sub-pixel units 102 of the same color. The driving circuit 105 sequentially loads the data signals to the sub-pixel units 102 in the nth row in the following order: the pixel comprises an R sub-pixel unit, a G sub-pixel unit and a B sub-pixel unit; the driving circuit 105 sequentially loads the data signals to the sub-pixel units 102 located in the (N + 1) th row in the following order: the pixel structure comprises a B sub-pixel unit, a G sub-pixel unit and an R sub-pixel unit.
In this implementation, the pixel units are designed as the most common RGB sub-pixel units, and two rows of pixel units are loaded in the order of RGB and BGR, respectively, which facilitates control of the data signal loading timing sequence.
Wherein the sub-pixel units 102 of the same color in any row are loaded with data signals at the same time.
The structure of the pixel unit 102 shown in fig. 3 is a conventional RGB design, and in the pixel unit 102, an R sub-pixel unit, a G sub-pixel unit, and a B sub-pixel unit are sequentially arranged. In other embodiments, the RGB sub-pixel units in the pixel unit 102 may also be arranged in other manners, for example, the R sub-pixel unit, the B sub-pixel unit, and the G sub-pixel unit are arranged in sequence, and in this case, the sequence of the data signals may also be RBG and GBR. In other embodiments, the pixel unit 102 may further include 4 sub-pixel units, for example, the pixel unit 102 includes two R sub-pixel units, a G sub-pixel unit, and a B sub-pixel unit, and the order of the data signals may also be RRGB and BGRR.
The driving scheme of the driving circuit 105 will be described below with reference to the drawings. FIG. 4 is a control timing diagram shown in accordance with an exemplary embodiment. Referring to fig. 4, when the gate line G1 is loaded with a gate-on level (a segment in fig. 4), data signals are sequentially output to R, G, B sub-pixel cells located in the first row; when the gate line G2 is loaded with a gate-on level (b segment in fig. 4), data signals are sequentially output to the B, G, R sub-pixel cells positioned at the second row. Since in this scheme, the data signals of the first row B of sub-pixel units and the second row B of sub-pixel units are loaded continuously, i.e. there is no need to switch the data lines of the source line connections through switches, there is no delay time between them, so this way saves signal loading time. Compared with fig. 1, the delay time of t7(0.25 microsecond) and t8(0.25 microsecond) is reduced, and the saved time can be used as the display or touch time, so that the scheme can meet the requirements of a touch screen with a high refresh rate and a high touch report rate, for example, the scheme can be applied to a touch screen with a refresh rate of 120Hz (120 frames per second) +120Hz touch report rate (120 touch signals per second).
In the embodiment of the present disclosure, the order in which the driving circuit 105 sequentially loads the data signals to the plurality of sub-pixel units 102 in the pixel units 101 located in the odd columns is the same as the arrangement order of the plurality of sub-pixel units 102 in the pixel units 101 located in the odd columns; the driving circuit 105 sequentially loads the data signals to the plurality of sub-pixel units 102 in the pixel units 101 located in the even columns in the order opposite to the arrangement order of the plurality of sub-pixel units 102 in the pixel units 101 located in the even columns.
Alternatively, the driving circuit 105 sequentially loads the data signals to the plurality of sub-pixel units 102 in the pixel units 101 in the odd columns in the order opposite to the arrangement order of the plurality of sub-pixel units 102 in the pixel units 101 in the odd columns; the driving circuit 105 sequentially loads the data signals to the plurality of sub-pixel units 102 in the pixel units 101 located in the even columns in the same order as the arrangement order of the plurality of sub-pixel units 102 in the pixel units 101 located in the even columns.
The sequence of loading the data signals by the sub-pixel units 102 in all the pixel units 101 in any row is the same.
As shown in fig. 3, the sequence of the sub-pixel units 102 from left to right in one pixel unit 101 is RGB, and the sequence of the data signals sequentially loaded by the sub-pixel units 102 in the pixel unit 101 in the first row is also RGB, which is the same as the sequence of the sub-pixel units 102. The sequence of sequentially loading the data signals to the plurality of sub-pixel units 102 in the pixel unit 101 in the second row is BGR, which is opposite to the sequence of the sub-pixel units 102.
In this implementation manner, the arrangement sequence of the sub-pixel units is the same as the sequence of the sub-pixel units for loading the data signals, so that the working sequence and the arrangement sequence of the sub-pixel units are the same, on one hand, the time sequence is convenient to design, and on the other hand, the display effect is better.
In other embodiments, the arrangement order of the plurality of sub-pixel units 102 in the pixel unit 101 in each row is different from and not opposite to the order in which the driving circuit 105 sequentially loads the data signals to the plurality of sub-pixel units 102 in the pixel unit, for example, the order of the sub-pixel units 102 from left to right in one pixel unit 101 is RGB, the order in which the plurality of sub-pixel units 102 in the pixel unit 101 in the first row are GRB, and the order in which the plurality of sub-pixel units 102 in the pixel unit 101 in the second row are BRG.
As shown in fig. 3, the driving circuit 105 includes a plurality of switches 106 and a control sub-circuit 107, and one switch 106 is provided at an input terminal of each data line 104. The on-off of the switch 106 is controlled by the control sub-circuit 107, so that the data line 104 to which the data signal is loaded is controlled, and in any column of pixel units, the loading of the data signal by the first sub-pixel unit in the nth row of pixel units and the loading of the data signal by the second sub-pixel unit in the (N + 1) th row of pixel units are performed continuously, so that the control switch is not required to perform switching, and the reserved interval time is not required.
The switches 106 are divided into a plurality of groups, and the data line 104 corresponding to each group of switches 106 is connected with one output channel of the driving integrated circuit.
The control sub-circuit 107 is configured to control each switch 106 in the group of switches 106 to be sequentially turned on and off, and time-share and load the data signal output by one output channel of the driving integrated circuit onto the data line 104 corresponding to the group of switches 106.
In the implementation mode, the connection and disconnection between the output channel of the driving integrated circuit and the data line are controlled through the switch to control the loading of the data signal, the driving circuit is convenient in structure, and the control method is simple.
As shown in fig. 3, the switches SW1, SW3 and SW5 are grouped, the switches SW2, SW4 and SW6 are grouped, one output channel of the driving integrated circuit loads data signals to the data lines L1, L3 and L5 through the source line S1, and the other output channel of the driving integrated circuit loads data signals to the data lines L2, L4 and L6 through the source line S2.
In the driving circuit 105, the control sub-circuit 107 includes a plurality of control terminals, and the plurality of switches 106 on the data lines of the sub-pixel units 102 of the same color are connected to the same control terminal.
In the embodiment of the present disclosure, the control sub-circuit 107 outputs control signals through the plurality of control terminals in sequence according to a predetermined sequence, and controls the switches connected to the plurality of control terminals to be turned on. Here, the predetermined sequence is designed according to the sequence that the signals output by the source driving IC need to be loaded to each sub-pixel unit, for example, when the signals output by the source driving IC need to be loaded to RGB sub-pixel units respectively in sequence, the predetermined sequence is that the control terminals in sequence output control signals to the switches of the corresponding columns of RGB sub-pixel units.
In the disclosed embodiment, the switch 106 may be implemented using a data selector (MUX).
In the disclosed embodiment, the switch 106 is integrated on the substrate. The control sub-circuit 107 may be integrated on the substrate or on the source driver IC, and the control sub-circuit 107 may also be implemented by a separate IC.
Fig. 5 is a flowchart illustrating a display panel control method according to an exemplary embodiment, where the display panel is as described above, and the method includes:
in step S201, a gate-on level is sequentially applied to each gate line according to an arrangement order of the plurality of gate lines.
As shown in fig. 3 and 4, the gate line G1 is first applied with a gate-on level (segment a in fig. 4) and then the gate line G2 is applied with a gate-on level (segment b in fig. 4) in the order of the arrangement of the gate lines.
In step S202, when the nth gate line loads the gate-on level, data signals are simultaneously loaded to all the pixel units in the nth row, and the plurality of sub-pixel units in each pixel unit load the data signals in sequence; when the (N + 1) th grid line loads a grid electrode conduction level, data signals are loaded to all the pixel units in the (N + 1) th row at the same time, and a plurality of sub-pixel units in each pixel unit are sequentially loaded with the data signals. In any column of pixel units, a first sub-pixel unit which is located in the pixel unit of the Nth row and is loaded with a data signal last and a second sub-pixel unit which is located in the pixel unit of the (N + 1) th row and is loaded with a data signal first are connected with the same data line, the first sub-pixel unit and the second sub-pixel unit are loaded with data signals continuously, N and K are integers, K is greater than N and greater than 0, and K is the row number of the pixel units.
The voltages of the data signals loaded by the first sub-pixel units in the nth row of pixel units and the voltages of the data signals loaded by the second sub-pixel units in the (N + 1) th row of pixel units may be the same or different.
In the disclosure, the signal loading of the sub-pixel units of the display panel is controlled by the driving circuit, when the N-th grid line loads the grid on state, the data signals are simultaneously loaded to all the pixel units in the N-th row, and the data signals are sequentially loaded to the plurality of sub-pixel units in each pixel unit; when the (N + 1) th grid line loads a grid electrode conduction level, simultaneously loading data signals to all pixel units in the (N + 1) th row, and sequentially loading the data signals to a plurality of sub-pixel units in each pixel unit; in addition, in a row of pixel units, the sub-pixel unit which loads the data signal last in the Nth row and the sub-pixel unit which loads the data signal first in the (N + 1) th row are connected with the same data line, and the two sub-pixel units continuously load the data signal, so that the interval time is not required to be reserved between the two sub-pixel units, so that the signal loading time is saved by the mode, the scanning time of a frame of picture is further shortened, and the technology can be applied to a large-size high-refresh-rate display screen; and, since the scanning time becomes short, the time that can be allocated to the touch is greatly increased, which is advantageous for the application of the technology to the touch screen.
In the embodiment of the present disclosure, in any column of pixel units, the sub-pixel unit which is located in the nth row and the (N + 2) th row and is loaded with the data signal first is connected to the same data line, and the sub-pixel unit which is loaded with the data signal last is connected to the same data line.
In this implementation manner, for any column of pixel units, it is defined that not only the sub-pixel unit which loads the data signal last in the nth row and the sub-pixel unit which loads the data signal first in the N +1 th row in the adjacent two rows are connected to the same data line, but also the sub-pixel unit which loads the data signal first in the nth row and the N +2 th row is connected to the same data line, and the sub-pixel unit which loads the data signal last is connected to the same data line. Therefore, the sub-pixel unit which loads the data signal firstly and the sub-pixel unit which loads the data signal finally in each row are connected to the two data lines, and the design is convenient for controlling the loading time sequence of the data signal.
According to the implementation mode, for any column of pixel units, the sub-pixel unit which loads the data signal firstly in the odd-numbered row is connected with the same data line, and the sub-pixel unit which loads the data signal finally in the odd-numbered row is connected with the same data line; the sub-pixel units which load the data signals firstly in the even-numbered rows are connected with the same data line, and the sub-pixel units which load the data signals finally in the even-numbered rows are connected with the same data line. In other implementation manners, only the sub-pixel unit which loads the data signal last in the nth row and the sub-pixel unit which loads the data signal first in the (N + 1) th row may be limited to be connected to the same data line, and the positional relationship between the nth row and the (N + 2) th row is not limited.
In the embodiment of the present disclosure, when the nth gate line loads the gate on state, the data signals are simultaneously loaded to all the pixel units in the nth row, and the data signals are sequentially loaded to the plurality of sub-pixel units in each pixel unit; when the (N + 1) th grid line loads the grid on level, load the data signal to all pixel units in the (N + 1) th row simultaneously, and a plurality of sub-pixel units in each pixel unit load the data signal in proper order, include:
in any column of pixel units, the sequence of loading data signals to the plurality of sub-pixel units positioned in the Nth row when the Nth grid line is loaded with grid conduction state is controlled to be opposite to the sequence of loading data signals to the plurality of sub-pixel units positioned in the (N + 1) th row when the (N + 1) th grid line is loaded with grid conduction state.
For example, referring to fig. 3, the order of loading the data signals to the plurality of sub-pixel units in the pixel unit in the first row is RBG, that is, the data signals are loaded to all R sub-pixel units first, then the data signals are loaded to all B sub-pixel units, and finally the data signals are loaded to all G sub-pixel units; the sequence of loading the data signals by the plurality of sub-pixel units in the pixel unit in the second row is GBR in sequence.
In this implementation manner, the sequence of sequentially loading the data signals to the plurality of sub-pixel units in the nth row and the (N + 1) th row is opposite, so that the on and off sequence of each switch is conveniently controlled, and the control of the data signal loading timing sequence is convenient.
In other embodiments, the order of sequentially loading the data signals to the plurality of sub-pixel units in the nth row and the N +1 th row may not be the same. For example, referring to fig. 3, the order in which the plurality of sub-pixel units load data signals in the pixel units located in the first row is RBG, and the order in which the plurality of sub-pixel units load data signals in the pixel units located in the second row is GRB.
In the embodiment of the present disclosure, each pixel unit includes a red sub-pixel unit, a green sub-pixel unit, and a blue sub-pixel unit, and the sub-pixel units connected to the same data line are sub-pixel units of the same color, and the order of loading data signals to the sub-pixel units in the nth row when the nth gate line is loaded with the gate-on voltage is controlled to be opposite to the order of loading data signals to the sub-pixel units in the N +1 th row when the N +1 th gate line is loaded with the gate-on voltage, including:
the sequence of loading the data signals to the plurality of sub-pixel units positioned on the Nth row is as follows: the pixel structure comprises a red sub-pixel unit, a green sub-pixel unit and a blue sub-pixel unit;
the sequence of loading the data signals to the plurality of sub-pixel units positioned in the (N + 1) th row is as follows: the pixel structure comprises a blue sub-pixel unit, a green sub-pixel unit and a red sub-pixel unit.
In this implementation, the pixel units are designed as the most common RGB sub-pixel units, and two rows of pixel units are loaded in the order of RGB and BGR, respectively, which facilitates control of the data signal loading timing sequence.
In the embodiment of the present disclosure, the order in which the plurality of sub-pixel units in the odd-numbered columns sequentially load the data signals is the same as the arrangement order of the plurality of sub-pixel units in the odd-numbered columns; the sequence of loading the data signals in sequence by the plurality of sub-pixel units in the even columns is opposite to the arrangement sequence of the plurality of sub-pixel units in the even columns.
Or the sequence of loading the data signals in turn by the plurality of sub-pixel units in the odd columns is opposite to the arrangement sequence of the plurality of sub-pixel units in the odd columns; the sequence of the driving circuit for sequentially loading the data signals to the plurality of sub-pixel units in the even columns is the same as the arrangement sequence of the plurality of sub-pixel units in the even columns.
As shown in fig. 3, the sequence of the sub-pixel units from left to right in one pixel unit is RGB, and the sequence of the data signals loaded by the sub-pixel units in the pixel unit in the first row is also RGB, which is the same as the sequence of the sub-pixel units. The sequence of sequentially loading the data signals by the plurality of sub-pixel units in the second row is BGR, and the sequence is opposite to that of the sub-pixel units.
In this implementation manner, the arrangement sequence of the sub-pixel units is the same as the sequence of the sub-pixel units for loading the data signals, so that the working sequence and the arrangement sequence of the sub-pixel units are the same, on one hand, the time sequence is convenient to design, and on the other hand, the display effect is better.
In other embodiments, the arrangement order of the plurality of sub-pixel units in the pixel units in each row is different from and not opposite to the order in which the driving circuit sequentially loads the data signals to the plurality of sub-pixel units in the pixel units, for example, the order of the sub-pixel units from left to right in one pixel unit is RGB sequentially, the order in which the plurality of sub-pixel units in the first row sequentially load the data signals is GRB, and the order in which the plurality of sub-pixel units in the second row sequentially load the data signals is BRG.
The embodiment of the disclosure also provides a display device, which includes the display panel. The display device may be a liquid crystal display.
Further, the display device further includes a source drive IC connected to the driving circuit of the display panel for supplying a data signal to the data line.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims (12)
1. A display panel, comprising:
a plurality of pixel units (101) arranged in an array, each of the pixel units (101) comprising a plurality of sub-pixel units (102);
a plurality of gate lines (103) and a plurality of data lines (104), wherein each gate line (103) of the plurality of gate lines (103) is respectively connected with all the sub-pixel units (102) of a unique row of the pixel units (101), each data line (104) of the plurality of data lines (104) is respectively connected with a unique column of the pixel units (101), and each data line (104) is connected with one sub-pixel unit (102) of each row of the pixel units (101);
a driving circuit (105), wherein the driving circuit (105) is used for loading data signals to all the pixel units (101) in the Nth row at the same time when the Nth grid line (103) loads a grid conduction level, and a plurality of sub-pixel units (102) in each pixel unit (101) are sequentially loaded with the data signals; when the gate-on level is loaded on the (N + 1) th grid line (103), data signals are loaded to all the pixel units (101) in the (N + 1) th row at the same time, and a plurality of sub-pixel units (102) in each pixel unit (101) are sequentially loaded with the data signals; in any column of the pixel units (101), a first sub-pixel unit which is located in the pixel unit (101) of the Nth row and is loaded with a data signal last and a second sub-pixel unit which is located in the pixel unit (101) of the (N + 1) th row and is loaded with a data signal first are connected with the same data line (104), the first sub-pixel unit and the second sub-pixel unit are loaded with data signals continuously, N and K are integers, K is greater than N and greater than 0, and K is the row number of the pixel unit (101).
2. The display panel according to claim 1, wherein in any column of the pixel units (101), the sub-pixel unit (102) loaded with the data signal first in the nth row and the N +2 th row is connected to the same data line (104), and the sub-pixel unit (102) loaded with the data signal last is connected to the same data line (104).
3. The display panel according to claim 2, wherein in any column of the pixel units (101), the driving circuit (105) is configured to control an order of loading data signals to the plurality of sub-pixel units (102) in the nth row when the nth gate line (103) is loaded with a gate-on state to be opposite to an order of loading data signals to the plurality of sub-pixel units (102) in the N +1 th row when the N +1 th gate line (103) is loaded with a gate-on state.
4. The display panel according to claim 3, wherein each of the pixel units (101) comprises a red sub-pixel unit, a green sub-pixel unit and a blue sub-pixel unit, and the sub-pixel units (102) connected to the same data line (104) are sub-pixel units (102) of the same color;
the driving circuit (105) is used for loading data signals to the plurality of sub-pixel units (102) positioned in the Nth row in the following sequence: the pixel structure comprises a red sub-pixel unit, a green sub-pixel unit and a blue sub-pixel unit;
the driving circuit (105) is used for loading data signals to the plurality of sub-pixel units (102) positioned in the (N + 1) th row in the following sequence: the pixel structure comprises a blue sub-pixel unit, a green sub-pixel unit and a red sub-pixel unit.
5. The display panel according to claim 3, wherein the driving circuit (105) sequentially loads the data signals to the plurality of sub-pixel units (102) in the pixel units (101) in the odd columns in the same order as the arrangement order of the plurality of sub-pixel units (102) in the pixel units (101) in the odd columns; the driving circuit (105) loads data signals to a plurality of sub-pixel units (102) in the pixel units (101) in even columns in sequence, and the sequence of the data signals is opposite to the arrangement sequence of the plurality of sub-pixel units (102) in the pixel units (101) in even columns;
or the driving circuit (105) loads the data signals to the plurality of sub-pixel units (102) in the pixel units (101) in the odd columns in sequence, and the sequence of the data signals is opposite to the arrangement sequence of the plurality of sub-pixel units (102) in the pixel units (101) in the odd columns; the sequence of sequentially loading the data signals to the plurality of sub-pixel units (102) in the pixel units (101) positioned in the even columns by the driving circuit (105) is the same as the arrangement sequence of the plurality of sub-pixel units (102) in the pixel units (101) positioned in the even columns.
6. A display panel as claimed in claim 1 characterized in that the driving circuit (105) comprises a plurality of switches (106) and control sub-circuits (107), one switch (106) being provided at the input of each data line (104);
the switches (106) are divided into a plurality of groups, and the data line (104) corresponding to each group of switches (106) is connected with one output channel of the driving integrated circuit;
the control sub-circuit (107) is used for controlling each switch (106) in a group of switches (106) to be sequentially opened and closed, and loading a data signal output by one output channel of the driving integrated circuit to a group of data lines (104) corresponding to the switches (106) in a time-sharing manner.
7. A display panel control method adapted to control the display panel according to claim 1, the method comprising:
loading a grid conducting level to each grid line in sequence according to the arrangement sequence of the grid lines;
when the loading grid of the Nth grid line is electrified, loading data signals to all the pixel units on the Nth row at the same time, and sequentially loading the data signals to a plurality of sub-pixel units in each pixel unit;
when the (N + 1) th grid line loads a grid electrode conduction level, loading data signals to all the pixel units in the (N + 1) th row at the same time, and sequentially loading the data signals to a plurality of sub-pixel units in each pixel unit;
in any column of the pixel units, a first sub-pixel unit which is located in the pixel unit of the Nth row and is loaded with a data signal last and a second sub-pixel unit which is located in the pixel unit of the (N + 1) th row and is loaded with a data signal first are connected with the same data line, the first sub-pixel unit and the second sub-pixel unit are loaded with data signals continuously, N and K are integers, K is more than N and more than 0, and K is the row number of the pixel units.
8. The method according to claim 7, wherein in any column of the pixel units, the sub-pixel unit which is loaded with the data signal first in the nth row and the (N + 2) th row is connected to the same data line, and the sub-pixel unit which is loaded with the data signal last is connected to the same data line.
9. The method according to claim 8, wherein when the nth gate line is loaded with the gate-on level, all the pixel units in the nth row are loaded with the data signals at the same time, and the plurality of sub-pixel units in each pixel unit are sequentially loaded with the data signals; when the (N + 1) th grid line loads the grid on-state, load the data signal to all the pixel units in the (N + 1) th row at the same time, and a plurality of sub-pixel units in each pixel unit load the data signal in proper order, including:
in any column of the pixel units, the order of loading the data signals to the plurality of sub-pixel units in the nth row when the nth gate line is loaded with the gate-on state is controlled to be opposite to the order of loading the data signals to the plurality of sub-pixel units in the (N + 1) th row when the (N + 1) th gate line is loaded with the gate-on state.
10. The method of claim 9, wherein each of the pixel units comprises a red sub-pixel unit, a green sub-pixel unit and a blue sub-pixel unit, and the sub-pixel units connected to the same data line are sub-pixel units of the same color, and the controlling loads the data signals to the sub-pixel units in the nth row in an order opposite to an order of loading the data signals to the sub-pixel units in the N +1 th row in the N +1 th gate line loading gate on states comprises:
the sequence of loading the data signals to the plurality of sub-pixel units positioned on the Nth row is as follows: the pixel structure comprises a red sub-pixel unit, a green sub-pixel unit and a blue sub-pixel unit;
the sequence of loading the data signals to the plurality of sub-pixel units positioned on the N +1 th row is as follows: the pixel structure comprises a blue sub-pixel unit, a green sub-pixel unit and a red sub-pixel unit.
11. The method according to claim 9, wherein the order of sequentially loading the data signals to the plurality of sub-pixel units in the pixel units located in the odd columns is the same as the arrangement order of the plurality of sub-pixel units in the pixel units located in the odd columns; the sequence of loading the data signals in sequence by the plurality of sub-pixel units in the pixel units positioned in the even columns is opposite to the arrangement sequence of the plurality of sub-pixel units in the pixel units positioned in the even columns;
or the sequence of loading the data signals in sequence by the plurality of sub-pixel units in the odd columns is opposite to the arrangement sequence of the plurality of sub-pixel units in the odd columns; the driving circuit loads the data signals to the plurality of sub-pixel units in the even columns in sequence, and the sequence of the data signals is the same as the arrangement sequence of the plurality of sub-pixel units in the even columns.
12. A display device characterized in that it comprises a display panel as claimed in any one of claims 1 to 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811265810.4A CN111105761B (en) | 2018-10-29 | 2018-10-29 | Display panel, control method thereof and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811265810.4A CN111105761B (en) | 2018-10-29 | 2018-10-29 | Display panel, control method thereof and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111105761A true CN111105761A (en) | 2020-05-05 |
| CN111105761B CN111105761B (en) | 2022-04-22 |
Family
ID=70420118
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811265810.4A Active CN111105761B (en) | 2018-10-29 | 2018-10-29 | Display panel, control method thereof and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111105761B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116092405A (en) * | 2022-12-12 | 2023-05-09 | 北京京东方技术开发有限公司 | Display panel, display driving method, display driving module and display device |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1956048A (en) * | 2005-10-20 | 2007-05-02 | 株式会社日立显示器 | display device |
| CN101149895A (en) * | 2006-08-18 | 2008-03-26 | 恩益禧电子股份有限公司 | Display panel driving technology to reduce power consumption |
| JP2012028170A (en) * | 2010-07-23 | 2012-02-09 | Hitachi Displays Ltd | Organic electroluminescent display device |
| CN104347663A (en) * | 2013-08-05 | 2015-02-11 | 业鑫科技顾问股份有限公司 | Organic Light Emitting Diode Display Panel |
| CN104505047A (en) * | 2014-12-31 | 2015-04-08 | 深圳市华星光电技术有限公司 | Display driving method, circuit and liquid crystal display |
| CN104678670A (en) * | 2015-03-17 | 2015-06-03 | 厦门天马微电子有限公司 | Array substrate, display panel and display device |
| CN106292096A (en) * | 2016-10-13 | 2017-01-04 | 武汉华星光电技术有限公司 | A kind of De mux liquid crystal display and driving method thereof |
| US20170148409A1 (en) * | 2015-05-26 | 2017-05-25 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Liquid crystal display panel and driving method thereof |
| CN107886885A (en) * | 2016-09-29 | 2018-04-06 | 乐金显示有限公司 | Display device and sub-pixel conversion method |
| EP3343284A1 (en) * | 2015-08-28 | 2018-07-04 | Boe Technology Group Co. Ltd. | Array panel, display device and drive method |
-
2018
- 2018-10-29 CN CN201811265810.4A patent/CN111105761B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1956048A (en) * | 2005-10-20 | 2007-05-02 | 株式会社日立显示器 | display device |
| CN101149895A (en) * | 2006-08-18 | 2008-03-26 | 恩益禧电子股份有限公司 | Display panel driving technology to reduce power consumption |
| JP2012028170A (en) * | 2010-07-23 | 2012-02-09 | Hitachi Displays Ltd | Organic electroluminescent display device |
| CN104347663A (en) * | 2013-08-05 | 2015-02-11 | 业鑫科技顾问股份有限公司 | Organic Light Emitting Diode Display Panel |
| CN104505047A (en) * | 2014-12-31 | 2015-04-08 | 深圳市华星光电技术有限公司 | Display driving method, circuit and liquid crystal display |
| CN104678670A (en) * | 2015-03-17 | 2015-06-03 | 厦门天马微电子有限公司 | Array substrate, display panel and display device |
| US20170148409A1 (en) * | 2015-05-26 | 2017-05-25 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Liquid crystal display panel and driving method thereof |
| EP3343284A1 (en) * | 2015-08-28 | 2018-07-04 | Boe Technology Group Co. Ltd. | Array panel, display device and drive method |
| CN107886885A (en) * | 2016-09-29 | 2018-04-06 | 乐金显示有限公司 | Display device and sub-pixel conversion method |
| CN106292096A (en) * | 2016-10-13 | 2017-01-04 | 武汉华星光电技术有限公司 | A kind of De mux liquid crystal display and driving method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116092405A (en) * | 2022-12-12 | 2023-05-09 | 北京京东方技术开发有限公司 | Display panel, display driving method, display driving module and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111105761B (en) | 2022-04-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11508298B2 (en) | Display panel and driving method thereof and display device | |
| KR100982104B1 (en) | Display devices | |
| US8587504B2 (en) | Liquid crystal display and method of driving the same | |
| US9934752B2 (en) | Demultiplex type display driving circuit | |
| US9865218B2 (en) | Display device | |
| US8199102B2 (en) | Liquid crystal display and method of driving the same utilizing data line blocks | |
| CN107993629B (en) | Driving method of liquid crystal display device | |
| US20100302215A1 (en) | Liquid crystal display device and liquid crystal display panel thereof | |
| US10482835B2 (en) | Gate driving circuit, gate driving method, array substrate and display panel | |
| WO2020244342A1 (en) | Display panel and driving method therefor, and display apparatus | |
| JP2007188089A (en) | Liquid crystal display | |
| US11282425B2 (en) | Source driving circuit and display panel | |
| CN110010096B (en) | Display panel, driving method thereof and display device | |
| US20150187292A1 (en) | Thin film transistor array panel and display device | |
| CN108628049A (en) | array substrate, display panel and display device | |
| US10410594B2 (en) | Active matrix substrate, and display device including same | |
| US10685612B2 (en) | Liquid crystal display device and liquid crystal display method | |
| CN114627793A (en) | Array substrate, display panel and display device | |
| CN111105761B (en) | Display panel, control method thereof and display device | |
| JP2017198914A (en) | Display device | |
| CN113781970B (en) | Driving circuit and driving method, and display device | |
| CN113439297B (en) | Display device and driving method thereof | |
| JP2015232590A (en) | Electro-optical device, electronic apparatus, and control method of electro-optical device | |
| CN111540323A (en) | Liquid crystal display device having a plurality of pixel electrodes | |
| KR20070109011A (en) | Liquid crystal panel and driving method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |