CN111096766A

CN111096766A - Portable color Doppler ultrasound device and color Doppler ultrasound system

Info

Publication number: CN111096766A
Application number: CN202010118513.8A
Authority: CN
Inventors: 毛志林; 宋浩然; 翟慎文; 兰家富; 凌灿
Original assignee: Shenzhen WellD Medical Electronics Co ltd
Current assignee: Shenzhen WellD Medical Electronics Co ltd
Priority date: 2020-02-26
Filing date: 2020-02-26
Publication date: 2020-05-05

Abstract

The invention discloses a portable color ultrasonic device and a color ultrasonic system, wherein the color ultrasonic system comprises a PC (personal computer), at least two probes, a probe switching device and the portable color ultrasonic device; each probe is connected with a probe switching device, and the portable color Doppler ultrasound device is connected with the probe switching device and the PC; the portable color Doppler ultrasound device controls the probe switching device to identify the plugging and unplugging state of each probe and switch among the probes; the transmitting excitation signal output by the portable color ultrasonic device is transmitted to the probe through the probe switching device, the probe converts the transmitting excitation signal into an ultrasonic signal and transmits the ultrasonic signal, and the probe receives a feedback echo signal and transmits the echo signal to the portable color ultrasonic device through the probe switching device; the portable color ultrasonic device performs data processing on the echo signals, generates corresponding ultrasonic data and transmits the ultrasonic data to the PC for display. The plug-in state of each probe can be identified in the power-on state, and the problem that the existing notebook color ultrasound system cannot realize hot plug of the probe is solved.

Description

Portable color Doppler ultrasound device and color Doppler ultrasound system

Technical Field

The invention relates to the technical field of electronics, in particular to a portable color ultrasound device and a color ultrasound system.

Background

The existing notebook color ultrasound device usually adopts a hardware architecture as shown in fig. 1, wherein a transmitting unit (provided with a transmitting/receiving switch inside) usually adopts a 3-level or 5-level chip, and the models are HDL5584, HDL5585 and the like; the receiving unit usually adopts 8-channel chip, such as AFE5805, AFE5808, AD927X, etc. The chips are correspondingly integrated with an LNA (low noise amplifier), a VCAT (voltage control attenuator), a PGA (programmable gain amplifier), an ADC (analog-to-digital converter), an LVDS (low voltage differential signal) interface, a CW-mixer (continuous Doppler mixer) and the like, and are very suitable for the application of notebook color Doppler ultrasound.

However, none of these chips except for a demodulator (demodulator). After a digital RF (radio frequency) signal enters an FPGA (field programmable gate array), only a traditional beam forming method (beam forming of an RF domain) can be adopted, namely delay (coarse delay + fine delay), addition, demodulation and the like, the focusing precision depends on the sampling frequency of an ADC (analog to digital converter) and a fine delay circuit, and the design difficulty and complexity of the FPGA are greatly increased. Moreover, due to the limitation of the word length inside the FPGA, the performance of the fir (finite impulse response) filter of the demodulator is greatly reduced, and the dynamic range and the spatial resolution of the image are seriously affected.

Meanwhile, if the hardware architecture needs to perform beam forming in an I/Q domain, circuits such as I/Q separation, FIR filtering, extraction and the like need to be designed for each channel in the FPGA, which occupies a large amount of FPGA resources, and is a nearly impossible scheme for circuit design especially when the number of channels is large and factors such as word length precision are considered. And the data preprocessed by the FPGA is transmitted to a computer or an intelligent terminal through a PCIe (peripheral component interconnect express) interface or a USB3.0 interface. The architecture needs a high-speed data transmission protocol, and has very high requirements on the performance of a computer or an intelligent terminal and the performance of an interface of the computer or the intelligent terminal. In addition, a probe switching circuit is not designed in the hardware architecture, only one probe connector is generally supported, other probes need to be replaced after power failure when the probes are switched, hot plugging of the probes cannot be achieved, and the application is inconvenient.

Thus, the prior art has yet to be improved and enhanced.

Disclosure of Invention

In view of the above disadvantages of the prior art, the present invention provides a portable color ultrasound device and a color ultrasound system, so as to solve the problem that the existing notebook color ultrasound system cannot realize hot plug of a probe.

In order to achieve the purpose, the invention adopts the following technical scheme:

a portable color Doppler ultrasound device is connected with a probe switching device and a PC, and comprises a receiving and transmitting isolation unit, a receiving unit, a processing unit and an interface unit: the receiving and transmitting isolation unit is connected with the receiving unit, the processing unit and the probe switching device, the processing unit is connected with the receiving unit and the interface unit, and the interface unit is externally connected with a PC;

the processing unit detects the plugging and unplugging state of the probe according to the identification signal fed back by the probe switching device, controls the probe switching device to enable the corresponding probe, and also outputs a transmission driving control signal to the receiving and transmitting isolation unit;

the receiving and transmitting isolation unit generates a transmitting excitation signal according to the transmitting driving control signal and transmits the transmitting excitation signal to the probe switching device, and also transmits a received echo signal to the receiving unit;

the receiving unit amplifies, compresses, logarithmically processes, IQ demodulates and analog-to-digital converts the echo signals and then outputs corresponding LVDS data to the processing unit;

the processing unit carries out channel sequencing, beam synthesis, blood flow extraction and image processing on the LVDS data and then outputs corresponding ultrasonic data;

and the interface unit transmits the preprocessed ultrasonic data to a PC.

In the portable color ultrasonic device, the transmitting-receiving isolation unit comprises a first ultrasonic transmitting-receiving chip U1, a second ultrasonic transmitting-receiving chip, a third ultrasonic transmitting-receiving chip and a fourth ultrasonic transmitting-receiving chip;

the TR0 pin, the TR1 pin, the CC0 pin, the CC1 pin, the EN pin, the IN _ P1 pin to the IN _ P8 pin and the IN _ N1 pin to the IN _ N8 pin of the first ultrasonic transceiving chip are all connected with a processing unit; the pins HVout1 to HVout8 of the first ultrasonic transceiver chip are connected with the probe switching device; the pins from LVout1 to LVout8 of the first ultrasonic transceiver chip U1 are all connected with a receiving unit;

the TR0 pin, the TR1 pin, the CC0 pin, the CC1 pin, the EN pin, the IN _ P1 pin to the IN _ P8 pin and the IN _ N1 pin to the IN _ N8 pin of the second ultrasonic transceiving chip are all connected with a processing unit; the pins HVout1 to HVout8 of the second ultrasonic transceiver chip are connected with the probe switching device; pins LVout1 to LVout8 of the second ultrasonic transceiver chip are connected with the receiving unit;

the TR0 pin, the TR1 pin, the CC0 pin, the CC1 pin, the EN pin, the IN _ P1 pin to the IN _ P8 pin and the IN _ N1 pin to the IN _ N8 pin of the third ultrasonic transceiving chip are all connected with a processing unit; the pins HVout1 to HVout8 of the third ultrasonic transceiver chip are connected with the probe switching device; the pins from LVout1 to LVout8 of the third ultrasonic transceiver chip U3 are all connected with a receiving unit;

the TR0 pin, the TR1 pin, the CC0 pin, the CC1 pin, the EN pin, the IN _ P1 pin to the IN _ P8 pin and the IN _ N1 pin to the IN _ N8 pin of the fourth ultrasonic transceiving chip are all connected with a processing unit; the pins HVout1 to HVout8 of the fourth ultrasonic transceiver chip are connected with the probe switching device; pins LVout1 to LVout8 of the fourth ultrasound transceiver chip are all connected to the receiving unit.

In the portable color ultrasonic device, the receiving unit comprises a first ultrasonic analog front-end chip, a second ultrasonic analog front-end chip, a third ultrasonic analog front-end chip and a fourth ultrasonic analog front-end chip;

the SEN pin, the SCLK pin, the SDATA pin, the D1P pin to the D8P pin, the D1M pin to the D8M pin, the DCLKP pin, the DCLKM pin, the FCLKP pin and the FCLKM pin of the first ultrasonic simulation front-end chip are all connected with a processing unit; an ACT1 pin, an ACT2 pin, an ACT3 pin, an ACT4 pin, an ACT5 pin, an ACT6 pin, an ACT7 pin and an ACT8 pin of the first ultrasonic analog front-end chip are connected with an LVout1 pin, an LVout2 pin, an LVout3 pin, an LVout4 pin, an LVout5 pin, an LVout6 pin, an LVout7 pin and an LVout8 pin of the first ultrasonic transceiver chip in a one-to-one manner; the INP1 pin, the INP2 pin, the INP3 pin, the INP4 pin, the INP5 pin, the INP6 pin, the INP7 pin and the INP8 pin of the first ultrasonic analog front-end chip are connected with the ACT1 pin, the ACT2 pin, the ACT3 pin, the ACT4 pin, the ACT5 pin, the ACT6 pin, the ACT7 pin and the ACT8 pin of the first ultrasonic analog front-end chip in a one-to-one mode;

the SEN pin, the SCLK pin, the SDATA pin, the D1P pin to the D8P pin, the D1M pin to the D8M pin, the DCLKP pin, the DCLKM pin, the FCLKP pin and the FCLKM pin of the second ultrasonic simulation front-end chip are all connected with a processing unit; an ACT1 pin, an ACT2 pin, an ACT3 pin, an ACT4 pin, an ACT5 pin, an ACT6 pin, an ACT7 pin and an ACT8 pin of the second ultrasonic analog front-end chip are connected with an LVout1 pin, an LVout2 pin, an LVout3 pin, an LVout4 pin, an LVout5 pin, an LVout6 pin, an LVout7 pin and an LVout8 pin of the second ultrasonic transceiver chip in a one-to-one manner; the INP1 pin, the INP2 pin, the INP3 pin, the INP4 pin, the INP5 pin, the INP6 pin, the INP7 pin and the INP8 pin of the second ultrasonic analog front-end chip are connected with the ACT1 pin, the ACT2 pin, the ACT3 pin, the ACT4 pin, the ACT5 pin, the ACT6 pin, the ACT7 pin and the ACT8 pin of the second ultrasonic analog front-end chip in a one-to-one mode;

the SEN pin, the SCLK pin, the SDATA pin, the D1P pin to the D8P pin, the D1M pin to the D8M pin, the DCLKP pin, the DCLKM pin, the FCLKP pin and the FCLKM pin of the third ultrasonic simulation front-end chip are all connected with a processing unit; an ACT1 pin, an ACT2 pin, an ACT3 pin, an ACT4 pin, an ACT5 pin, an ACT6 pin, an ACT7 pin and an ACT8 pin of the third ultrasonic analog front-end chip are connected with an LVout1 pin, an LVout2 pin, an LVout3 pin, an LVout4 pin, an LVout5 pin, an LVout6 pin, an LVout7 pin and an LVout8 pin of the third ultrasonic transceiver chip in a one-to-one manner; the INP1 pin, the INP2 pin, the INP3 pin, the INP4 pin, the INP5 pin, the INP6 pin, the INP7 pin and the INP8 pin of the third ultrasonic analog front-end chip are connected with the ACT1 pin, the ACT2 pin, the ACT3 pin, the ACT4 pin, the ACT5 pin, the ACT6 pin, the ACT7 pin and the ACT8 pin of the third ultrasonic analog front-end chip in a one-to-one mode;

the SEN pin, the SCLK pin, the SDATA pin, the D1P pin to the D8P pin, the D1M pin to the D8M pin, the DCLKP pin, the DCLKM pin, the FCLKP pin and the FCLKM pin of the fourth ultrasonic simulation front-end chip are all connected with a processing unit; an ACT1 pin, an ACT2 pin, an ACT3 pin, an ACT4 pin, an ACT5 pin, an ACT6 pin, an ACT7 pin and an ACT8 pin of the fourth ultrasonic analog front-end chip are connected with an LVout1 pin, an LVout2 pin, an LVout3 pin, an LVout4 pin, an LVout5 pin, an LVout6 pin, an LVout7 pin and an LVout8 pin of the fourth ultrasonic transceiver chip in a one-to-one manner; the INP1 pin, the INP2 pin, the INP3 pin, the INP4 pin, the INP5 pin, the INP6 pin, the INP7 pin and the INP8 pin of the fourth ultrasonic analog front-end chip are connected with the ACT1 pin, the ACT2 pin, the ACT3 pin, the ACT4 pin, the ACT5 pin, the ACT6 pin, the ACT7 pin and the ACT8 pin of the fourth ultrasonic analog front-end chip in a one-to-one mode.

In the portable color ultrasonic device, the processing unit comprises an FPGA chip and a DSP chip, and the FPGA chip comprises a first functional module, a second functional module, a third functional module, a fourth functional module and a fifth functional module;

the F7 pin of the first functional module is connected with the CC1 pins of the first ultrasonic transceiver chip and the fourth ultrasonic transceiver chip; the F8 pin of the first functional module is connected with the CC0 pins of the first ultrasonic transceiver chip and the fourth ultrasonic transceiver chip; the H6 pin of the first functional module is connected with the EN pins of the first ultrasonic transceiver chip and the fourth ultrasonic transceiver chip; a G11 pin, a G10 pin, an F10 pin, an E10 pin, a D10 pin, a C10 pin, a B10 pin, a10 pin, A8 pin, a7 pin, a D6 pin, a C6 pin, a B3 pin, a4 pin, A3 pin, a2 pin, a11 pin, a C11 pin, a9 pin, a9 pin of the first functional module and a D1P pin, a D1M pin, a D2P pin, a D2M pin, a D3P pin, a D3M pin, a D4P pin, a D4M pin, a D5P pin, a D5M pin, a D6P pin, a D6M pin, a D7P pin, a D7M pin, a D8P pin, a D8M pin, a DCFCLKM pin and a pair of first ultrasonic simulation front-end chip are connected; the H9 pin, the AC13 pin, the AA8 pin, the AA9 pin and the E9 pin of the first functional module are all connected with the probe switching device; the F9 pin of the first functional module is connected with the SEN pins of the first ultrasonic analog front-end chip and the fourth ultrasonic analog front-end chip; the G9 pin of the first functional module is connected with the SCLK pins of the first ultrasonic simulation front-end chip and the fourth ultrasonic simulation front-end chip; a W12 pin of the first functional module is connected with SDATA pins of the first ultrasonic analog front-end chip and the fourth ultrasonic analog front-end chip;

the pin C7, the pin F3, the pin AB4, the pin AA5, the pin D8, the pin G3, the pin AB5, the pin AA6, the pin C9, the pin E3, the pin U3, the pin AB6, the pin D9, the pin D3, the pin T2, the pin V6, and the pin IN _ P1, the pin IN _ N1, the pin IN _ P2, the pin IN _ N2, the pin IN _ P3, the pin IN _ N3, the pin IN _ P4, the pin IN _ N4, the pin IN _ P5, the pin IN _ N5, the pin IN _ P6, the pin IN _ N6, the pin IN _ P7, the pin IN _ N7, the pin IN _ P8 and the pin IN _ N8 of the second functional module are connected IN a one-to one manner; a pair of connecting pins of C3, C2, B1, C1, D2, D1, E1, F1, H1, J1, K1, L1, M4, M3, N1, P1, N4, N3, G2, G1 of the second functional module, D1P, D1M, D2P, D2M, D3P, D3M, D4P, D4M, D5P, D5M, D6P, D6M, D7P, D7M, D8P, D8M, DCLKP, DCFCLKM, and LKM;

the pin H4, the pin T5, the pin C4, the pin J6, the pin G4, the pin R4, the pin B4, the pin M1, the pin F4, the pin R3, the pin D4, the pin L3, the pin E4, the pin T3, and the pin IN _ P2, the pin IN _ N2, the pin IN _ P3, the pin IN _ N3, the pin IN _ P4, the pin IN _ N4, the pin IN _ P5, the pin IN _ N5, the pin IN _ P6, the pin IN _ N6, the pin IN _ P7, the pin IN _ N7, the pin IN _ P8, and the pin IN _ N8 of the third functional module are connected one to one; the pin a5, the pin K3, the pin V3, the pin T4, the pin B6, the pin K2, the pin W2, the pin V4, the pin a6, the pin J3, the pin Y3, the pin W4, the pin B7, the pin H3, the pin AA4, the pin W3, and the pin IN _ P1, the pin IN _ N1, the pin IN _ P2, the pin IN _ N2, the pin IN _ P3, the pin IN _ N3, the pin IN _ P4, the pin IN _ N4, the pin IN _ P5, the pin IN _ N5, the pin IN _ P6, the pin IN _ N6, the pin IN _ P7, the pin IN _ N7, the pin IN _ P8, and the pin IN _ N8 of the third functional module are connected IN a one-to-one manner; a pair of connecting pins of R1, T1, U1, V1, W2, Y1, AA1, AB1, AB2, AC1, AC3, AC4, AD2, AD3, AD4, AD5, P4, P3, AA3, AB3 of the third functional module, D1P, D1M, D2P, D2M, D3P, D3M, D4P, D4M, D5P, D5M, D6P, D6M, D7P, D7M, D8P, D8M, DCLKP, DCFCLKM, and LKM;

a pin G6, a pin N6, a pin K4, a pin R7, a pin G5, a pin N2, a pin K5, a pin P7, a pin D7, a pin N7, a pin J4, a pin R6, a pin E7, a pin M7, a pin J5, and a pin R5 of the fourth functional module are connected with a pin IN _ P1, a pin IN _ N1, a pin IN _ P2, a pin IN _ N2, a pin IN _ P3, a pin IN _ N3, a pin IN _ P4, a pin IN _ N4, a pin IN _ P5, a pin IN _ N5, a pin IN _ P6, a pin IN _ N6, a pin IN _ P7, a pin IN _ N7, a pin IN _ P8, and a pin IN _ N8 of the first functional module; the pins G8 and L7 of the fourth functional module are connected with the pins IN _ P1 and IN _ N1 of the second ultrasonic transceiving chip IN a one-to-one manner; a pair of connecting pins of AC6, AD6, AA7, AB7, AA10, AB10, AA11, AB11, AD9, AD10, AD11, AD12, AB12, AC12, Y12, AA12, AD13, AD14, AD7, AD8 of the fourth functional module, D1P, D1M, D2P, D2M, D3P, D3M, D4P, D4M, D5P, D5M, D6P, D6M, D7P, D7M, D8P, D8M, DCLKP, DCFCLKM, and LKM;

AA23, AA24, W23, W24, R24, N24, Y24, V24, P24, M24, ritotxp 24 of the DSP chip, ritotxp 24, ritotxn 24, ritotxp 24, ritotxn 24, ritotxp 24, RIORXN 24, ritorxn 24 and ritorxn 24 of the fifth functional module are connected in a pair; the pins K22, K21, H22, H21, D22, D21, B22 and B21 of the fifth functional module are all connected with a probe switching device;

and the SGMII1RXP pin, the SGMII1RXN pin, the SGMII1TXP pin, the SGMII1TXN pin, the MDIO pin and the MDCLK pin of the DSP chip are all connected with an interface circuit.

In the portable color super device, the interface unit comprises an Ethernet chip, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor and a crystal head;

the S _ OUT + pin, the S _ OUT-pin, the S _ IN + pin, the S _ IN-pin, the MDIO pin and the MDC pin of the Ethernet chip are connected with the SGMII1RXP pin, the SGMII1RXN pin, the SGMII1TXP pin, the SGMII1TXN pin, the MDIO pin and the MDCLK pin of the DSP chip IN a one-to-one way; the MDI3+ pin of the Ethernet chip is connected with one end of the first resistor and the 9 th pin of the crystal head, the MDI 3-pin of the Ethernet chip is connected with one end of the second resistor and the 8 th pin of the crystal head, the MDI2+ pin of the Ethernet chip is connected with one end of the third resistor and the 2 nd pin of the crystal head, the MDI 2-pin of the Ethernet chip is connected with one end of the fourth resistor and the 3 rd pin of the crystal head, the other end of the first resistor is connected with one end of the first capacitor and the other end of the second resistor, the other end of the third resistor is connected with one end of the second capacitor and the other end of the fourth resistor, the other end of the first capacitor is connected with the other end of the second capacitor and the ground, the MDI1+ pin of the Ethernet chip is connected with one end of the eighth resistor and the 5 th pin of the crystal head, the MDI 1-pin of the Ethernet chip is connected with one end of the seventh resistor and the 4 th pin of the crystal head, the MDI10+ pin of the Ethernet chip is connected with the first end of the sixth resistor and the 10 th, one end of a fifth resistor and the 11 th pin of the crystal head are connected to the MDI 10-pin of the Ethernet chip, the other end of an eighth resistor is connected to one end of a fourth capacitor and the other end of a seventh resistor, the other end of a sixth resistor is connected to one end of a third capacitor and the other end of the fifth resistor, and the other end of the fourth capacitor is connected to the other end of the third capacitor and the ground.

A color Doppler ultrasound system comprises a PC, at least two probes, a probe switching device and a portable color ultrasound device; the portable color Doppler ultrasound device is connected with the probe switching device and the PC;

the portable color Doppler ultrasound device controls the probe switching device to identify the plugging and unplugging state of each probe and switch among the probes;

the transmitting excitation signal output by the portable color ultrasonic device is transmitted to the probe through the probe switching device, the probe converts the transmitting excitation signal into an ultrasonic signal and transmits the ultrasonic signal, and the probe receives a feedback echo signal and transmits the echo signal to the portable color ultrasonic device through the probe switching device;

the portable color ultrasonic device performs data processing on the echo signals, generates corresponding ultrasonic data and transmits the ultrasonic data to a PC (personal computer) for display.

In the color Doppler ultrasound system, the probe switching device comprises a hot plug detection unit, a probe identification unit, a driving unit and a plurality of probe sockets; the hot plug detection unit is connected with each probe socket and the FPGA chip in the processing unit, the probe identification unit is connected with the driving unit and the FPGA chip, the driving unit is connected with each probe socket and the FPGA chip, and each probe socket is correspondingly externally connected with one probe;

when the hot plug detection unit detects that a probe is plugged after being powered on, outputting a corresponding hot plug identification signal to the FPGA chip;

the probe identification unit scans the identification code of the probe and outputs a corresponding identification signal to the FPGA chip;

the probe identification unit generates a probe selection signal according to the selection signal output by the FPGA chip;

and the driving unit amplifies the probe selection signal and the array element driving control signal output by the FPGA chip, outputs a corresponding probe enabling signal and an array element selection signal and transmits the signals to a corresponding probe socket.

In the color Doppler ultrasound system, the probe socket comprises a first probe socket, a second probe socket, a third probe socket and a fourth probe socket;

the hot plug detection unit comprises a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor and a fifth capacitor;

one end of the ninth resistor is connected with one end of the fifth capacitor, one end of the tenth resistor, one end of the eleventh resistor, one end of the twelfth resistor, one end of the thirteenth resistor and the processing unit; the other end of the ninth resistor is connected with a power supply end, the other end of the fifth capacitor is grounded, the other end of the tenth resistor is connected with the first probe socket, the other end of the eleventh resistor is connected with the second probe socket, the other end of the twelfth resistor is connected with the third probe socket, and the other end of the thirteenth resistor is connected with the fourth probe socket.

In the color Doppler ultrasound system, the probe identification unit comprises a decoding chip, a multiplexer and a sixth capacitor;

the A pin of the decoding chip is connected with the A0 pin and the processing unit of the multiplexer, the B pin of the decoding chip is connected with the A1 pin and the processing unit of the multiplexer, and the A pin of the decoding chip is connected with the processing unit of the multiplexer

A foot part,

A foot part,

Foot and

the feet are all connected with a driving unit; the COM pin of the multiplexer is connected with the processing unit, and the EN pin of the multiplexer is connected with the V + pin, one end of the sixth capacitor and a power supply end; NO1 pin, NO2 pin, NO3 pin and NO4 pin of the multiplexer are connected with the first probe socket, the second probe socket, the third probe socket and the fourth probe socket in a one-to-one mode; and the GND pin of the multiplexer is connected with the other end of the sixth capacitor and the ground.

In the color Doppler ultrasound system, the driving unit comprises a first driving chip and a second driving chip;

pins B5, B6, B7 and B8 of the first driver chip and the decoder chip

A foot part,

A foot part,

Foot and

the feet are connected in a one-to-one way; the B3 pin of the first drive chip is connected with the B4 pin and the processing unit, the B1 pin of the first drive chip is connected with the B2 pin and the processing unit, the A3 pin of the first drive chip is connected with the A4 pin and the probe socket, and the A1 pin of the first drive chip is connected with the A2 pin and the probe socket; the A5 pin, the A6 pin, the A7 pin and the A8 pin of the first drive chip are connected with the first probe socket, the second probe socket, the third probe socket and the fourth probe socket in a one-to-one mode; the pin B1, the pin B2, the pin B3, the pin B4, the pin B5, the pin B6, the pin B7 and the pin B8 of the second driving chip are all connected with the processing unit; a1 pin, A2 pin, A3 pin, A4 pin, A5 pin, A6 pin, A7 pin and A8 pin of the second driving chip are connected with the probe sockets respectively.

Compared with the prior art, the portable color ultrasonic device and the color ultrasonic system provided by the invention comprise a PC (personal computer), at least two probes, a probe switching device and the portable color ultrasonic device; the portable color Doppler ultrasound device is connected with the probe switching device and the PC; the portable color Doppler ultrasound device controls the probe switching device to identify the plugging and unplugging state of each probe and switch among the probes; the transmitting excitation signal output by the portable color ultrasonic device is transmitted to the probe through the probe switching device, the probe converts the transmitting excitation signal into an ultrasonic signal and transmits the ultrasonic signal, and the probe receives a feedback echo signal and transmits the echo signal to the portable color ultrasonic device through the probe switching device; the portable color ultrasonic device performs data processing on the echo signals, generates corresponding ultrasonic data and transmits the ultrasonic data to a PC (personal computer) for display. The plug-in state of each probe can be identified and switched among the probes under the state of keeping the power-on work, the hot plug-in of the probes can be realized, the trouble that the probes can be replaced only by shutting down in the prior art is avoided, and the problem that the hot plug-in of the probes cannot be realized by the existing notebook color ultrasound system is solved.

Drawings

Fig. 1 is a schematic diagram of a hardware architecture of a conventional notebook color ultrasound.

Fig. 2 is a block diagram of a color Doppler ultrasound system provided by the invention.

Fig. 3 is a circuit diagram of a first ultrasound transceiver chip in the transceiver isolation unit according to the present invention.

Fig. 4 is a circuit diagram of a second ultrasound transceiver chip in the transceiver isolation unit provided by the present invention.

Fig. 5 is a circuit diagram of a third ultrasound transceiver chip in the transceiver isolation unit provided by the present invention.

Fig. 6 is a circuit diagram of a fourth ultrasound transceiver chip in the transceiver isolation unit provided by the present invention.

Fig. 7 is a circuit diagram of a first ultrasound analog front-end chip in the receiving unit provided by the present invention.

Fig. 8 is a circuit diagram of a second ultrasound analog front-end chip in the receiving unit provided by the present invention.

Fig. 9 is a circuit diagram of a third ultrasound analog front-end chip in the receiving unit provided by the present invention.

Fig. 10 is a circuit diagram of a fourth ultrasound analog front-end chip in the receiving unit provided by the present invention.

Fig. 11 is a circuit diagram of a first functional module in the FPGA chip according to the present invention.

Fig. 12 is a circuit diagram of a second functional module in the FPGA chip according to the present invention.

Fig. 13 is a circuit diagram of a third functional module in the FPGA chip according to the present invention.

Fig. 14 is a circuit diagram of a fourth functional module in the FPGA chip according to the present invention.

Fig. 15 is a circuit diagram of a fifth functional module in the FPGA chip according to the present invention.

Fig. 16 is a circuit diagram of a DSP chip provided by the present invention.

Fig. 17 is a schematic diagram of an internal signal flow of the FPGA chip according to the present invention.

Fig. 18 is a circuit diagram of an interface unit provided by the present invention.

Fig. 19 is a circuit diagram of a hot plug detecting unit in the probe switching device according to the present invention.

Fig. 20 is a circuit diagram of a probe identification unit in the probe switching device provided by the present invention.

Fig. 21 is a circuit diagram of a driving unit in the probe switching device provided by the present invention.

FIG. 22 is a schematic view of a probe socket provided by the present invention.

Detailed Description

The invention provides a portable color ultrasonic device and a color ultrasonic system. In order to make the objects, technical solutions and effects of the present invention clearer and clearer, the present invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Referring to fig. 2, the color ultrasound system according to the embodiment of the present invention includes at least two probes (4 probes are taken as an example in the embodiment), a probe switching device 10, a portable color ultrasound device 20, and a PC 30; each probe is connected with the probe switching device 10, the portable color Doppler ultrasound device 20 is connected with the probe switching device 10 and the PC 30, after the power is on, the portable color Doppler ultrasound device 20 controls the probe switching device 10 to identify the plugging state and the probe information of each probe and switch among the probes as required, the portable color Doppler ultrasound device 20 outputs a transmitting excitation signal, the ultrasonic data transmission device transmits the ultrasonic data to the PC 30, the transducer array element on the probe converts the transmitting excitation signal into an ultrasonic signal and transmits the ultrasonic signal, the ultrasonic wave enters the human body and then generates a reflection signal and feeds back the corresponding echo signal, the transducer array element on the probe receives the echo signal and transmits the echo signal to the portable color ultrasonic device 20 through the probe switching device 10, and the portable color ultrasonic device 20 performs data processing on the echo signal and generates corresponding ultrasonic data, and transmits the ultrasonic data to the PC 30 for post-processing imaging display.

Wherein, the probe is a medical ultrasonic diagnosis probe. The portable color ultrasonic device can adopt a notebook or a tablet computer as a color ultrasonic platform. Can connect the probe of two at least different grade types through probe auto-change over device 10, for example can connect abdomen convex array probe, high frequency linear array probe, heart probe etc. simultaneously, the doctor can be according to the needs of inspection, pull out and insert the probe under the state of keeping circular telegram work, probe auto-change over device 10 passes through the identification code of scanning each probe and transmits the type of the probe of discerning inserting for portable color Doppler ultrasound device 20, if do not have the identification code then no probe connection, can realize like this that the hot of probe is pulled out and is inserted and switch into required probe, can avoid prior art need shut down just can change the trouble of probe, the problem that current notebook formula color Doppler ultrasound system can not realize probe hot pull out and insert has been solved, it is more convenient to use. Meanwhile, the ultrasonic data processed by the portable color ultrasonic device 20 is directly transmitted to the PC through USB2.0 or EMAC (internet access), which greatly reduces the amount of data transmitted to the PC, thereby greatly reducing the requirements for the transmission protocol and the interface performance of the PC. It should be understood that the control of the portable color Doppler ultrasound device by the PC is the prior art (such as data storage and display, man-machine interaction), and the detailed description thereof is omitted here.

In this embodiment, the portable color Doppler ultrasound device 20 includes a transceiver isolation unit 210, a receiving unit 220, a processing unit 230, and an interface unit 240; the receiving and transmitting isolation unit 210 is connected with the receiving unit 220, the processing unit 230 and the probe switching device 10, the processing unit 230 is connected with the receiving unit 220 and the interface unit 240, and the interface unit 240 is externally connected with the PC 30; the processing unit 230 detects the plugging/unplugging state of the probe according to the identification signal fed back by the probe switching device 10 and controls the probe switching device 10 to enable the corresponding probe (in the specific implementation, the high-voltage switch in the corresponding probe socket is enabled, i.e. the corresponding signal is output to the connected probe through the probe socket), and also outputs a transmission driving control signal (FS 1-FS 64) to the transceiving isolating unit 210, the transceiving isolating unit 210 drives the ultrasonic pulse generator to generate a transmission excitation signal (TR 1-TR 32) according to the transmission driving control signal (FS 1-FS 64) and transmits the transmission excitation signal (TR 1-TR 32) to the probe socket inside the probe switching device 10 so as to transmit the transmission excitation signal to the corresponding probe, and the transducer array on the probe converts the transmission excitation signal (TR 1-TR 32) into the corresponding ultrasonic signal. The transmitting and receiving isolation unit 210 isolates the transmitting signal from the received echo signal, and the receiving unit 220 amplifies, compresses, logarithmically processes, IQ demodulates and performs analog-to-digital conversion on the received echo signal and outputs corresponding LVDS data to the processing unit; the processing unit 230 performs channel ordering, beam forming, blood flow extraction and image processing on the LVDS data and outputs corresponding ultrasonic data; the interface unit 240 transmits the preprocessed ultrasonic data to the PC at high speed.

The transmit/receive isolation unit 210 generates various pulses/pulse trains (i.e., transmit excitation signals (TR 1-TR 32) with adjustable voltage, frequency, number of cycles, etc.) with adjustable programs for exciting transducer elements of the probe to generate ultrasonic signals. Referring to fig. 3, 4, 5 and 6, the transceiver isolation unit 210 includes a first ultrasound transceiver chip U1, a second ultrasound transceiver chip U2, a third ultrasound transceiver chip U3 and a fourth ultrasound transceiver chip U4; the TR0 pin, the TR1 pin, the CC0 pin, the CC1 pin, the EN pin, the IN _ P1 pin, the IN _ N1 pin, the IN _ P2 pin, the IN _ N2 pin, the IN _ P3 pin, the IN _ N3 pin, the IN _ P4 pin, the IN _ N4 pin, the IN _ P5 pin, the IN _ N5 pin, the IN _ P6 pin, the IN _ N6 pin, the IN _ P7 pin, the IN _ N7 pin, the IN _ P8 pin and the IN _ N8 pin of the first ultrasound transceiver chip U1 are all connected with the processing unit 230; the pin HVout1, the pin HVout2, the pin HVout3, the pin HVout4, the pin HVout5, the pin HVout6, the pin HVout7 and the pin HVout8 of the first ultrasonic transceiver chip U1 are connected with the probe switching device 10; the LVout1 pin, the LVout2 pin, the LVout3 pin, the LVout4 pin, the LVout5 pin, the LVout6 pin, the LVout7 pin and the LVout8 pin of the first ultrasonic transceiver chip U1 are all connected to the receiving unit 220;

the TR0 pin, the TR1 pin, the CC0 pin, the CC1 pin, the EN pin, the IN _ P1 pin, the IN _ N1 pin, the IN _ P2 pin, the IN _ N2 pin, the IN _ P3 pin, the IN _ N3 pin, the IN _ P4 pin, the IN _ N4 pin, the IN _ P5 pin, the IN _ N5 pin, the IN _ P6 pin, the IN _ N6 pin, the IN _ P7 pin, the IN _ N7 pin, the IN _ P8 pin and the IN _ N8 pin of the second ultrasound transceiver chip U2 are all connected with the processing unit 230; the pin HVout1, the pin HVout2, the pin HVout3, the pin HVout4, the pin HVout5, the pin HVout6, the pin HVout7 and the pin HVout8 of the second ultrasonic transceiving chip U2 are all connected with the probe switching device 10; the LVout1 pin, the LVout2 pin, the LVout3 pin, the LVout4 pin, the LVout5 pin, the LVout6 pin, the LVout7 pin and the LVout8 pin of the second ultrasound transceiver chip U2 are all connected to the receiving unit 220;

the TR0 pin, the TR1 pin, the CC0 pin, the CC1 pin, the EN pin, the IN _ P1 pin, the IN _ N1 pin, the IN _ P2 pin, the IN _ N2 pin, the IN _ P3 pin, the IN _ N3 pin, the IN _ P4 pin, the IN _ N4 pin, the IN _ P5 pin, the IN _ N5 pin, the IN _ P6 pin, the IN _ N6 pin, the IN _ P7 pin, the IN _ N7 pin, the IN _ P8 pin and the IN _ N8 pin of the third ultrasound transceiver chip U3 are all connected with the processing unit 230; the pin HVout1, the pin HVout2, the pin HVout3, the pin HVout4, the pin HVout5, the pin HVout6, the pin HVout7 and the pin HVout8 of the third ultrasonic transceiving chip U3 are all connected with the probe switching device 10; the LVout1 pin, the LVout2 pin, the LVout3 pin, the LVout4 pin, the LVout5 pin, the LVout6 pin, the LVout7 pin and the LVout8 pin of the third ultrasound transceiver chip U3 are all connected to the receiving unit 220;

the TR0 pin, the TR1 pin, the CC0 pin, the CC1 pin, the EN pin, the IN _ P1 pin, the IN _ N1 pin, the IN _ P2 pin, the IN _ N2 pin, the IN _ P3 pin, the IN _ N3 pin, the IN _ P4 pin, the IN _ N4 pin, the IN _ P5 pin, the IN _ N5 pin, the IN _ P6 pin, the IN _ N6 pin, the IN _ P7 pin, the IN _ N7 pin, the IN _ P8 pin and the IN _ N8 pin of the fourth ultrasound transceiver chip U4 are all connected with the processing unit 230; the pin HVout1, the pin HVout2, the pin HVout3, the pin HVout4, the pin HVout5, the pin HVout6, the pin HVout7 and the pin HVout8 of the fourth ultrasonic transceiving chip U4 are all connected with the probe switching device 10; the LVout1 pin, the LVout2 pin, the LVout3 pin, the LVout4 pin, the LVout5 pin, the LVout6 pin, the LVout7 pin and the LVout8 pin of the fourth ultrasound transceiver chip U4 are all connected to the receiving unit 220.

The model of each ultrasonic transceiver chip is preferably HDL5584, each HDL5584 chip has 8 channels, and in this embodiment, 32 channels are taken as an example, and 4 chips are required. The FPGA chip in the processing unit 230 outputs a working mode selection signal (TRKZ 0, TRKZ1, CC0, CC 1) to control the working mode of the ultrasound transceiver chip, and the enable signal EN is used to enable the ultrasound transceiver chip. The existing power supply module provides various working voltages (HV _ VA +, HV _ VA-, TR _ +3.3V, TR _ +5V, TR _ -5V) for the ultrasonic transceiver chip. The CLKIF pin, the CLK pin, the CLKB pin and the CLKEN pin of each ultrasonic transceiver chip are all connected with the existing clock module, and the output clock signals (CLKIF, CLK _ P, CLK _ N, CLKEN) provide clocks required by the operation and clock control for the ultrasonic transceiver chip.

Nodes in the ultrasonic transceiver chip can be switched, and different paths are taken during transmitting and receiving, so that transceiver isolation is realized. During transmission, the transmission driving control signals (FS 1-FS 64) output by the FPGA chip in the processing unit 230 are subjected to two-four decoding and level conversion processing by the corresponding ultrasound transceiver chip, and then the ultrasound pulse generator is driven to generate transmission excitation signals (TR 1-TR32, a high-voltage pulse signal) and output to the probe switching device 10, wherein adjacent 2 transmission driving control signals are a group for controlling one high-voltage transmission channel (in the probe switching device 10), for example, a group of FS1 and FS2 controls TR1, a group of FS3 and FS4 controls TR2, and so on. During reception, the echo signal fed back from the probe switching device 10 is input from the HVout1-8 pin of the ultrasound transceiver chip (corresponding to TR1-TR32 at this time representing the echo signal), and the echo signal (RV 1-RV 7) is output from the LVout1-8 pin to the receiving unit 220.

Each ultrasonic transceiver chip has its corresponding peripheral circuit, for example, the VLL pin, the VDD pin, and the VSS pin are grounded through a capacitor (filter), a resistor is connected between the THP pin and the VLL pin, 2 capacitors are connected between the Vpp pin and the Vfp pin, the Vpp pin is also grounded through 4 capacitors (filters) connected in parallel, 2 capacitors are connected between the Vnn pin and the Vfn pin, and the Vnn pin is also grounded through 4 capacitors (filters) connected in parallel, as shown in fig. 3 to 6.

The HDL5584 is a highly integrated 8-channel, 3-level RTZ, high-voltage, high-speed ultrasonic pulse generator and a transceiving conversion isolation chip, integrates a logic control circuit, a level conversion circuit, an MOS transistor gate level control buffer circuit and a transceiving conversion isolation circuit in a9 x 9mm area, and is simple and easy in peripheral circuits. The floating high-voltage stabilizer is arranged in the ultrasonic transceiver chip, positive and negative pulses are completely symmetrical without deformation, output noise is greatly reduced, and second harmonic distortion is greatly reduced; the SOI CMOS technology is also adopted to ensure that the crosstalk between channels is smaller; four kinds of output current can be selected, the automatic thermal protection function is realized, and each group of high voltage integrates a noise reduction diode and a high-voltage clamping diode, so that the transmitting circuit is effectively protected; the logic control circuit is wide in voltage range, can adapt to signals with different voltage levels given by various control units, and has no power-on time sequence requirement.

Referring to fig. 7, 8, 9 and 10, the receiving unit 220 includes a first ultrasonic analog front end chip U5, a second ultrasonic analog front end chip U6, a third ultrasonic analog front end chip U7 and a fourth ultrasonic analog front end chip U8;

the SEN pin, the SCLK pin, the SDATA pin, the D1P pin, the D1M pin, the D2P pin, the D2M pin, the D3P pin, the D3M pin, the D4P pin, the D4M pin, the D5P pin, the D5M pin, the D6P pin, the D6M pin, the D7P pin, the D7M pin, the D8P pin, the D8M pin, the DCLKP pin, the DCLKM pin, the FCLKP pin and the FCLKM pin of the first ultrasonic simulation front-end chip U5 are all connected with the processing unit 230; an ACT1 pin, an ACT2 pin, an ACT3 pin, an ACT4 pin, an ACT5 pin, an ACT6 pin, an ACT7 pin and an ACT8 pin of the first ultrasonic analog front-end chip U5 are connected with an LVout1 pin, an LVout2 pin, an LVout3 pin, an LVout4 pin, an LVout5 pin, an LVout6 pin, an LVout7 pin and an LVout8 pin of the first ultrasonic transceiver chip U1 in a one-to-one manner; the INP1 pin, the INP2 pin, the INP3 pin, the INP4 pin, the INP5 pin, the INP6 pin, the INP7 pin and the INP8 pin of the first ultrasonic analog front-end chip U5 are connected with the ACT1 pin, the ACT2 pin, the ACT3 pin, the ACT4 pin, the ACT5 pin, the ACT6 pin, the ACT7 pin and the ACT8 pin of the first ultrasonic analog front-end chip U5 in a one-to-one manner;

the SEN pin, the SCLK pin, the SDATA pin, the D1P pin, the D1M pin, the D2P pin, the D2M pin, the D3P pin, the D3M pin, the D4P pin, the D4M pin, the D5P pin, the D5M pin, the D6P pin, the D6M pin, the D7P pin, the D7M pin, the D8P pin, the D8M pin, the DCLKP pin, the DCLKM pin, the FCLKP pin and the FCLKM pin of the second ultrasonic simulation front-end chip U6 are all connected with the processing unit 230; an ACT1 pin, an ACT2 pin, an ACT3 pin, an ACT4 pin, an ACT5 pin, an ACT6 pin, an ACT7 pin and an ACT8 pin of the second ultrasonic analog front-end chip U6 are connected with an LVout1 pin, an LVout2 pin, an LVout3 pin, an LVout4 pin, an LVout5 pin, an LVout6 pin, an LVout7 pin and an LVout8 pin of the second ultrasonic transceiver chip U2 in a one-to-one manner; the INP1 pin, the INP2 pin, the INP3 pin, the INP4 pin, the INP5 pin, the INP6 pin, the INP7 pin and the INP8 pin of the second ultrasonic analog front-end chip U6 are connected with the ACT1 pin, the ACT2 pin, the ACT3 pin, the ACT4 pin, the ACT5 pin, the ACT6 pin, the ACT7 pin and the ACT8 pin of the second ultrasonic analog front-end chip U6 in a one-to-one manner;

the SEN pin, the SCLK pin, the SDATA pin, the D1P pin, the D1M pin, the D2P pin, the D2M pin, the D3P pin, the D3M pin, the D4P pin, the D4M pin, the D5P pin, the D5M pin, the D6P pin, the D6M pin, the D7P pin, the D7M pin, the D8P pin, the D8M pin, the DCLKP pin, the DCLKM pin, the FCLKP pin and the FCLKM pin of the third ultrasonic simulation front-end chip U7 are all connected with the processing unit 230; an ACT1 pin, an ACT2 pin, an ACT3 pin, an ACT4 pin, an ACT5 pin, an ACT6 pin, an ACT7 pin and an ACT8 pin of the third ultrasonic analog front-end chip U7 are connected with an LVout1 pin, an LVout2 pin, an LVout3 pin, an LVout4 pin, an LVout5 pin, an LVout6 pin, an LVout7 pin and an LVout8 pin of the third ultrasonic transceiver chip U3 in a one-to-one manner; the INP1 pin, the INP2 pin, the INP3 pin, the INP4 pin, the INP5 pin, the INP6 pin, the INP7 pin and the INP8 pin of the third ultrasonic analog front-end chip U7 are connected with the ACT1 pin, the ACT2 pin, the ACT3 pin, the ACT4 pin, the ACT5 pin, the ACT6 pin, the ACT7 pin and the ACT8 pin of the third ultrasonic analog front-end chip U7 in a one-to-one manner;

the SEN pin, the SCLK pin, the SDATA pin, the D1P pin, the D1M pin, the D2P pin, the D2M pin, the D3P pin, the D3M pin, the D4P pin, the D4M pin, the D5P pin, the D5M pin, the D6P pin, the D6M pin, the D7P pin, the D7M pin, the D8P pin, the D8M pin, the DCLKP pin, the DCLKM pin, the FCLKP pin and the FCLKM pin of the fourth ultrasonic simulation front-end chip U8 are all connected with the processing unit 230; an ACT1 pin, an ACT2 pin, an ACT3 pin, an ACT4 pin, an ACT5 pin, an ACT6 pin, an ACT7 pin and an ACT8 pin of a fourth ultrasonic analog front-end chip U8 are connected with an LVout1 pin, an LVout2 pin, an LVout3 pin, an LVout4 pin, an LVout5 pin, an LVout6 pin, an LVout7 pin and an LVout8 pin of a fourth ultrasonic transceiver chip U4 in a one-to-one manner; the INP1 pin, the INP2 pin, the INP3 pin, the INP4 pin, the INP5 pin, the INP6 pin, the INP7 pin and the INP8 pin of the fourth ultrasonic analog front-end chip U8 are connected with the ACT1 pin, the ACT2 pin, the ACT3 pin, the ACT4 pin, the ACT5 pin, the ACT6 pin, the ACT7 pin and the ACT8 pin of the fourth ultrasonic analog front-end chip U8 in a one-to-one manner.

The model of each ultrasonic analog front-end chip is preferably AFE5809, each AFE5809 is 8 channels, and in this example, 32 channels are taken as an example, and 4 chips are correspondingly arranged. The FPGA chip in the processing unit 230 outputs configuration signals (SCLK, SDATA) to control the working mode of the ultrasound analog front-end chip, and the front-end enable signal SEN is used to enable the ultrasound analog front-end chip. The existing voltage control module (comprising a digital-to-analog conversion circuit and an analog amplification circuit) provides bias voltage STC for the ultrasonic analog front-end chip. The CLKP _ ADC pin, the CLKM _ ADC pin, the CLKP _16X pin and the CLKP _1X pin of each ultrasonic simulation front-end chip are all connected with the existing clock module, and the output front-end clock signals (CLK _ ADC _ p, CLK _ ADC _ n, CLK _16X _ p and CLK _1X _ p) provide clocks required by work for the ultrasonic simulation front-end chip.

The echo signals (RV 1-RV 32) are amplified, compressed, logarithmically processed, IQ demodulated, decimated and analog-to-digital converted by an ultrasonic analog front-end chip to output corresponding LVDS data (D1 _ p-D32 _ p, D1_ n-D32 _ n, DCLK1_ p-DCLK 4_ p, DCLK1_ n-DCLK 4_ n, FCLK1_ p-FCLK 4_ p, FCLK1_ n-FCLK 4_ n) to an FPGA chip in the processing unit 230. For example, RV1 is input from pins ACT1 and INP1 of the ultrasonic analog front-end chip respectively, corresponding outputs D1_ p and D1_ n, RV2 is input from pins ACT2 and INP2 of the ultrasonic analog front-end chip respectively, and corresponding outputs D2_ p and D2_ n, and so on. Meanwhile, 2 sets of differential clock signals (DCLK 1_ p and DCLK1_ n, FCLK1_ p and FCLK1_ n) of each ultrasonic analog front end chip are accessed into the FPGA chip as data synchronization signals and frame synchronization signals.

Each ultrasonic analog front-end chip has a corresponding peripheral circuit, for example, after a pin ACT1 and a pin INP1 of the ultrasonic analog front-end chip are respectively externally connected with a coupling capacitor, the pins are connected with a pin LVout1 of a fourth ultrasonic transceiver chip U4, as shown in fig. 7 to 10.

The AFE5809 integrates a complete Time Gain Control (TGC) imaging path and a Continuous Wave Doppler (CWD) path so that the user can select different power/noise combinations to optimize system performance. The AFE5809 includes an 8-channel Voltage Controlled Amplifier (VCA), a 14-bit analog-to-digital converter (ADC), a CW mixer, and a digital demodulator (DEMOD). The Voltage Controlled Amplifier (VCA) includes a Low Noise Amplifier (LNA), a Voltage Controlled Attenuator (VCAT), a Programmable Gain Amplifier (PGA), and a Low Pass Filter (LPF). The LNA gain is programmable to support an input signal of 250mVpp to 1Vpp, VCAT provides a 40dB attenuation control range, and PGA provides gain options of 24dB and 30 dB. The LPF before the ADC can be configured to 10MHz, 15MHz, 20MHz or 30MHz to support ultrasound applications at different frequencies.

Besides all the functions, the AFE5809 is mainly characterized by integrating a high-performance digital demodulator (demodulator), supporting any sampling rate between 2 and 32 (M = 2-32) and a 16 × M tap full-precision FIR sampling filter (multiphase structure), wherein the sampling precision of an ADC after sampling reaches 16 bits (at most 14 bits in the traditional scheme).

Referring to fig. 11, 12, 13, 14, 15 and 16, the processing unit 230 includes an FPGA (field programmable logic array) chip and a DSP chip DS1P (floating point multi-core digital signal processor), and the FPGA chip includes a first functional module PIF (BANK 7), a second functional module PIE (BANK 6), a third functional module PID (BANK 5), a fourth functional module PIC (BANK 4) and a fifth functional module P1J;

the F7 pin of the first functional module PIF is connected with the CC1 pins of the first ultrasonic transceiving chip U1, the second ultrasonic transceiving chip U2, the third ultrasonic transceiving chip U3 and the fourth ultrasonic transceiving chip U4; the F8 pin of the first functional module PIF is connected with the CC0 pins of the first ultrasonic transceiving chip U1, the second ultrasonic transceiving chip U2, the third ultrasonic transceiving chip U3 and the fourth ultrasonic transceiving chip U4; an H6 pin of the first functional module PIF is connected with EN pins of the first ultrasonic transceiving chip U1, the second ultrasonic transceiving chip U2, the third ultrasonic transceiving chip U3 and the fourth ultrasonic transceiving chip U4; the pins G, F, E, D, C, B, A, D, C, B, A, D, C, B, A, D, C, B, A and A of the first functional module PIF are connected with the pins D1, D2, D3, D4, D5, D6, D7, D8, DCLKP, DCLKM, FCLKP, FCLKM in an LVDS manner; the pin H9, the pin AC13, the pin AA8, the pin AA9 and the pin E9 of the first functional module PIF are all connected with the probe switching device 10; the F9 pin of the first functional module PIF is connected with the SEN pin of the first ultrasonic analog front-end chip U5, the SEN pin of the second ultrasonic analog front-end chip U6, the SEN pin of the third ultrasonic analog front-end chip U7 and the SEN pin of the fourth ultrasonic analog front-end chip U8; the pin G9 of the first functional module PIF is connected with the SCLK pin of the first ultrasonic simulation front-end chip U5, the SCLK pin of the second ultrasonic simulation front-end chip U6, the SCLK pin of the third ultrasonic simulation front-end chip U7 and the SCLK pin of the fourth ultrasonic simulation front-end chip U8; a pin W12 of the first functional module PIF is connected with an SDATA pin of the first ultrasonic analog front-end chip U5, an SDATA pin of the second ultrasonic analog front-end chip U6, an SDATA pin of the third ultrasonic analog front-end chip U7 and an SDATA pin of the fourth ultrasonic analog front-end chip U8;

the pin C, the pin F, the pin AB, the pin AA, the pin D, the pin G, the pin AB, the pin AA, the pin C, the pin E, the pin U, the pin AB, the pin D, the pin T, the pin V and the pin IN _ P, the pin IN _ N, the pin IN _ P and the pin IN _ N of the second functional module PIE (BANK) are connected IN a one-to-one manner; the pins C, B, C, D, E, F, H, J, K, L, M, N, P, N, G and G of the second functional module PIE (BANK) are connected in a one-to-one manner in the form of LVDS signals with the pins D1, D2, D3, D4, D5, D6, D7, D8, DCLKP, DCLKM, FCLKP and FCLKM of the second ultrasonic analog front-end chip U;

an H4 pin, a T5 pin, a C4 pin, a J6 pin, a G4 pin, an R4 pin, a B4 pin, an M1 pin, an F4 pin, an R3 pin, a D4 pin, an L3 pin, an E4 pin, a T3 pin of the third functional module PID (BANK 5), an IN _ P2 pin, an IN _ N2 pin, an IN _ P3 pin, an IN _ N3 pin, an IN _ P4 pin, an IN _ N4 pin, an IN _ P5 pin, an IN _ N5 pin, an IN _ P6 pin, an IN _ N6 pin, an IN _ P7 pin, an IN _ N7 pin, an IN _ P8 pin and an IN _ N8 pin of the second ultrasonic transceiver chip U2 are connected IN a one-to one manner; a pin A, a pin K, a pin V, a pin T, a pin B, a pin K, a pin W, a pin V, a pin A, a pin J, a pin Y, a pin W, a pin B, a pin H, a pin AA, a pin W, and a pin IN _ P, a pin IN _ N, a pin IN _ P, a pin IN _ N, a pin IN _ P, a pin IN _ N, a pin IN _ P, and a pin IN _ N of a third functional module PID (BANK) are connected IN a one-to-one manner; a pin R1, a pin T1, a pin U1, a pin V1, a pin W2, a pin Y1, a pin AA1, a pin AB1, a pin AB2, a pin AC1, a pin AC3, a pin AC4, a pin AD2, a pin AD3, a pin AD4, a pin AD5, a pin P4, a pin P3, a pin AA3, a pin AB3 of the third functional module PID (BANK 5) is connected to a pin D1P, a pin D1M, a pin D2M, a pin D3M, a pin D4M, a pin D5M, a pin D6M, a pin D7 FCLKP, a pin DCLKP, a pin FCLKP, and a pair of the third ultrasonic analog front-end chip U7;

the fourth functional module PIC (BANK) is connected with the G pin, the N pin, the K pin, the R pin, the G pin, the N pin, the K pin, the P pin, the D pin, the N pin, the J pin, the R pin, the E pin, the M pin, the J pin, the R pin and the IN _ P pin, the IN _ N pin, the IN _ P pin and the IN _ N pin IN a one-to-one manner; a G8 pin and an L7 pin of a fourth functional module PIC (BANK 4) are connected with an IN _ P1 pin and an IN _ N1 pin of the second ultrasonic transceiving chip U2 IN a one-to-one mode; an AC pin, an AD pin, an AA pin, an AB pin, an AA pin, an AB pin, an AD pin, an AB pin, an AC pin, a Y pin, an AA pin, an AD pin and a D1 pin, a D2 pin, a D3 pin, a D4 pin, a D5 pin, a D6 pin, a D7 pin, a D8 pin, a DCLKP pin, a DCLKM pin, an FCLKP pin and an FCLKM pin of a fourth functional module PIC (PIC) are connected in a one-to-one manner in a;

the AA pin, the W pin, the R pin, the N pin, the Y pin, the V pin, the P pin, the M pin of the fifth functional module P1, and the RIOTXP pin, the RIOTXN pin, the RIOTXP pin, the RIOTXN pin, the riorxxp pin, the RIORXN pin, the RIORXP pin, the RIORXN pin are connected one to one by one through a coupling capacitor in the manner of LVDS signals; the pins K22, K21, H22, H21, D22, D21, B22 and B21 of the fifth functional module P1J are all connected with the probe switching device 10;

the SGMII1RXP pin, the SGMII1RXN pin, the SGMII1TXP pin, the SGMII1TXN pin, the MDIO pin, and the MDCLK pin of the DSP chip DS1P are all connected to the interface circuit 240.

It should be understood that, because there are many pins of the FPGA chip and one diagram cannot be displayed, the FPGA chip is divided into various functional modules, and other functional modules such as an FPGA power module are also provided therein, and only the modules related to the present embodiment are described here; the DSP chip is configured with other modules such as a memory, a DSP power module, etc., which are prior art and will not be described in detail herein.

The model of the FPGA chip is preferably EP2AGX65DF25C6N, and the model of the DSP chip is preferably TMS320C 6678. When the demodulated LVDS data (D1 _ p-D32 _ p, D1_ n-D32 _ n, DCLK1_ p-DCLK 4_ p, DCLK1_ n-DCLK 4_ n, FCLK1_ p-FCLK 4_ p, FCLK1_ n-FCLK 4_ n) of each channel of the ultrasonic analog front-end chip (U5-U8) is transmitted to the FPGA chip through the LVDS interface, the data amount is already reduced from dozens of K samples at most to hundreds of samples (for example, 512), the FPGA chip can easily store the complete data transmitted/received each channel, and the pulse inversion harmonic data processing is very easily realized (the conventional scheme is very complicated). The LVDS data are transmitted to the DSP chip through an SRIO interface (Serial Rapid IO) after channel sequence arrangement is completed in the FPGA chip. The FPGA chip in the embodiment basically has a bridging effect (Bridge) in the whole platform, so that the FPGA chip with simple design and low resource consumption can be selected and used on a small scale.

The internal signal flow of the FPGA chip is shown in fig. 17: the LVDS data output by the receiving unit 220 is decomposed by the deserializer and then output from 32 channels to corresponding buffers, and I/Q data is output after channel sorting (AMCC _ P8_ SRIO1_ RX _ P, AMCC _ P8_ SRIO1_ RX _ N, AMCC _ P9_ SRIO2_ RX _ P, AMCC _ P9_ SRIO2_ RX _ N, AMCC _ P10_ SRIO3 \\ \/

RX_P、AMCC_P10_SRIO3_RX_N、AMCC_P11_SRIO4_RX_P、AMCC_

P11_SRIO4_RX_N、AMCC_P8_SRIO1_TXC_P、AMCC_P8_SRIO1_TXC_N、AMCC_P9_SRIO2_TXC_P、AMCC_P9_SRIO2_TXC_N、AMCC_P10_SRIO3

The _ TXC _ P, AMCC _ P10_ SRIO3_ TXC _ N, AMCC _ P11_ SRIO4_ TXC _ P, AMCC _ P11_ SRIO4_ TXC _ N) is transmitted to the DSP chip by the SRIO interface (using SRIO protocol). The phase-locked loop is a part of circuit for normal work of the FPGA, provides a global clock and a local clock for the FPGA system, and is a clock source of a digital signal.

The I/Q data preprocessed by the FPGA chip completes advanced algorithms such as I/Q domain beam synthesis, synthetic aperture imaging, blood flow extraction, image processing and the like in the DSP chip. The DSP chip adopts an 8-core processor with the model TMS320C6678, the single-core dominant frequency of the DSP chip is 1.0GHz, the application requirements of portable ultrasound can be met, the power consumption is low, and seamless upgrading can be realized. Compared with the prior art that the advanced algorithm is realized by using an FPGA chip, the embodiment adopts the DSP chip to realize a very complex or special algorithm more easily, and the algorithm is more convenient to change, upgrade, maintain and the like.

The ultrasonic data (DSP _ SGMII _ RX _ P, DSP _ SGMII _ RX _ N, DSP _ SGMII _ TX _ P, DSP _ SGMII _ TX _ N; including two-dimensional B-type data, blood flow data, frequency spectrum data, etc.) processed by the DSP chip is transmitted to the PC through the interface unit 240, and a series of processing such as data storage, post-processing, imaging display, man-machine interaction, etc. is completed on the PC. Because the complex algorithm of the bottom layer is not involved, the performance of the PC is almost not required. Meanwhile, the MDIO pin and the MDCLK pin of the DSP chip communicate with the interface unit 240 through control signals (DSP _ MDIO, DSP _ MDC), the DSP chip configures the operating mode of the interface unit 240 through the control signals, and the interface unit 240 feeds back the operating state information to the DSP chip through the control signals.

It should be understood that the peripheral circuit of the DSP chip includes several capacitors, such as the RIOTXP0 pin to RIOTXP3 pin, the RIOTXN0 pin to RIOTXN3 pin, the RIOTXP0 pin to RIOTXP3 pin, and the RIORXN0 pin to RIORXN3 pin of the DSP chip DS1P, which are respectively connected with the corresponding pins of the fifth functional module P1J through one capacitor; the SGMII1RXP pin, the SGMII1RXN pin, the SGMII1TXP pin, and the SGMII1TXN pin of the DSP chip DS1P are respectively connected to corresponding pins of the interface circuit 240 through a capacitor. The ultrasonic data DSP _ SGMII _ RX _ P, DSP _ SGMII _ RX _ N, DSP _ SGMII _ TX _ P, DSP _ SGMII _ TX _ N becomes DSP _ SGMII _ RXC _ P, DSP _ SGMII _ RXC _ N, DSP _ SGMII _ TXC _ P, DSP _ SGMII _ TXC _ N through corresponding capacitors, and is also ultrasonic data, and the data content is not changed, but direct current is isolated through capacitors.

The interface unit 240 may adopt an EMAC network port (one hundred mega/one giga network port) or a USB2.0 interface, in this embodiment, taking the EMAC network port as an example, please refer to fig. 18, the interface unit 240 includes an ethernet chip U9, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, and a crystal head LAN;

the S _ OUT + pin, the S _ OUT-pin, the S _ IN + pin, the S _ IN-pin, the MDIO pin and the MDC pin of the Ethernet chip U9 are connected with the SGMII1RXP pin, the SGMII1RXN pin, the SGMII1TXP pin, the SGMII1TXN pin, the MDIO pin and the MDCLK pin of the DSP chip DS1P IN a one-to-one manner; the MDI3+ pin of the Ethernet chip U9 is connected with one end of a first resistor R1 and the 9 th pin of the crystal head LAN, the MDI 3-pin of the Ethernet chip U9 is connected with one end of a second resistor R2 and the 8 th pin of the crystal head LAN, the MDI2+ pin of the Ethernet chip U9 is connected with one end of a third resistor R3 and the 2 nd pin of the crystal head LAN, the MDI 2-pin of the Ethernet chip U9 is connected with one end of a fourth resistor R4 and the 3 rd pin of the crystal head LAN, the other end of a first resistor R1 is connected with one end of a first capacitor C1 and the other end of a second resistor R2, the other end of a third resistor R3 is connected with one end of a second capacitor C2 and the other end of a fourth resistor R4, the other end of a first capacitor C1 is connected with the other end of a second capacitor C2 and the ground, the MDI1+ pin of the Ethernet chip U9 is connected with one end of an eighth resistor R1 and the first pin 1 of the crystal head LAN 1 and the first resistor R1 and the seventh pin 1 of the crystal head LAN, one end of a sixth resistor R6 and a10 th pin of the crystal head LAN are connected to the MDI10+ pin of the Ethernet chip U9, one end of a fifth resistor R5 and a11 th pin of the crystal head LAN are connected to the MDI 10-pin of the Ethernet chip U9, the other end of an eighth resistor R8 is connected to one end of a fourth capacitor C4 and the other end of a seventh resistor R7, the other end of a sixth resistor R6 is connected to one end of a third capacitor C3 and the other end of a fifth resistor R5, and the other end of a fourth capacitor C4 is connected to the other end of the third capacitor C3 and the ground.

The model number of the Ethernet chip U9 is preferably MARVELL _88E1111-B2-BAB1C 000; the first resistor R1 to the eighth resistor R8 and the first capacitor C1 to the fourth capacitor C4 form an impedance matching circuit, and the ultrasonic data processed by the DSP chip are transmitted to the PC through the Ethernet chip U9 and the crystal head LAN. The data returned by the PC is also transmitted through signals MDI0_ P to MDI3_ P, MDI0_ N to MDI3_ N, which are data channels for bidirectional communication.

In this embodiment, the probe switching device 10 supports a high-frequency superficial probe with 256 array elements at maximum, and referring to fig. 2, fig. 19, fig. 20 and fig. 21 together, it includes: the device comprises a hot plug detection unit 110, a probe identification unit 120, a driving unit 130 and a plurality of probe sockets (1-n, n is a positive integer); the hot plug detection unit 110 is connected with a plurality of probe sockets and the FPGA chip in the processing unit, the probe identification unit 120 is connected with the drive unit 130 and the FPGA chip in the processing unit, the drive unit 130 is connected with the plurality of probe sockets, and each probe socket is correspondingly externally connected with one probe. When the hot plug detection unit 110 detects that a probe is plugged after being powered on, outputting a corresponding hot plug identification signal probe to the FPGA chip; the probe identification unit 120 scans the identification code of the probe according to the selection signal output by the FPGA and outputs corresponding probe information to the FPGA chip, so that the FPGA chip identifies the type of the probe inserted into the probe socket; the FPGA chip outputs selection signals (HPBSEL 0 and HPBSEL 1), control signals (HHVCT 0-HHVCT 7) of a high-voltage switch in the probe socket, a switch clock signal HHVCK and a switch enabling signal HHVLE according to work requirements, the probe identification unit 120 generates probe selection signals (probe 1_ CS-probe 4_ CS) according to the selection signals, the driving unit 130 drives and amplifies the probe selection signals (probe 1_ CS-probe 4_ CS), the switch clock signal HHVCK, the switch enable signal HHVLE and the array element driving control signals (HHVCT 0-HHVCT 7) to output corresponding probe enable signals (probe 1_ EN-probe 4_ EN), a probe switch clock signal (probe _ CLK), a probe switch enable signal (probe _ LE) and an array element selection signal (also called high-voltage switch control signals, D0-D7) to the high-voltage switch part in the corresponding probe socket, and accordingly excites the corresponding transducer elements to complete the emission of ultrasonic waves.

In this embodiment, taking external 4 probes as an example, 4 probe sockets are correspondingly disposed.

The hot plug detection unit 110 includes a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13 and a fifth capacitor C5; one end of the ninth resistor R9 is connected with one end of the fifth capacitor C5, one end of the tenth resistor R10, one end of the eleventh resistor R11, one end of the twelfth resistor R12, one end of the thirteenth resistor R13 and the W10 pin of the first functional module PIF; the other end of the ninth resistor R9 is connected with a 5V power supply end, the other end of the fifth capacitor C5 is grounded, the other end of the tenth resistor R10 is connected with the first probe socket A, the other end of the eleventh resistor R11 is connected with the second probe socket B, the other end of the twelfth resistor R12 is connected with the third probe socket C, and the other end of the thirteenth resistor R13 is connected with the fourth probe socket D.

When the probe plug is arranged on each probe socket, a corresponding plug signal is generated, sb _ prb1 is the plug signal of the first probe socket A, sb _ prb2 is the plug signal of the second probe socket B, and so on. When a probe is inserted, the corresponding sb _ prb is connected to GND, the voltage of the sb _ prb is pulled up by R9 when the probe is pulled out, so that the voltage of the hot plug identification signal probe changes, which is a voltage division network of the voltage. It should be understood that if the number of the probe sockets is increased or decreased, the number of the resistors arranged on the right side can be correspondingly increased or decreased.

Referring to fig. 20, the probe identification unit 120 includes a decoding chip U10, a multiplexer U11, and a sixth capacitor C6; the A pin of the decoding chip U10 is connected with the A0 pin of the multiplexer U11 and the AA8 pin of the first functional module PIF, the B pin of the decoding chip U10 is connected with the A1 pin of the multiplexer U11 and the AA9 pin of the first functional module PIF, and the A pin of the decoding chip U10 is connected with the A1 pin of the multiplexer U11 and the AA9 pin of the first functional module PIF

A foot part,

A foot part,

Foot and

the feet are all connected with the driving unit 130; the COM pin of the multiplexer U11 is connected with the E9 pin of the first functional module, the EN pin of the multiplexer U11 is connected with the V + pin, one end of the sixth capacitor C6 and the 5V power supply end; the NO1 pin, the NO2 pin, the NO3 pin and the NO4 pin of the multiplexer U11 are connected with the first probe socket A, the second probe socket B, the third probe socket C and the fourth probe socket D in a one-to-one mode; the GND pin of the multiplexer U11 is connected to the other terminal of the sixth capacitor C6 and ground.

The model of the decoding chip U10 is preferably MC74VHC139DT, and the model of the multiplexer U11 is preferably MAX4634 EUB. After the power-on and the power-on of the FPGA chip are started, the FPGA chip outputs selection signals (HPBSEL 0 and HPBSEL 1) to sequentially scan 4 probe sockets, if identification codes (WireA-WireD) of the probe sockets can be acquired, an identification signal one _ wire is fed back to the FPGA chip, the type of a probe inserted into the probe socket can be identified, and if no identification code exists, the probe socket is empty. After the FPGA chip is identified, the corresponding probe can be selected to work according to the work requirement, and the selection signals (HPBSEL 0 and HPBSEL 1) are output to the decoding chip U10 to generate corresponding probe selection signals (probe 1_ CS-probe 4_ CS). Drive enhancement is required due to the weaker probe selection signal.

Referring to fig. 21, the driving unit 130 includes a first driving chip U12 and a second driving chip U13; the pins B5, B6, B7 and B8 of the first driver chip U12 and the pin B10 of the decoder chip U10

A foot part,

A foot part,

Foot and

the feet are connected in a one-to-one way; a pin B3 of the first drive chip U12 is connected with a pin B4 and a pin H9 of the first functional module PIF, a pin B1 of the first drive chip U12 is connected with a pin B2 and a pin AC13 of the first functional module PIF, a pin A3 of the first drive chip U12 is connected with a pin A4 and a probe socket, and a pin A1 of the first drive chip U12 is connected with a pin A2 and the probe socket; the A5 pin, the A6 pin, the A7 pin and the A8 pin of the first drive chip U12 are connected with the first probe socket A, the second probe socket B, the third probe socket C and the fourth probe socket D in a one-to-one manner; the pins B1, B2, B3, B4, B5, B6, B7 and B8 of the second driving chip U13 are connected with the pins K22, K21, H22, H21, D22, D21, B22 and B21 of the fifth functional module P1J in a one-to-one manner; a1 pin, A2 pin, A3 pin, A4 pin, A5 pin, A6 pin, A7 pin and A8 pin of the second drive chip U13 are connected with the probe sockets.

After the first driving chip U12 drives and enhances the probe selection signals (probe 1_ CS to probe 4_ CS), probe enabling signals (probe 1_ EN to probe 4_ EN) are output to the high-voltage switches of the corresponding probe sockets, so that the corresponding probes are enabled to work. The second driving chip U13 drives and enhances array element driving control signals (HHVCT 0-HHVCT 7) output by the FPGA chip to output array element selection signals (D0-D7) so as to control corresponding transducer elements in the probe to work, and therefore ultrasonic signals are emitted. The states of the signals before and after driving are unchanged, but the driving capability is enhanced. A switch clock signal HHVCK and a switch enable signal HHVLE of a high-voltage switch given by the FPGA chip are changed into a probe switch clock signal (probe _ CLK) and a probe switch enable signal (probe _ LE) through a first driving core U12.

In the embodiment, a plurality of probes can be switched, when the probe 1_ EN is effective, the probe 2_ EN is ineffective, and only one probe can work. The probe socket is a conventional one, and the first probe socket a and the first probe 1 are taken as examples, as shown in fig. 22. High voltage switches are shown in the dashed boxes for channel and array element selection. The selection of which probe works is carried out by probe enable signals (probe 1_ EN-probe 4_ EN), and the selection of which transducer element works is carried out by array element selection signals (D0-D7). It should be understood that the high voltage switch may be disposed on the probe switching device, or may be disposed within the probe, without limitation,

in summary, compared with the conventional hardware scheme, the portable color ultrasound device provided by the invention adopts a TI ultrasonic front-end chip (model number is AFE 5809) to replace AFE5805/5808 and other chips, simplifies the design of an FPGA by using a built-in digital demodulator with excellent performance, and can realize functions of I/Q domain focusing, pulse inversion harmonic data processing and the like with infinite high precision. By transmitting the data preprocessed by the FPGA chip to the DSP chip to perform advanced algorithms such as complex beam forming algorithm, blood flow extraction and image processing, the data volume processed by the DSP chip becomes very small and can be directly transmitted to the PC through a USB2.0 or EMAC (Internet access controller), thereby greatly reducing the data volume transmitted to the PC and greatly reducing the requirements on the transmission protocol and the interface performance of the PC.

The division of the functional modules is only used for illustration, and in practical applications, the functions may be distributed by different functional modules according to needs, that is, the functions may be divided into different functional modules to complete all or part of the functions described above.

It should be understood that equivalents and modifications of the technical solution and inventive concept thereof may occur to those skilled in the art, and all such modifications and alterations should fall within the scope of the appended claims.

Claims

1. The utility model provides a portable color Doppler ultrasound device, connects probe auto-change over device and PC, its characterized in that, including receiving and dispatching isolation element, receiving element, processing unit and interface unit: the receiving and transmitting isolation unit is connected with the receiving unit, the processing unit and the probe switching device, the processing unit is connected with the receiving unit and the interface unit, and the interface unit is externally connected with a PC;

and the interface unit transmits the preprocessed ultrasonic data to a PC.

2. The portable color Doppler ultrasound device according to claim 1, wherein the transceiver isolation unit comprises a first ultrasound transceiver chip, a second ultrasound transceiver chip, a third ultrasound transceiver chip and a fourth ultrasound transceiver chip;

3. The portable color Doppler ultrasound device according to claim 2, wherein the receiving unit comprises a first ultrasonic analog front end chip, a second ultrasonic analog front end chip, a third ultrasonic analog front end chip and a fourth ultrasonic analog front end chip;

4. The portable color Doppler ultrasound device according to claim 3, wherein the processing unit comprises a FPGA chip and a DSP chip, and the FPGA chip comprises a first functional module, a second functional module, a third functional module, a fourth functional module and a fifth functional module;

5. The portable color Doppler ultrasound device according to claim 4, wherein the interface unit comprises an Ethernet chip, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor and a crystal head;

6. A color Doppler ultrasound system comprising a PC, characterized by further comprising at least two probes, a probe switching device and a portable color Doppler ultrasound device according to any one of claims 1 to 5; the portable color Doppler ultrasound device is connected with the probe switching device and the PC;

7. The color Doppler ultrasound system according to claim 6, wherein the probe switching device comprises a hot plug detection unit, a probe identification unit, a driving unit and a plurality of probe sockets; the hot plug detection unit is connected with each probe socket and the FPGA chip in the processing unit, the probe identification unit is connected with the driving unit and the FPGA chip, the driving unit is connected with each probe socket and the FPGA chip, and each probe socket is correspondingly externally connected with one probe;

8. The color Doppler ultrasound system according to claim 7, wherein the probe socket comprises a first probe socket, a second probe socket, a third probe socket, and a fourth probe socket;

9. The color Doppler ultrasound system according to claim 8, wherein the probe identification unit comprises a decoding chip, a multiplexer and a sixth capacitor;

A foot part,

A foot part,

Foot and

10. The color Doppler ultrasound system according to claim 9, wherein the driving unit comprises a first driving chip and a second driving chip;

pins B5, B6, B7 and B8 of the first driver chip and the decoder chip

A foot part,

A foot part,

Foot and